Planar high-voltage device

Abstract

The embodiment of the utility model discloses a planar high-voltage device. The planar high-voltage device comprises a semiconductor substrate, a P-type isolation layer, an N-type drift layer, a gate region, a source region, a drain region and a body region, the P-type isolation layer is located above the semiconductor substrate, the N-type drift layer is located above the P-type isolation layer, the gate region, the source region, the drain region and the body region are located above the N-type drift layer, the body region, the gate region and the drain region are arranged in the horizontal direction, and the N-type drift layer is located above the body region. The gate region is located between the body region and the drain region, and the source region is located above the body region and adjacent to the gate region; the gate region comprises a gate deep groove, a first gate oxide layer and a first polysilicon gate, wherein the first gate oxide layer and the first polysilicon gate are located in the gate deep groove. The first polysilicon gate is wrapped by the first gate oxide layer. A shallow slot isolation region is arranged between the gate region and the drain region, and the depth of the gate deep slot is greater than that of the body region and the shallow slot isolation region. According to the embodiment of the utility model, the on-resistance of the planar high-voltage DMOS device can be obviously reduced, and the withstand voltage value of the device can be obviously increased at the same time.

Description

Technical Field

[0001] The embodiment of the utility model relates to the technical field of integrated circuits, and in particular to a planar high-voltage device. Background Art

[0002] For the design of high-voltage devices in the field of high-voltage integrated circuits, in order to facilitate integration with complementary metal oxide semiconductor (CMOS) devices, the traditional method is to choose a planar polysilicon gate process, which leads to a significant increase in on-resistance while increasing the withstand voltage of the device. In other words, traditional planar laterally diffused metal oxide semiconductor (LDMOS) devices have the problems of large on-resistance and low withstand voltage.

[0003] In order to ensure that the withstand voltage of high-voltage devices is not affected while reducing the on-resistance, the doping morphology of the withstand voltage drift region is optimized, the manufacturing method of the withstand voltage region is optimized, or different doping methods are used. However, these methods cannot achieve a better balance between increasing the withstand voltage and reducing the on-resistance, and cannot effectively solve the problem of increasing the withstand voltage and reducing the on-resistance. Utility Model Content

[0004] The utility model provides a planar high-voltage device, which can significantly improve the withstand voltage value of the device and reduce the on-resistance of the device.

[0005] In a first aspect, an embodiment of the utility model provides a planar high voltage device, comprising:

[0006] Semiconductor substrate;

[0007] A P-type isolation layer, located above the semiconductor substrate;

[0008] An N-type drift layer, located above the P-type isolation layer;

[0009] A gate region, a source region, a drain region and a body region are located above the N-type drift layer; the body region, the gate region and the drain region are arranged in a horizontal direction, and the gate region is located between the body region and the drain region, and the source region is located above the body region and adjacent to the gate region;

[0010] The gate region includes a gate deep trench, a first gate oxide layer and a first polysilicon gate located in the gate deep trench, and the first gate oxide layer wraps the first polysilicon gate;

[0011] A shallow trench isolation region is provided between the gate region and the drain region, and the depth of the gate deep trench is greater than the depth of the body region and the shallow trench isolation region.

[0012] Optionally, a second polysilicon gate is disposed above the shallow trench isolation region, and the first polysilicon gate is connected to the gate metal layer through a vertical silicon gate contact hole, and the second polysilicon gate is connected to the gate metal layer through a planar silicon gate contact hole.

[0013] Optionally, the depth of the gate deep trench is in the range of 0.3 to 3 um, and / or the thickness of the first gate oxide layer is in the range of 20 nm to 1000 nm.

[0014] Optionally, the source region and the drain region both include an N-type heavily doped region, the N-type heavily doped region in the source region is connected to the source metal layer through a contact hole; the N-type heavily doped region in the drain region is connected to the drain metal layer through a contact hole.

[0015] Optionally, the body region includes a body pole deep trench and a P-type heavily doped region located in the body pole deep trench, and the P-type heavily doped region in the body pole deep trench is connected to the body pole metal layer through a contact hole; the depth of the body pole deep trench is less than the depth of the body region.

[0016] Optionally, an upper surface of the P-type heavily doped region in the body region is lower than an upper surface of the N-type heavily doped region in the source region.

[0017] Optionally, the depth of the body region ranges from 0.3 to 3 um, and / or the depth difference between the upper surface of the P-type heavily doped region in the body region and the upper surface of the N-type heavily doped region in the source region ranges from 0.3 to 3 um.

[0018] Optionally,

[0019] The upper surfaces of the P-type heavily doped region in the body region and the N-type heavily doped region in the source region are flush and have the same depth.

[0020] Optionally, it further includes a P-type well region, which is located above the P-type isolation layer and adjacent to the N-type drift layer in a horizontal direction; the P-type well region is connected to the outside through a contact hole.

[0021] Optionally, the semiconductor substrate further includes an N-type buried layer, and the N-type buried layer is located between the semiconductor substrate and the P-type isolation layer.

[0022] In the technical solution of the utility model, a planar high-voltage device is provided, including a semiconductor substrate, a P-type isolation layer, an N-type drift layer, a gate region, a source region, a drain region and a body region, wherein the P-type isolation layer is located above the semiconductor substrate, the N-type drift layer is located above the P-type isolation layer, the gate region, the source region, the drain region and the body region are located above the N-type drift layer, the body region, the gate region and the drain region are arranged in a horizontal direction, and the gate region is located between the body region and the drain region, the source region is located above the body region and adjacent to the gate region; the gate region includes a gate deep groove and a first gate oxide layer and a first polysilicon gate located in the gate deep groove, the first gate oxide layer wraps the first polysilicon gate; a shallow trench isolation region is provided between the gate region and the drain region, and the depth of the gate deep groove is greater than the depth of the body region and the shallow trench isolation region. The embodiments of the utility model solve the problem that existing planar high-voltage devices are unable to effectively improve the withstand voltage while reducing the on-resistance. The deep trench gate structure can be used in conjunction with a P-type isolation layer to regulate the conductive channel in the N-type drift layer, thereby significantly reducing the on-resistance of the planar high-voltage DMOS device and significantly increasing the withstand voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of a planar high voltage device provided by an embodiment of the utility model;

[0024] Figure 2 It is a schematic diagram of the structure of another planar high voltage device provided by an embodiment of the utility model;

[0025] Figure 3 This is a flow chart for preparing a planar high voltage device provided by an embodiment of the utility model;

[0026] Figure 4 yes Figure 3 The structural flow chart of the planar high voltage device preparation process shown;

[0027] Figure 5 This is a flow chart of another preparation of a planar high voltage device provided by an embodiment of the utility model;

[0028] Figure 6 yes Figure 5 The structural flow chart of the planar high voltage device preparation process shown;

[0029] In the figure:

[0030] 100 - semiconductor substrate, 200 - P-type isolation layer, 300 - N-type drift layer, 400 - gate region, 410 - gate deep trench, 420 - first gate oxide layer, 430 - first polysilicon gate, 500 - source region, 600 - drain region, 700 - body region, 710 - body deep trench, 800 - second polysilicon gate;

[0031] 10- shallow trench isolation area, 21- vertical silicon gate contact hole, 22- planar silicon gate contact hole, 30- contact hole. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0033] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second" and the like are only used for descriptive purposes and do not represent any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances.

[0034] The term "including" and its variations used in the present invention are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment".

[0035] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish the corresponding contents, and are not used to limit the order or interdependence.

[0036] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0037] Figure 1 This is a schematic diagram of the structure of a planar high voltage device provided by the embodiment of the utility model, referring to Figure 1The planar high voltage device comprises: a semiconductor substrate 100; a P-type isolation layer 200, located above the semiconductor substrate 100; an N-type drift layer 300, located above the P-type isolation layer 200; a gate region 400, a source region 500, a drain region 600 and a body region 700, located above the N-type drift layer 300; the body region 700, the gate region 400 and the drain region 600 are arranged in a horizontal direction, and the gate region 40 is located between the body region 700 and the drain region 600, and the source region 500 is located between the body region 700 and the drain region 600. 00 is located above the body region 700 and adjacent to the gate region 400; the gate region 400 includes a gate deep trench 410 and a first gate oxide layer 420 and a first polysilicon gate 430 located in the gate deep trench 410, and the first gate oxide layer 420 wraps the first polysilicon gate 430; a shallow trench isolation region 10 is arranged between the gate region 400 and the drain region 600, and a depth D1 of the gate deep trench 410 is greater than a depth D2 of the body region 700 and a depth D3 of the shallow trench isolation region 10.

[0038] First, the planar high-voltage device in the embodiment of the utility model is a high-voltage diffused metal oxide semiconductor (DMOS) device, wherein the horizontal direction refers to the direction parallel to the surface of the semiconductor substrate 100, the body region 700, the gate region 400 and the drain region 600 are arranged in the horizontal direction above the N-type drift region 30, and the source region 500 is located above the body region 700 and adjacent to the gate region 400, indicating that the device is essentially a planar device. Specifically, in the embodiment of the utility model, the gate region 400 includes a gate deep groove 410, a first gate oxide layer 420 and a first polysilicon gate 430 located in the gate deep groove 410, which constitute a deep groove gate structure. By using the deep groove gate structure, the on-resistance of the high-voltage DMOS device can be significantly reduced, and the withstand voltage value of the device can be significantly increased. In addition, a shallow trench isolation region 10 is set between the gate region 400 and the drain region 600, and the shallow trench can be used to effectively cut off the electrical connection between the gate and the drain, so as to achieve electrical insulation and avoid short circuit and leakage problems.

[0039] In addition, based on the above-mentioned deep trench gate structure and shallow trench isolation structure, and the depth D1 of the gate deep trench 410 is greater than the depth D2 of the body region 700 and the depth D3 of the shallow trench isolation region 10, it can be known that the lateral conductive channel between the source region 500 and the drain region 600 formed in the N-type drift region 300 of the high-voltage DMOS device in the embodiment of the utility model will be blocked to a certain extent by the deep trench gate structure and the shallow trench isolation structure, making the lateral conductive channel path longer and more tortuous. Therefore, the embodiment of the utility model sets a P-type isolation layer 200 between the semiconductor substrate 100 and the N-type drift layer 300, and the flow area of ​​the carriers in the N-type drift region 300 can be isolated by the P-type isolation layer 200, thereby improving the problem of the long and tortuous conductive channel path caused by the deep trench gate structure and the shallow trench isolation structure, further improving the voltage resistance of the device while reducing the on-resistance.

[0040] In the above technical scheme, the planar high voltage device is provided with a semiconductor substrate, a P-type isolation layer, an N-type drift layer, a gate region, a source region, a drain region and a body region, wherein the P-type isolation layer is located above the semiconductor substrate, the N-type drift layer is located above the P-type isolation layer, the gate region, the source region, the drain region and the body region are located above the N-type drift layer, the body region, the gate region and the drain region are arranged in a horizontal direction, and the gate region is located between the body region and the drain region, the source region is located above the body region and adjacent to the gate region; the gate region includes a gate deep groove and a first gate oxide layer and a first polysilicon gate located in the gate deep groove, the first gate oxide layer wraps the first polysilicon gate; a shallow trench isolation region is provided between the gate region and the drain region, and the depth of the gate deep groove is greater than the depth of the body region and the shallow trench isolation region. The embodiment of the utility model solves the problem that the existing planar high voltage device cannot solve the problem of reducing the on-resistance while improving the withstand voltage, and can use the deep trench gate structure to cooperate with the P-type isolation layer to regulate the conductive channel in the N-type drift layer, thereby significantly reducing the on-resistance of the planar high voltage DMOS device, and significantly increasing the withstand voltage value of the device.

[0041] In an alternative embodiment, continue to refer to Figure 1 A second gate oxide layer (not shown in the figure) and a second polysilicon gate 800 are sequentially arranged above the shallow trench isolation region 10. The first polysilicon gate 430 is connected to the gate metal layer (not shown in the figure) through the longitudinal silicon gate contact hole 21, and the second polysilicon gate 800 is connected to the gate metal layer (not shown in the figure) through the planar silicon gate contact hole 22.

[0042] Here, the first polysilicon gate 430 substantially forms a deep trench gate structure, and the second polysilicon gate 800 disposed above the shallow trench isolation region 10 forms a planar gate structure. The planar gate structure can serve as a field plate to improve the withstand voltage of the planar high-voltage DMOS device.

[0043] In a specific embodiment, continue to refer to Figure 1 The depth D1 of the gate deep trench 410 is in the range of 0.3-3 um, and / or the thickness D4 of the first gate oxide layer 420 is in the range of 20 nm-1000 nm.

[0044] In a specific embodiment, continue to refer to Figure 1 The source region 500 and the drain region 600 both include an N-type heavily doped region N+. The N-type heavily doped region N+ in the source region 500 is connected to the source metal layer (not shown in the figure) through a contact hole 30; the N-type heavily doped region N+ in the drain region 600 is connected to the drain metal layer (not shown in the figure) through a contact hole 30.

[0045] In a specific embodiment, continue to refer to Figure 1The body region 700 includes a body deep trench 710 and a P-type heavily doped region P+ located in the body deep trench 710 . The P-type heavily doped region P+ in the body deep trench 710 is connected to the body metal layer (not shown in the figure) through a contact hole 30 . The depth D5 of the body deep trench 710 is less than the depth D2 of the body region 700 .

[0046] In this embodiment, the depth D5 of the body deep trench 710 is less than the depth D2 of the body region 700. In essence, the P+ deep hole contact window is formed by using the P-type heavily doped region P+ to form a larger contact area with the body region 700. Therefore, when the high-voltage device is used in a space scene and the body region 700 absorbs a large number of holes generated by cosmic rays, the holes can be exported as soon as possible, thereby reducing the generation of large BJT currents and improving the life of the device. It should also be added that the bottom of the P+ deep hole contact window formed by the P-type heavily doped region P+ can form an ohmic contact by p+ injection or preparation of a silicide film layer to ensure good conductivity.

[0047] In an alternative embodiment, continue to refer to Figure 1 , the upper surface of the P-type heavily doped region P+ in the body region 700 is lower than the upper surface of the N-type heavily doped region N+ in the source region 500 .

[0048] In this embodiment, the upper surface of the P-type heavily doped region P+ in the body region 700 is set lower than the upper surface of the N-type heavily doped region N+ in the source region 500. This can reduce the vertical height of the P-type heavily doped region P+ in the body region 700, thereby enabling the additional holes to be extracted as quickly as possible, which helps to reduce the large current of the BJT.

[0049] In a specific embodiment, continue to refer to Figure 1 , the depth D2 of the body region 700 ranges from 0.3 to 3 um, and / or the depth difference ΔD between the upper surface of the P-type heavily doped region P+ in the body region 700 and the upper surface of the N-type heavily doped region N+ in the source region 500 ranges from 0.3 to 3 um.

[0050] Figure 2 is a schematic diagram of the structure of another planar high voltage device provided by the embodiment of the utility model, referring to Figure 2 In another embodiment of the present invention, optionally, the upper surface of the P-type heavily doped region P+ in the body region 700 is flush with the upper surface of the N-type heavily doped region N+ in the source region 500 and they have the same depth.

[0051] Continue to refer Figure 1 and Figure 2 In a specific embodiment of the present utility model, the planar high-voltage device further includes a P-type well region PW, which is located above the P-type isolation layer 200 and is adjacent to the N-type drift layer 300 in a horizontal direction; the P-type well region PW is connected to the outside through a contact hole 30.

[0052] Here, the P-type well region PW is connected to the outside through the contact hole 30, with the purpose of forming a longitudinal electric field by applying an appropriate voltage to the P-type isolation layer 200 from the outside, thereby realizing the P-type isolation layer 200 to repel and block the carriers in the N-type drift region 300, thereby achieving an isolation effect.

[0053] Continue to refer Figure 1 and Figure 2 In other embodiments of the present invention, the semiconductor substrate 100 further includes an N-type buried layer 900 , and the N-type buried layer 900 is located between the semiconductor substrate 100 and the P-type isolation layer 200 .

[0054] Among them, the N-type buried layer 900 can also achieve an isolation effect. It can shield the impurity ions in the semiconductor substrate 100. At the same time, it can also suppress the generation of current and effectively limit the leakage current, thereby cooperating with the P-type isolation layer 200 to form a horizontal conductive channel in the N-type drift region 300.

[0055] It should be noted that in the embodiments of the present invention, the concentrations of all doping regions cover the concentration range of 1*e14 to 1*e22, and the P-type isolation layer 200, N-type drift layer 300, deep trench gate structure, etc. in the embodiments of the present invention are not limited to specific manufacturing methods, and any manufacturing method and doping method that forms the above-mentioned concentration range fall within the protection scope of this application.

[0056] Based on the same concept, the embodiment of the present utility model also provides a method for preparing a planar high voltage device, which is used to prepare any planar high voltage device provided by the embodiment of the present utility model. Specifically, Figure 3 This is a flow chart of the preparation of a planar high voltage device provided by an embodiment of the utility model. Figure 4 yes Figure 3 The structural flow chart of the planar high voltage device preparation process is shown, wherein: Figure 4 Example structure preparation process corresponds to Figure 1 The planar high voltage device shown in the reference Figure 1-Figure 4 , the preparation method comprises:

[0057] S110, providing a semiconductor substrate;

[0058] For details, please refer to Figure 4 Figure a) in .

[0059] S120, growing an epitaxial layer of a first preset thickness on the semiconductor substrate;

[0060] For details, please refer to Figure 4 Figure a) in .

[0061] S130, performing ion implantation within a preset depth range of the epitaxial layer to form a P-type isolation region;

[0062] For details, please refer to Figure 4 b) Figure in .

[0063] S140, etching and filling the active area on the surface of the epitaxial layer to form a shallow trench isolation area;

[0064] For details, please refer to Figure 4 Figure c) in .

[0065] S150, performing ion implantation and diffusion in the non-shallow trench isolation region of the epitaxial layer, so that the epitaxial layer forms an N-type drift layer;

[0066] For details, please refer to Figure 4 Figure c) in .

[0067] S160, performing ion implantation in a first preset region of the N-type drift layer to form a body region;

[0068] For details, please refer to Figure 4 Figure d) in the figure.

[0069] S170, etching is performed in a second preset region of the N-type drift layer to form a gate deep groove, and a first gate oxide layer and a first polysilicon gate are sequentially prepared in the gate deep groove to form a gate region; the first gate oxide layer wraps the first polysilicon gate;

[0070] For details, please refer to Figure 4 Figure d) in the figure.

[0071] S180. Perform ion implantation in a first preset area of ​​the body region and a third preset area of ​​the N-type drift layer to form a source region and a drain region, respectively; wherein the body region, the gate region and the drain region are arranged in a horizontal direction, and the gate region is located between the body region and the drain region, the source region is located above the body region and adjacent to the gate region; and the shallow trench isolation region is located between the gate region and the drain region.

[0072] For details, please refer to Figure 4 Figure d) in the figure.

[0073] It should be noted that when the specific region is formed by ion implantation in the above steps, the implanted ions include trivalent elements or pentavalent elements, and those skilled in the art can make judgments based on the specific specific region, wherein pentavalent elements may include boron, indium, etc., and trivalent elements may include phosphorus, antimony, arsenic, etc. Exemplarily, the P-type isolation region may be formed by implanting indium elements in step S130.

[0074] In addition, for the planar high-voltage device provided by the embodiment of the utility model, it can also be divided into a high-voltage planar high-voltage device and a low-voltage planar high-voltage device according to the specific voltage resistance. For the low-voltage planar high-voltage device, the depth requirement for the P-type isolation layer 200 is not high, and the P-type isolation layer 200 can be directly implemented to a specific depth through the ion implantation process step. For the high-voltage planar high-voltage device, the thickness of its N-type drift region 300 should be thicker, and a deeper depth cannot be reached directly through the ion implantation process step, and the P-type isolation layer 200 of the high-voltage planar high-voltage device cannot be prepared directly through ion implantation. In view of this, the embodiment of the utility model also provides a method for preparing a planar high-voltage device.

[0075] Figure 5 is a flow chart of another preparation of a planar high voltage device provided by an embodiment of the utility model, Figure 6 yes Figure 5 The structural flow chart of the planar high voltage device preparation process is shown in FIG. Figure 6 Example structure preparation process corresponds to Figure 1 The planar high voltage device shown in the reference Figure 1 , Figure 2 , Figure 5 and Figure 6 , the preparation method comprises:

[0076] S210, providing a semiconductor substrate;

[0077] For details, please refer to Figure 6 Figure a) in .

[0078] S211, performing photolithography and ion implantation on the semiconductor substrate to form an N-type buried layer.

[0079] For details, please refer to Figure 6 Figure a) in .

[0080] S220, growing an epitaxial layer of a first preset thickness on the semiconductor substrate;

[0081] For details, please refer to Figure 6 b) Figure in .

[0082] S230, performing ion implantation within a preset depth range of the epitaxial layer to form a P-type isolation region;

[0083] For details, please refer to Figure 6 b) Figure in .

[0084] S231 , growing an epitaxial layer of a second preset thickness on the epitaxial layer.

[0085] For details, please refer to Figure 6In this embodiment, by first forming an epitaxial layer of a certain thickness in step S220, forming a P-type isolation region by ion implantation, and then preparing another epitaxial layer, the thickness of the P-type isolation layer 200 can be made thicker, which is conducive to obtaining a device with higher withstand voltage.

[0086] S240, etching and filling the active area on the surface of the epitaxial layer to form a shallow trench isolation area;

[0087] For details, please refer to Figure 6 Figure d) in the figure.

[0088] S250, performing ion implantation and diffusion in the non-shallow trench isolation region of the epitaxial layer, so that the epitaxial layer forms an N-type drift layer;

[0089] For details, please refer to Figure 6 Figure d) in the figure.

[0090] S260, performing ion implantation in a first preset region of the N-type drift layer to form a body region;

[0091] For details, please refer to Figure 6 Figure e) in .

[0092] S261. Perform ion implantation in a second preset area of ​​the body region to form a body deep trench and a P-type heavily doped region in the body deep trench; the depth of the body deep trench is less than the depth of the body region.

[0093] For details, please refer to Figure 6 Figure e) in .

[0094] S270, etching is performed in a second preset area of ​​the N-type drift layer to form a gate deep groove, and a first gate oxide layer and a first polysilicon gate are sequentially prepared in the gate deep groove to form a gate region; the first gate oxide layer wraps the first polysilicon gate;

[0095] For details, please refer to Figure 6 Figure e) in .

[0096] S271. Prepare a second gate oxide layer and a second polysilicon gate in sequence above the shallow trench isolation region.

[0097] For details, please refer to Figure 6 Figure e) in .

[0098] S280. Perform ion implantation in a first preset area of ​​the body region and a third preset area of ​​the N-type drift layer to form a source region and a drain region, respectively; wherein the body region, the gate region and the drain region are arranged in a horizontal direction, and the gate region is located between the body region and the drain region, the source region is located above the body region and adjacent to the gate region; and the shallow trench isolation region is located between the gate region and the drain region.

[0099] For details, please refer to Figure 6 Figure e) in .

[0100] In the above two preparation method embodiments, it is also necessary to add that after the device is prepared by the above preparation method, in order to ensure the normal use of the device, the high-voltage device needs to be connected to the outside, that is, the metal electrode needs to be connected. Therefore, after step S180 or S280, the following steps need to be added: performing a back-end process to form a plurality of contact holes, and connecting each electrode of the device to the corresponding metal layer through the contact holes. Specifically, Figure 1 and Figure 2 As shown, the first polysilicon gate 430 is connected to the gate metal layer (not shown in the figure) through the longitudinal silicon gate contact hole 21, and the second polysilicon gate 800 is connected to the gate metal layer (not shown in the figure) through the planar silicon gate contact hole 22; the N-type heavily doped region N+ in the source region 500 is connected to the source metal layer (not shown in the figure) through the contact hole 30; the N-type heavily doped region N+ in the drain region 600 is connected to the drain metal layer through the contact hole 30; and the P-type heavily doped region P+ in the body deep trench 710 is connected to the body metal layer through the contact hole 30.

[0101] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A planar high voltage device, characterized in that: include: Semiconductor substrate; A P-type isolation layer, located above the semiconductor substrate; An N-type drift layer, located above the P-type isolation layer; A gate region, a source region, a drain region and a body region are located above the N-type drift layer; the body region, the gate region and the drain region are arranged in a horizontal direction, and the gate region is located between the body region and the drain region, and the source region is located above the body region and adjacent to the gate region; The gate region includes a gate deep trench, a first gate oxide layer and a first polysilicon gate located in the gate deep trench, and the first gate oxide layer wraps the first polysilicon gate; A shallow trench isolation region is provided between the gate region and the drain region, and the depth of the gate deep trench is greater than the depth of the body region and the shallow trench isolation region.

2. The planar high voltage device according to claim 1, characterized in that: A second gate oxide layer and a second polysilicon gate are sequentially arranged above the shallow trench isolation region. The first polysilicon gate is connected to the gate metal layer through a vertical silicon gate contact hole, and the second polysilicon gate is connected to the gate metal layer through a planar silicon gate contact hole.

3. The planar high voltage device according to claim 1, characterized in that: The depth of the gate deep trench is in the range of 0.3 to 3 um, and / or the thickness of the first gate oxide layer is in the range of 20 nm to 1000 nm.

4. The planar high voltage device according to claim 1, characterized in that: The source region and the drain region both include an N-type heavily doped region, the N-type heavily doped region in the source region is connected to the source metal layer through a contact hole; the N-type heavily doped region in the drain region is connected to the drain metal layer through a contact hole.

5. The planar high voltage device according to claim 4, characterized in that: The body region includes a body deep trench and a P-type heavily doped region located in the body deep trench, wherein the P-type heavily doped region in the body deep trench is connected to a body metal layer via a contact hole; and the depth of the body deep trench is less than the depth of the body region.

6. The planar high voltage device according to claim 5, characterized in that: An upper surface of the P-type heavily doped region in the body region is lower than an upper surface of the N-type heavily doped region in the source region.

7. The planar high voltage device according to claim 6, characterized in that: The depth of the body region is in the range of 0.3 to 3 um, and / or the depth difference between the upper surface of the P-type heavily doped region in the body region and the upper surface of the N-type heavily doped region in the source region is in the range of 0.3 to 3 um.

8. The planar high voltage device according to claim 5, characterized in that: The upper surfaces of the P-type heavily doped region in the body region and the N-type heavily doped region in the source region are flush and have the same depth.

9. The planar high voltage device according to claim 1, characterized in that: It also includes a P-type well region, which is located above the P-type isolation layer and is adjacent to the N-type drift layer in a horizontal direction; the P-type well region is connected to the outside through a contact hole.

10. The planar high voltage device according to claim 1, characterized in that: The semiconductor substrate further includes an N-type buried layer, and the N-type buried layer is located between the semiconductor substrate and the P-type isolation layer.

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