Multi-chip cascade packaging structure
Through the multi-chip cascade packaging structure, including the electrical connection of the first gallium nitride chip, silicon-based MOSFET chip and the second gallium nitride chip, the problems of long development cycle and high cost of medium and high power gallium nitride devices are solved, and efficient packaging and convenient cascade are achieved.
Patent Information
- Application Number
- CN202421922082.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-08-09
AI Technical Summary
Medium and high-power gallium nitride devices have long development cycles and high costs, making it difficult to adapt to cascade packaging with silicon-based MOSFETs.
The multi-chip cascade packaging structure is adopted, including a first gallium nitride chip, a semiconductor chip (such as a silicon-based MOSFET) and a second gallium nitride chip arranged in sequence, and the package base island and direct copper clad plate are used to improve the convenience and stability of the packaging.
It reduces the development cycle and cost of gallium nitride chips, improves the cascade packaging convenience with silicon-based MOSFETs, and is suitable for medium and high-power industrial and automotive-grade products.
Smart Images
Figure CN222916509U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, in particular to a multi-chip cascade packaging structure. Background Art
[0002] Gallium nitride devices have the characteristics of large bandgap, high electron mobility, and high saturation speed, and can be widely used in high voltage, high current, and high temperature environments. Taking AlGaN (aluminum gallium nitride) and GaN (gallium nitride) heterojunction high electron mobility transistors as an example, as normally-on devices, they are usually cascaded and packaged with silicon-based MOSFETs (metal-oxide semiconductor field-effect transistors) to form normally-off devices. With the development of gallium nitride technology, gallium nitride power devices have gradually been applied to medium and high-power industrial and automotive-grade products, which can replace silicon-based power devices and achieve efficiency improvement.
[0003] At present, the development of medium and high-power GaN devices requires designing a large-size GaN chip layout, making a mask for tape-out and reliability verification, and then cascading packaging with silicon-based MOSFETs according to the power and current requirements of electronic product systems. However, the development cycle of large-size GaN chips is long and the cost is high.
[0004] Therefore, how to provide a medium-to-high power gallium nitride device that reduces the development cycle and manufacturing cost, and is suitable for cascade packaging with silicon-based MOSFET, is a technical problem that technical personnel in this field urgently need to solve. Utility Model Content
[0005] In view of this, the purpose of the utility model is to provide a multi-chip cascade packaging structure, which solves the problem that the development of medium and high power gallium nitride devices in the prior art requires designing a large-size gallium nitride chip layout, making a mask plate for tape-out and reliability verification, and then cascading packaging with silicon-based MOSFET, but the development cycle of large-size gallium nitride chips is long and the cost is high.
[0006] In order to solve the above technical problems, the utility model provides a multi-chip cascade packaging structure, comprising:
[0007] A first gallium nitride chip, a semiconductor chip, and a second gallium nitride chip are arranged in sequence; the semiconductor chip is a silicon-based MOSFET chip or a silicon carbide-based MOSFET chip;
[0008] The gate, drain and source of the first gallium nitride chip, the gate, drain and source of the second gallium nitride chip, and the gate and source of the semiconductor chip are all arranged on the front side of the corresponding chip, the drain of the semiconductor chip is arranged on the back side of the semiconductor chip, and the first gallium nitride chip and the second gallium nitride chip are both provided with gates on both sides along a direction perpendicular to the arrangement direction of the first gallium nitride chip, the semiconductor chip and the second gallium nitride chip;
[0009] The first gate in the first gallium nitride chip and the second gate in the second gallium nitride chip are both conductively connected to the source of the semiconductor chip; the first gate is the gate on the side of the first gallium nitride chip close to the source of the semiconductor chip, and the second gate is the gate on the side of the second gallium nitride chip close to the source of the semiconductor chip;
[0010] The source of the first gallium nitride chip and the source of the second gallium nitride chip are both conductively connected to the drain of the semiconductor chip, and the drain of the first gallium nitride chip and the drain of the second gallium nitride chip are both conductively connected to the drain pin, the gate of the semiconductor chip is conductively connected to the gate pin, and the source of the semiconductor chip is conductively connected to the source pin.
[0011] Optionally, the first gallium nitride chip and the second gallium nitride chip are the same, and the first gallium nitride chip and the second gallium nitride chip are symmetrically arranged along the semiconductor chip.
[0012] Optionally, the first gate is conductively connected to the source of the semiconductor chip through a first binding wire, and the second gate is conductively connected to the source of the semiconductor chip through a second binding wire;
[0013] The first binding wires and the second binding wires have the same number and are symmetrically arranged along the semiconductor chip.
[0014] Optionally, the source electrode of the first gallium nitride chip is conductively connected to the drain electrode of the semiconductor chip through a third bonding wire or a third metal strip, and the source electrode of the second gallium nitride chip is conductively connected to the drain electrode of the semiconductor chip through a fourth bonding wire or a fourth metal strip;
[0015] The third binding wires or the third metal strips have the same number as the fourth binding wires or the fourth metal strips, and are symmetrically arranged along the semiconductor chip.
[0016] Optionally, it also includes a package base island and a direct copper clad board;
[0017] The direct copper clad laminate is arranged on the surface of the package base island, and a first copper clad area, a second copper clad area and a third copper clad area are arranged on a surface of one side of the direct copper clad laminate exposed; the first gallium nitride chip, the semiconductor chip and the second gallium nitride chip are arranged on the surfaces of the first copper clad area, the second copper clad area and the third copper clad area respectively;
[0018] Correspondingly, the drain of the first gallium nitride chip and the drain of the second gallium nitride chip are both conductively connected to the drain pin through the package base island.
[0019] Optionally, a fourth copper-clad area is further provided on the surface of the direct copper-clad board in contact with the base island of the package body;
[0020] The fourth copper-clad area is connected to the package base island via soft solder or conductive adhesive.
[0021] Optionally, the direct copper clad board is a direct copper clad silicon nitride ceramic board.
[0022] Optionally, the first gallium nitride chip, the semiconductor chip and the second gallium nitride chip are correspondingly arranged on the surfaces of the first copper clad area, the second copper clad area and the third copper clad area through conductive glue.
[0023] Optionally, the package base island and the drain pin are an integrated structure.
[0024] Optionally, the gate pin, the drain pin and the source pin are arranged in sequence.
[0025] It can be seen that the multi-chip cascade packaging structure provided by the utility model comprises a first gallium nitride chip, a semiconductor chip and a second gallium nitride chip which are arranged in sequence, and the semiconductor chip is a silicon-based MOSFET chip or a silicon carbide-based MOSFET chip; the gate, drain and source of the first gallium nitride chip, the gate, drain and source of the second gallium nitride chip, and the gate and source of the semiconductor chip are all arranged on the front side of the corresponding chip, the drain of the semiconductor chip is arranged on the back side of the semiconductor chip, and the first gallium nitride chip and the second gallium nitride chip are arranged on both sides perpendicular to the direction in which the first gallium nitride chip, the semiconductor chip and the second gallium nitride chip are arranged. Both are provided with gates; the first gate in the first gallium nitride chip and the second gate in the second gallium nitride chip are both conductively connected to the source of the semiconductor chip, the first gate is the gate of the first gallium nitride chip on the side close to the source of the semiconductor chip, and the second gate is the gate of the second gallium nitride chip on the side close to the source of the semiconductor chip; the source of the first gallium nitride chip and the source of the second gallium nitride chip are both conductively connected to the drain of the semiconductor chip, and the drain of the first gallium nitride chip and the drain of the second gallium nitride chip are both conductively connected to the drain pin, the gate of the semiconductor chip is conductively connected to the gate pin, and the source of the semiconductor chip is conductively connected to the source pin. The utility model arranges two gallium nitride chips in parallel to be connected with a silicon-based MOSFET chip, or to a silicon carbide-based MOSFET chip, and the two gallium nitride chips are arranged on both sides of the silicon-based MOSFET chip, or on both sides of the silicon carbide-based MOSFET chip, and the gate electrode close to the source electrode of the silicon-based MOSFET chip is connected to the source electrode of the silicon-based MOSFET chip, or the gate electrode close to the source electrode of the silicon carbide-based MOSFET chip is connected to the source electrode of the silicon carbide-based MOSFET chip, thereby avoiding the long cycle and high cost problems of developing large-size gallium nitride chips, and is suitable for cascade packaging with silicon-based MOSFET chips, or silicon carbide-based MOSFET chips, thereby improving the convenience of packaging. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.
[0027] Figure 1 A schematic diagram of a multi-chip cascade packaging structure provided by an embodiment of the utility model;
[0028] Figure 2 A schematic diagram of the structure of a directly copper-clad silicon nitride ceramic plate in a multi-chip cascade packaging structure provided by an embodiment of the utility model;
[0029] Figure 1 to Figure 2 In the figure, the reference numerals are described as follows:
[0030] 1-package base island, 2-direct copper clad board, 3-binding wire, 4-first copper clad area, 5-first gallium nitride chip, 6-drain of the first gallium nitride chip, 7-source of the first gallium nitride chip, 8-first gate of the first gallium nitride chip, 9-gate of the semiconductor chip, 10-gate pin, 11-drain pin, 12-source pin, 13-source of the semiconductor chip, 14-semiconductor chip, 15-second gate of the second gallium nitride chip, 16-source of the second gallium nitride chip, 17-drain of the second gallium nitride chip, 18-second gallium nitride chip, 19-third copper clad area, 20-first gate of the second gallium nitride chip, 21-second copper clad area, 22-second gate of the first gallium nitride chip, 23-silicon nitride ceramic board, 24-fourth copper clad area. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0032] Please refer to Figure 1 , Figure 1 A schematic diagram of a multi-chip cascade packaging structure provided by an embodiment of the utility model. The multi-chip cascade packaging structure may include:
[0033] A first gallium nitride chip 5, a semiconductor chip 14, and a second gallium nitride chip 18 are arranged in sequence; the semiconductor chip 14 is a silicon-based MOSFET chip or a silicon carbide-based MOSFET chip;
[0034] The gate, drain and source of the first gallium nitride chip 5, the gate, drain and source of the second gallium nitride chip 18, and the gate 9 of the semiconductor chip 14 and the source 13 of the semiconductor chip are all arranged on the front side of the corresponding chip, the drain of the semiconductor chip 14 is arranged on the back side of the semiconductor chip 14, and the first gallium nitride chip 5 and the second gallium nitride chip 18 are both provided with gates on both sides along the direction perpendicular to the arrangement of the first gallium nitride chip 5, the semiconductor chip 14 and the second gallium nitride chip 18;
[0035] The first gate 8 in the first gallium nitride chip and the second gate 15 in the second gallium nitride chip are both conductively connected to the source 13 of the semiconductor chip; the first gate is the gate on the side of the first gallium nitride chip 5 close to the source 13 of the semiconductor chip, and the second gate is the gate on the side of the second gallium nitride chip 18 close to the source 13 of the semiconductor chip;
[0036] The source 7 of the first gallium nitride chip and the source 16 of the second gallium nitride chip are both conductively connected to the drain of the semiconductor chip 14, and the drain 6 of the first gallium nitride chip and the drain 17 of the second gallium nitride chip are both conductively connected to the drain pin 11, the gate 9 of the semiconductor chip is conductively connected to the gate pin 10, and the source 13 of the semiconductor chip is conductively connected to the source pin 12.
[0037] It should be noted that in this embodiment, the semiconductor chip 14 is set as a silicon-based MOSFET chip, or the semiconductor chip 14 is set as a silicon carbide-based MOSFET chip, so as to be compatible with the gallium nitride chip for cascade packaging. And the gate, drain and source of the first gallium nitride chip 5, the gate, drain and source of the second gallium nitride chip 18, and the gate 9 and source of the semiconductor chip can be set on the front of the chip, and the drain of the semiconductor chip 14 is set on the back of the semiconductor chip 14. When multiple chips are cascaded and packaged, they are generally set to the same surface height to ensure regularity. At this time, the first gallium nitride chip 5 and the second gallium nitride chip 18 are led out, and the gate 9 and source of the semiconductor chip are set on the same surface for easy connection. It should be pointed out that this embodiment does not limit the specific setting area of the drain of the semiconductor chip 14. For example, the drain of the semiconductor chip 14 can be set on the side surface facing away from the surface of the semiconductor chip 14 where the gate and source are set.
[0038] Furthermore, the leads between the multiple chips in the cascade package can be connected by wire bonding. However, considering that the first gallium nitride chip 5, the second gallium nitride chip 18, and the semiconductor chip 14 as described above are provided in this embodiment, the number of leads is greatly increased, so it is necessary to reduce the complexity of wire bonding. Therefore, in this application, the arrangement direction of the first gallium nitride chip 5, the semiconductor chip 14, and the second gallium nitride chip 18 can be set as a preset direction, and the surface of the first gallium nitride chip 5 is perpendicular to the preset direction. Both sides are provided with corresponding gates, and the surface of the second gallium nitride chip 18 is also perpendicular to the preset direction. Both sides are provided with corresponding gates. The gate, that is, the first gallium nitride chip 5 and the second gallium nitride chip 18 both include a first gate and a second gate. Therefore, when the gate in the first gallium nitride chip 5 and the gate in the second gallium nitride chip 18 are both connected to the source 13 of the above-mentioned semiconductor chip, the gate in the first gallium nitride chip 5 close to the source 13 of the above-mentioned semiconductor chip can be connected to the source 13 of the above-mentioned semiconductor chip by wire bonding. Correspondingly, the gate in the second gallium nitride chip 18 close to the source 13 of the above-mentioned semiconductor chip can be connected to the source 13 of the above-mentioned semiconductor chip by wire bonding, thereby realizing the simplicity of multi-chip cascade packaging.
[0039] It should be noted that in this embodiment, the first gate electrode of the first gallium nitride chip 5 is arranged closer to the source electrode 13 of the semiconductor chip, and the second gate electrode of the second gallium nitride chip 18 is arranged closer to the source electrode 13 of the semiconductor chip, that is, the first gate electrode 8 of the first gallium nitride chip and the second gate electrode 15 of the second gallium nitride chip are arranged on the same side perpendicular to the preset direction in the corresponding gallium nitride chip. In this embodiment, the specific positions of the first gate electrode 8 of the first gallium nitride chip and the second gate electrode 15 of the second gallium nitride chip are not limited, as long as they are located in the first gallium nitride chip 5 and the second gallium nitride chip 18 close to the source electrode 13 of the semiconductor chip. Furthermore, to ensure that the multi-chip cascade packaging is completed, the source electrode 7 of the first gallium nitride chip and the source electrode 16 of the second gallium nitride chip are both conductively connected to the drain electrode of the semiconductor chip 14. In a feasible embodiment, since the drain electrode of the semiconductor chip 14 is arranged on a side surface facing away from the source electrode 13 and the gate electrode of the semiconductor chip, the source electrode 7 of the first gallium nitride chip and the source electrode 16 of the second gallium nitride chip can be arranged on a side of the surface of each gallium nitride chip close to the semiconductor chip 14, so as to facilitate wire bonding connection with the drain electrode of the semiconductor chip 14, and then the remaining lead electrodes of each chip are respectively connected to the corresponding pins.
[0040] In this embodiment, while ensuring that the first gallium nitride chip 5, the second gallium nitride chip 18 and the semiconductor chip 14 are cascade packaged to improve the overall power of the device, the simplicity of connection between the three is improved and the difficulty of preparation is reduced.
[0041] Furthermore, in order to improve the manufacturing efficiency of the multi-chip cascade packaging structure, the first gallium nitride chip 5 and the second gallium nitride chip 18 may be identical, and the first gallium nitride chip 5 and the second gallium nitride chip 18 may be symmetrically arranged along the semiconductor chip 14 .
[0042] It should be noted that, in this embodiment, the first gallium nitride chip 5 and the second gallium nitride chip 18 are identical, and the first gallium nitride chip 5 and the second gallium nitride chip 18 are symmetrically arranged along the semiconductor chip 14. It is not necessary to distinguish between the first gallium nitride chip 5 and the second gallium nitride chip 18. It is only necessary to arrange the first gallium nitride chip 5 and the second gallium nitride chip 18 on both sides of the semiconductor chip 14 according to different arrangement positions during preparation. In addition, in this embodiment, since the first gallium nitride chip 5 and the second gallium nitride chip 18 are identical, the first gate 8 of the first gallium nitride chip is identical to the first gate 20 of the second gallium nitride chip, the second gate 22 of the first gallium nitride chip is identical to the second gate 15 of the second gallium nitride chip, and the first gallium nitride chip 5 and the second gallium nitride chip 18 are symmetrically arranged along the semiconductor chip 14. Therefore, the gate of the second gallium nitride chip 18 close to the source of the semiconductor chip 14 is the second gate, that is, the first gate 8 of the first gallium nitride chip and the second gate 15 of the second gallium nitride chip are both connected to the source 13 of the semiconductor chip.
[0043] Furthermore, in order to ensure the regularity and convenience of the first gate 8 of the first gallium nitride chip and the second gate 15 of the second gallium nitride chip being connected to the source 13 of the semiconductor chip, the first gate may be conductively connected to the source 13 of the semiconductor chip through a first binding wire, and the second gate may be conductively connected to the source 13 of the semiconductor chip through a second binding wire;
[0044] The number of the first bonding wires and the second bonding wires is the same and they are symmetrically arranged along the semiconductor chip 14 .
[0045] It should be noted that, in this embodiment, the first gate 8 of the first gallium nitride chip is conductively connected to the source 13 of the above-mentioned semiconductor chip by using the first binding wire, and the second gate 15 of the second gallium nitride chip is conductively connected to the source 13 of the above-mentioned semiconductor chip by using the second binding wire. When the above-mentioned first gallium nitride chip 5 and the second gallium nitride chip 18 are symmetrically arranged along the above-mentioned semiconductor chip 14, the first gate 8 of the first gallium nitride chip and the second gate 15 of the second gallium nitride chip can be specifically arranged symmetrically along the above-mentioned semiconductor chip 14, and then the number of the above-mentioned first binding wires and the second binding wires can be set to be the same, and they can be symmetrically arranged along the above-mentioned semiconductor chip 14, so as to further improve the regularity of the package.
[0046] Furthermore, in order to improve the regularity of the multi-chip cascade packaging structure, the source electrode 7 of the first gallium nitride chip can be conductively connected to the drain electrode of the semiconductor chip 14 through a third bonding wire or a third metal strip, and the source electrode 16 of the second gallium nitride chip can be conductively connected to the drain electrode of the semiconductor chip 14 through a fourth bonding wire or a fourth metal strip;
[0047] The number of the third bonding wires or the third metal strips is the same as that of the fourth bonding wires or the fourth metal strips, and they are symmetrically arranged along the semiconductor chip 14 .
[0048] It should be noted that when the drain of the semiconductor chip 14 is located on different surfaces from the source 13 and the gate of the semiconductor chip, the drain is set on the side surface of the semiconductor chip 14 facing away from its source and gate. At this time, the drain of the semiconductor chip 14 can be at the same distance from the first gallium nitride chip 5 and the second gallium nitride chip 18, which improves the convenience and regularity of connection. It should be pointed out that in this embodiment, the source 7 of the first gallium nitride chip and the source 16 of the second gallium nitride chip can be set on the side of the surface of each chip close to the semiconductor chip 14 to facilitate conductive connection.
[0049] Furthermore, in order to improve the convenience of cascade packaging of the multi-chip cascade packaging structure, it may also include a package base island 1 and a direct copper clad plate 2;
[0050] The direct copper clad board 2 is arranged on the surface of the package base island 1, and the exposed side surface of the direct copper clad board 2 is provided with a first copper clad area 4, a second copper clad area 21 and a third copper clad area 19; the first gallium nitride chip 5, the semiconductor chip 14 and the second gallium nitride chip 18 are arranged on the surfaces of the first copper clad area 4, the second copper clad area 21 and the third copper clad area 19 respectively;
[0051] Correspondingly, the drain 6 of the first gallium nitride chip and the drain 17 of the second gallium nitride chip are both conductively connected to the drain pin 11 through the package base island 1 .
[0052] It should be noted that, in this embodiment, the package base island 1 is used as a support body, and a direct copper clad board 2 is prepared on the package base island 1, and the exposed surface of the direct copper clad board 2 includes a first copper clad area 4, a second copper clad area 21 and a third copper clad area 19. Specifically, the first copper clad area 4, the second copper clad area 21 and the third copper clad area 19 are generally arranged on the side of the direct copper clad board 2 facing away from the package base island 1. When the drain of the semiconductor chip 14 is arranged on the back side, it can be conductively connected to the corresponding copper clad area, and the source 7 of the first gallium nitride chip and the source 16 of the second gallium nitride chip can be conductively connected to the copper clad area, which is convenient for wiring.
[0053] Furthermore, in order to ensure the stability of the multi-chip cascade packaging structure, a fourth copper-clad area 24 is further provided on the surface of the copper-clad board 2 that directly contacts the package base island 1;
[0054] The fourth copper-clad area 24 is connected to the package base island 1 through soft solder or conductive glue.
[0055] It should be noted that in this embodiment, the surface of the direct copper clad laminate 2 facing the package base island 1 is connected to the package base island 1 through soft solder or conductive glue, which can reduce the stress between the direct copper clad laminate 2 and the package base island 1 and improve the packaging stability.
[0056] Further, in a feasible embodiment, reference may be made to Figure 2 , Figure 2 The schematic diagram of the structure of a direct copper-clad silicon nitride ceramic board in a multi-chip cascade packaging structure provided by an embodiment of the utility model. The direct copper-clad board 2 can be set as a direct copper-clad silicon nitride ceramic board.
[0057] It should be noted that, in this embodiment, the direct copper-clad board 2 is configured to be directly copper-clad on the surface of the silicon nitride ceramic board 23 to obtain the above-mentioned direct copper-clad silicon nitride ceramic board 23, which can ensure the heat dissipation effect of the structure.
[0058] Furthermore, in order to improve the stability of the multi-chip cascade packaging structure, the first gallium nitride chip 5, the semiconductor chip 14 and the second gallium nitride chip 18 can be arranged on the surfaces of the first copper clad area 4, the second copper clad area 21 and the third copper clad area 19 through conductive glue.
[0059] It should be noted that, in this embodiment, the first and second gallium nitride chips and the semiconductor chip 14 are arranged in corresponding copper-clad areas by using conductive adhesive, which reduces the stress between structures and further improves the structural stability.
[0060] Furthermore, in order to improve the simplicity of the structure, the package base island 1 and the drain pin 11 may be arranged as an integrated structure.
[0061] It should be noted that in this embodiment, the package base island 1 and the drain pin 11 are integrated into a structure, and the drain 6 of the first gallium nitride chip and the drain 17 of the second gallium nitride chip can be directly conductively connected to the package base island 1, which is convenient for wiring connection.
[0062] Furthermore, in a feasible embodiment, the gate pin 10 , the drain pin 11 and the source pin 12 may be arranged in sequence.
[0063] It should be noted that in this embodiment, the gate pin 10, the drain pin 11 and the source pin 12 are arranged in sequence along the specified direction, and the lead-out electrode of the corresponding chip is connected to the corresponding pin by wire bonding, which ensures that the pin layout in this application is the same as the conventional pin layout, thereby improving the convenience of preparation.
[0064] The multi-chip cascade packaging structure provided by the utility model comprises a first gallium nitride chip 5, a semiconductor chip 14, and a second gallium nitride chip 18 which are arranged in sequence, wherein the semiconductor chip 14 is a silicon-based MOSFET chip or a silicon carbide-based MOSFET chip; the gate, drain, and source of the first gallium nitride chip 5, the gate, drain, and source of the second gallium nitride chip 18, and the gate 9 and source of the semiconductor chip are all arranged on the front side of the corresponding chip, the drain of the semiconductor chip 14 is arranged on the back side of the semiconductor chip 14, and the first gallium nitride chip 5 and the second gallium nitride chip 18 are both arranged on both sides perpendicular to the arrangement direction of the first gallium nitride chip 5, the semiconductor chip 14, and the second gallium nitride chip 18. There is a gate; the first gate in the first gallium nitride chip 5 and the second gate in the second gallium nitride chip 18 are both conductively connected to the source 13 of the semiconductor chip, the first gate is the gate of the first gallium nitride chip 5 on the side close to the source 13 of the semiconductor chip, and the second gate is the gate of the second gallium nitride chip 18 on the side close to the source 13 of the semiconductor chip; the source 7 of the first gallium nitride chip and the source 16 of the second gallium nitride chip are both conductively connected to the drain of the semiconductor chip 14, and the drain 6 of the first gallium nitride chip and the drain 17 of the second gallium nitride chip are both conductively connected to the drain pin 11, the gate 9 of the semiconductor chip is conductively connected to the gate pin 10, and the source 13 of the semiconductor chip is conductively connected to the source pin 12. The utility model arranges two gallium nitride chips in parallel to be connected with a silicon-based MOSFET chip, or to a silicon carbide-based MOSFET chip, and the two gallium nitride chips are arranged on both sides of the silicon-based MOSFET chip, or on both sides of the silicon carbide-based MOSFET chip, and the gate electrode close to the source electrode of the silicon-based MOSFET chip is connected to the source electrode of the silicon-based MOSFET chip, or the gate electrode close to the source electrode of the silicon carbide-based MOSFET chip is connected to the source electrode of the silicon carbide-based MOSFET chip, thereby avoiding the long cycle and high cost problems of developing large-size gallium nitride chips, and is suitable for cascade packaging with silicon-based MOSFET chips, or silicon carbide-based MOSFET chips, thereby improving the convenience of packaging.
[0065] In addition, in the embodiment of the utility model, the first gallium nitride chip 5 and the second gallium nitride chip 18 are arranged identically, and the first gallium nitride chip 5 and the second gallium nitride chip 18 are arranged symmetrically along the semiconductor chip 14, so that the first gallium nitride chip 5 and the second gallium nitride chip 18 do not need to be distinguished. It is only necessary to arrange the first gallium nitride chip 5 and the second gallium nitride chip 18 on both sides of the semiconductor chip 14 according to different arrangement positions during preparation, thereby improving the preparation efficiency of the multi-chip cascade packaging structure; the first gate electrode 8 of the first gallium nitride chip is connected to the source electrode 8 of the semiconductor chip by using the first bonding wire. 13 is conductively connected, and the second gate 15 of the second gallium nitride chip is conductively connected to the source 13 of the semiconductor chip by using the second binding wire, and the number of the first binding wires and the second binding wires is the same, and they are symmetrically arranged along the semiconductor chip 14, thereby ensuring the regularity and convenience of the multi-chip cascade packaging structure; by setting the source 7 of the first gallium nitride chip to be conductively connected to the drain of the semiconductor chip 14 through the third binding wire or the third metal strip, the source 16 of the second gallium nitride chip is conductively connected to the drain of the semiconductor chip 14 through the fourth binding wire or the fourth metal strip, and the third binding wire or the third metal strip is conductively connected to the drain of the semiconductor chip 14 The number of the fourth binding wires or the fourth metal strips is the same, and they are symmetrically arranged along the semiconductor chip 14, thereby improving the regularity of the multi-chip cascade packaging structure; the package base island 1 and the direct copper clad board 2 are used as the support body to improve the convenience of cascade packaging of the multi-chip cascade packaging structure; the surface of the direct copper clad board 2 close to the package base island 1 is set to be connected to the package base island 1 through soft solder or conductive glue, which can reduce the stress between the direct copper clad board 2 and the package base island 1 and improve the packaging stability; the direct copper clad board 2 is set to be a direct copper clad silicon nitride ceramic board, which can ensure the heat dissipation effect of the structure; The first and second gallium nitride chips and the semiconductor chip 14 are arranged in corresponding copper-clad areas with conductive glue, which reduces the stress between the structures and further improves the structural stability; the package base island 1 and the drain pin 11 are arranged as an integrated structure, and the drain 6 of the first gallium nitride chip and the drain 17 of the second gallium nitride chip can be directly conductively connected to the package base island 1, which is convenient for wiring connection and further improves the stability of the structure; the gate pin 10, the drain pin 11 and the source pin 12 are arranged in sequence, which ensures that the pin layout in the present application is the same as the conventional pin layout, and improves the convenience of preparation.
[0066] In a feasible embodiment, the multi-chip cascade packaging structure provided by the utility model may specifically include the following structure:
[0067] A package base island, a first gallium nitride chip, a second gallium nitride chip, a silicon-based MOSFET and a direct copper-clad ceramic board, wherein the first gallium nitride chip and the second gallium nitride chip are both depletion-type high-voltage gallium nitride chips, and the first gallium nitride chip and the second gallium nitride chip are exactly the same;
[0068] The direct copper-clad ceramic plate includes a first upper copper-clad area, a second upper copper-clad area, and a third upper copper-clad area arranged in sequence on the surface, and the direct copper-clad ceramic plate also includes a lower copper-clad area and a ceramic plate, and the ceramic plate is a silicon nitride ceramic plate to improve thermal conductivity;
[0069] The first gallium nitride chip, the silicon-based MOSFET chip, and the second gallium nitride chip are correspondingly attached to the first upper copper-clad area, the second upper copper-clad area, and the third upper copper-clad area through conductive adhesive, and the lower copper-clad area of the direct copper-clad ceramic board is connected to the package base island through soft solder or conductive adhesive;
[0070] The first upper copper region and the third upper copper region have the same size, which is larger than the size of the gallium nitride chip. The second upper copper region has the same length as the first upper copper region and the third upper copper region, and its width is larger than the length of the silicon-based MOSFET chip. In this embodiment, the maximum value of the lateral size and the longitudinal size is used as the length of the silicon-based MOSFET chip here.
[0071] The gate, source and drain of the first gallium nitride chip, and the gate, source and drain of the second gallium nitride chip are all arranged on the front side of the chip. To facilitate wire bonding, the first gallium nitride chip and the second gallium nitride chip are both provided with a first gate and a second gate on both sides of the direction perpendicular to the arrangement of the first upper copper region, the second upper copper region and the third upper copper region; the gate and source of the silicon-based MOSFET chip are arranged on the front side of the chip, and the drain is arranged on the back side of the chip;
[0072] The source of the first gallium nitride chip and the source of the second gallium nitride chip are both connected to the drain of the silicon-based MOSFET chip through bonding wires, the number of leads is the same, and they are symmetrically arranged along the silicon-based MOSFET chip, and can also be connected through copper strips; the drain of the first gallium nitride chip and the drain of the second gallium nitride chip are both connected to the base island of the package through bonding wires, and the base island of the package and the drain pin are an integrated structure;
[0073] The first gate of the first gallium nitride chip is connected to the source of the silicon-based MOSFET chip through a bonding wire, and the second gate of the second gallium nitride chip is connected to the source of the silicon-based MOSFET chip through a bonding wire, and the bonding wires connected to the first gate wire and the bonding wires connected to the second gate wire have the same number of leads and are symmetrically arranged along the silicon-based MOSFET chip;
[0074] The gate of the silicon-based MOSFET chip is connected to the gate pin through a bonding wire, and the source of the silicon-based MOSFET chip is connected to the source pin through a bonding wire.
[0075] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0076] In addition, it should be noted that, in this article, relationships such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants are intended to cover non-exclusive inclusions.
[0077] The above is a detailed introduction to a multi-chip cascade packaging structure provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the structure of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A multi-chip cascade packaging structure, characterized in that: include: A first gallium nitride chip, a semiconductor chip, and a second gallium nitride chip are arranged in sequence; The semiconductor chip is a silicon-based MOSFET chip or a silicon carbide-based MOSFET chip; The gate, drain and source of the first gallium nitride chip, the gate, drain and source of the second gallium nitride chip, and the gate and source of the semiconductor chip are all arranged on the front side of the corresponding chip, the drain of the semiconductor chip is arranged on the back side of the semiconductor chip, and the first gallium nitride chip and the second gallium nitride chip are both provided with gates on both sides along a direction perpendicular to the arrangement direction of the first gallium nitride chip, the semiconductor chip and the second gallium nitride chip; The first gate in the first gallium nitride chip and the second gate in the second gallium nitride chip are both conductively connected to the source of the semiconductor chip; the first gate is the gate on the side of the first gallium nitride chip close to the source of the semiconductor chip, and the second gate is the gate on the side of the second gallium nitride chip close to the source of the semiconductor chip; The source of the first gallium nitride chip and the source of the second gallium nitride chip are both conductively connected to the drain of the semiconductor chip, and the drain of the first gallium nitride chip and the drain of the second gallium nitride chip are both conductively connected to the drain pin, the gate of the semiconductor chip is conductively connected to the gate pin, and the source of the semiconductor chip is conductively connected to the source pin.
2. The multi-chip cascade packaging structure according to claim 1, characterized in that: The first gallium nitride chip and the second gallium nitride chip are identical, and the first gallium nitride chip and the second gallium nitride chip are symmetrically arranged along the semiconductor chip.
3. The multi-chip cascade packaging structure according to claim 2, characterized in that: The first gate is conductively connected to the source of the semiconductor chip through a first bonding wire, and the second gate is conductively connected to the source of the semiconductor chip through a second bonding wire; The first binding wires and the second binding wires have the same number and are symmetrically arranged along the semiconductor chip.
4. The multi-chip cascade packaging structure according to claim 2, characterized in that: The source electrode of the first gallium nitride chip is conductively connected to the drain electrode of the semiconductor chip through a third bonding wire or a third metal strip, and the source electrode of the second gallium nitride chip is conductively connected to the drain electrode of the semiconductor chip through a fourth bonding wire or a fourth metal strip; The third binding wires or the third metal strips have the same number as the fourth binding wires or the fourth metal strips, and are symmetrically arranged along the semiconductor chip.
5. The multi-chip cascade packaging structure according to claim 1, characterized in that: It also includes the package base island and direct copper clad laminate; The direct copper clad laminate is arranged on the surface of the package base island, and a first copper clad area, a second copper clad area and a third copper clad area are arranged on a surface of one side of the direct copper clad laminate exposed; the first gallium nitride chip, the semiconductor chip and the second gallium nitride chip are arranged on the surfaces of the first copper clad area, the second copper clad area and the third copper clad area respectively; Correspondingly, the drain of the first gallium nitride chip and the drain of the second gallium nitride chip are both conductively connected to the drain pin through the package base island.
6. The multi-chip cascade packaging structure according to claim 5, characterized in that: The surface of the direct copper-clad board in contact with the package base island is further provided with a fourth copper-clad area; The fourth copper-clad area is connected to the package base island via soft solder or conductive adhesive.
7. The multi-chip cascade packaging structure according to claim 5, characterized in that: The direct copper clad board is a direct copper clad silicon nitride ceramic board.
8. The multi-chip cascade packaging structure according to claim 5, characterized in that: The first gallium nitride chip, the semiconductor chip and the second gallium nitride chip are correspondingly arranged on the surfaces of the first copper clad area, the second copper clad area and the third copper clad area through conductive adhesive.
9. The multi-chip cascade packaging structure according to claim 5, characterized in that: The package base island and the drain pin are an integrated structure.
10. The multi-chip cascade packaging structure according to claim 1, characterized in that: The gate pin, the drain pin and the source pin are arranged in sequence.