Sensor pixel unit, pulse signal processing circuit and electronic equipment

Abstract

The embodiment of the utility model discloses a sensor pixel unit, a pulse signal processing circuit and electronic equipment, and an image sensor unit comprises a photodiode, a variable resistance type memory and a signal output circuit, one end of the photodiode is in signal connection with a power supply, the other end of the photodiode is connected with the variable resistance type memory and the signal output circuit, and the photodiode is used for receiving an optical signal in an exposure duration to generate a voltage signal; one end of the variable resistance type memory is connected with the photodiode, the other end of the variable resistance type memory is grounded, and the variable resistance type memory is used for controlling an output end to output a voltage signal or resetting the photodiode; and the signal output circuit is used for obtaining a target signal based on the voltage signal and outputting the target signal. The pixel unit provided by the embodiment of the utility model comprises few components, is simple in structure and small in occupied area, and is more beneficial to integrated distribution in a chip.

Description

Technical Field

[0001] The present disclosure relates to the technical field of image sensors, and in particular to a sensor pixel unit, a pulse signal processing circuit, and an electronic device. Background Art

[0002] Image sensors have been widely used in fields such as digital cameras, mobile phones, medical, automotive, drones, and machine recognition. In particular, the rapid development of complementary metal oxide semiconductor (CMOS) image sensor technology has led to higher requirements for the output image quality of image sensors. CMOS image sensors can be classified into two categories according to the signal acquisition method: one method is to set the exposure duration of pixels and then measure the change in voltage signals; the second method is to set the change in voltage of pixels and then measure the exposure duration. Such an image sensor is called a pulse train image sensor. In existing image sensors, the pixel unit encodes data into an encoded signal, and then the pulse signal processing circuit performs information processing, resulting in low processing efficiency. Summary of the Utility Model

[0003] One aspect of an embodiment of the present disclosure provides a sensor pixel unit, including: a photodiode, a variable resistive memory, and a signal output circuit;

[0004] One end of the photodiode is connected to a power signal, and the other end is connected to the variable resistive memory and the signal output circuit. The photodiode is configured to receive a light signal during an exposure duration to generate a voltage signal;

[0005] One end of the variable resistive memory is connected to the photodiode, and the other end is grounded;

[0006] The signal output circuit is configured to obtain a target signal based on the voltage signal and output it.

[0007] Optionally, the variable resistive memory receives the voltage signal. In response to the voltage signal rising to a first preset voltage value, the variable resistive memory controls to output the voltage signal to the signal output circuit; in response to the voltage signal decreasing from the first preset voltage value to a second preset voltage value, the variable resistive memory controls the photodiode to perform a reset; the second preset voltage value is less than the first preset voltage value.

[0008] Optionally, the target signal is a pulse signal;

[0009] The signal output circuit includes two-stage inverters;

[0010] The two-stage inverter is used to convert the voltage signal to obtain the pulse signal.

[0011] Optionally, the two-stage inverter includes a first inverter and a second inverter connected in series;

[0012] The input end of the first inverter is connected to the photodiode and the variable resistive memory, and the output end is connected to the input end of the second inverter;

[0013] The input end of the second inverter is connected to the output end of the first inverter, and the output end serves as the output end of the sensor pixel unit.

[0014] On the other hand, an embodiment of the present disclosure provides a pulse signal processing circuit, including: a pixel array composed of sensor pixel units described in any one of the above embodiments in n rows and m columns, and a pulse processor; n and m are respectively integers greater than 1;

[0015] The pixel array is used to process the received optical signal to obtain a pulse signal. Each column of the pixel units is connected in series to the pulse processor and sends the pulse signal to the pulse processor;

[0016] The pulse processor is used to receive the pulse signal and output a processing result corresponding to the pulse signal.

[0017] Optionally, the pulse processor includes one neuron unit or multiple neuron units;

[0018] The multiple neuron units include multiple pairs of neuron pairs, and each pair of neuron pairs includes a previous neuron unit and a next neuron unit;

[0019] Each neuron unit is used to obtain an output signal for the received input signal; wherein, the input signal is the pulse signal output by the pixel array, or when the neuron unit is the next neuron unit, the output signal of the corresponding previous neuron unit;

[0020] In response to the neuron unit being the last neuron unit in the pulse processor, the output signal is used as the processing result.

[0021] Optionally, the neuron unit includes a variable resistive memory in i rows and j columns; each variable resistive memory corresponds to trained calculation parameters, and the calculation parameters indicate that the state of the variable resistive memory is in a high resistance state or a low resistance state; i and j are respectively integers greater than or equal to 1;

[0022] The neuron unit performs at least one arithmetic operation on the input signal according to the state of the variable resistive memory; wherein, the at least one arithmetic operation includes at least one of the following: addition, subtraction, multiplication, and division.

[0023] Optionally, it further includes: a first chip and a second chip stacked up and down;

[0024] Integrate the pixel array in the first chip;

[0025] Integrate the pulse processor in the second chip, and make a signal connection between the first chip and the second chip at the output end of each pixel unit.

[0026] According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, including: a processor, and a memory communicatively connected to the processor, and further including the sensor pixel unit according to any one of the above embodiments or the pulse signal processing circuit according to any one of the above embodiments;

[0027] The memory stores computer-executable instructions;

[0028] The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the pulse signal processing circuit.

[0029] Optionally, the electronic device is incorporated into any one of the following: an image data acquisition device, an audio / video player, a navigation device, an entertainment device, a communication device, roadside traffic facilities, a device in a motor vehicle, an industrial inspection device, a flight device, a medical device, a security device.

[0030] Based on the sensor pixel unit, the pulse signal processing circuit, and the electronic device provided by the above embodiments of the present disclosure, it includes: a photodiode, a variable resistive memory, and a signal output circuit; one end of the photodiode is connected to a power signal, and the other end is connected to the variable resistive memory and the signal output circuit. The photodiode is configured to receive a light signal within an exposure duration to generate a voltage signal; one end of the variable resistive memory is connected to the photodiode, and the other end is grounded, and is configured to control the output end to output a voltage signal or perform a reset on the photodiode; the signal output circuit is configured to obtain a target signal based on the voltage signal and output it. The pixel unit provided by the embodiments of the present disclosure includes fewer components, has a simple structure, occupies a smaller area, and is more conducive to being integrated and distributed in a chip; in addition, it directly outputs a pulse signal, and subsequent matching with other circuits directly processes and operates on the pulse signal without a transcoding process, improving the efficiency of signal processing.

[0031] The technical solutions of the present disclosure will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0033] Referring to the drawings, the present disclosure can be more clearly understood from the following detailed description, where:

[0034] Figure 1 is a schematic circuit structure diagram of a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0035] Figure 2 shows a schematic diagram of the basic electrical characteristics of a variable resistor memory;

[0036] Figure 3 is a schematic diagram of the photoelectric response characteristics of a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0037] Figure 4 is for Figure 3 a schematic diagram of a pulse signal obtained by processing the voltage signal in the shown example through two-stage inverters;

[0038] Figure 5 is a schematic circuit structure diagram of a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0039] Figure 6 is a schematic circuit structure diagram of a pulse signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0040] Figure 7 is a schematic circuit structure diagram of a neuron unit of a pulse signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0041] Figure 8 is a schematic structure diagram of an application embodiment of an electronic device of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and values set forth in these embodiments do not limit the scope of the present disclosure.

[0043] Those skilled in the art will understand that terms such as "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices, or modules, etc., and neither represent any specific technical meaning nor indicate an inevitable logical order between them.

[0044] It should also be understood that in the embodiments of the present disclosure, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0045] It should also be understood that for any component, data or structure mentioned in the embodiments of the present disclosure, in the absence of explicit limitation or contrary indication in the context, it is generally understood as one or more.

[0046] In addition, the term "and / or" in the present disclosure is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the associated objects before and after.

[0047] It should also be understood that the description of each embodiment in the present disclosure emphasizes the differences between the embodiments, and their similarities can be referred to each other. For the sake of brevity, they will not be elaborated one by one.

[0048] Meanwhile, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn in actual proportional relationship.

[0049] The following description of at least one exemplary embodiment is actually merely illustrative and in no way a limitation on the present disclosure and its application or use.

[0050] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and devices should be regarded as part of the specification.

[0051] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0052] The embodiments of the present disclosure can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with terminal devices, computer systems, servers and other electronic devices include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, and so on.

[0053] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system-executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, target programs, components, logics, data structures, etc., which perform specific tasks or implement specific abstract data types. The computer system / server can be implemented in a distributed cloud computing environment where tasks are executed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0054] In the process of implementing the present disclosure, the inventors found that in the biological vision system, optical signals are converted into pulse signals by the retina and transmitted and processed in the neuron network, which is a very efficient visual information processing method. In order to implement an efficient machine vision system, brain-inspired computing architectures based on pulse signals have been widely studied and developed. Since the signal outputs of current mainstream vision sensors are not pulse signals, a brain-inspired vision system based on pulse signals usually needs to add a signal transcoding module to encode the data of traditional sensors into encoded signals, and then the information is processed by a signal processing circuit. The existence of the transcoding module increases the hardware cost on the one hand and affects the information processing efficiency on the other hand. The architecture of the traditional vision sensor + pulse transcoding module + brain-inspired signal processing chip being disjointed is obviously not the most efficient means to implement a brain-inspired vision perception and processing system.

[0055] To address the above problems, the inventors propose a sensor pixel unit with a novel structure.

[0056] Figure 1 It is a schematic circuit diagram of the sensor pixel unit provided by an exemplary embodiment of the present disclosure. As Figure 1 shown, the sensor pixel unit (hereinafter referred to as the pixel unit) provided in this embodiment includes: a photodiode 110, a variable resistive memory 120, and a signal output circuit 130;

[0057] One end of the photodiode 110 is connected to the power supply signal Vdd, and the other end is connected to the variable resistive memory 120 and the signal output circuit 130. The photodiode 110 is used to receive optical signals during the exposure duration to generate voltage signals.

[0058] A photodiode is a light detector that can convert light into current or voltage signals according to the usage mode. In this embodiment, it is converted into voltage signals. The die often uses a PN junction with photosensitive characteristics, which is very sensitive to light changes, has unidirectional conductivity, and its electrical characteristics will change when the light intensity is different. Therefore, the light intensity can be used to change the voltage or current in the circuit.

[0059] One end of the variable resistor memory 120 is connected to the photodiode 110, and the other end is grounded, which is used to control the output voltage signal at the output end or perform reset on the photodiode 110.

[0060] In this embodiment, the electrical characteristics of the variable resistor memory itself are utilized to achieve a high resistance state when the voltage signal obtained by the photodiode 110 accumulates to the first preset voltage value. At this time, the photodiode is not conductive to the ground terminal GND, and the voltage signal is output through the output end; when the voltage signal drops to the second preset voltage value, it presents a low resistance state. At this time, the photodiode is grounded to GND, realizing the reset of the photodiode.

[0061] The signal output circuit 130 is used to obtain and output a target signal based on the voltage signal.

[0062] Optionally, the target signal is a pulse signal or the like.

[0063] In this embodiment, the signal output circuit 130 processes the voltage signal generated by the photodiode. For example, the voltage signal in the form of fluctuations is processed into a mutation signal including only 0 and 1, which is convenient for subsequent processing by other circuits.

[0064] The sensor pixel unit provided in the above embodiment of the present disclosure includes: a photodiode, a variable resistor memory, and a signal output circuit; one end of the photodiode is connected to a power signal, and the other end is connected to the variable resistor memory and the signal output circuit. The photodiode is used to receive a light signal during the exposure duration to generate a voltage signal; one end of the variable resistor memory is connected to the photodiode, and the other end is grounded, which is used to control the output voltage signal at the output end or perform reset on the photodiode; the signal output circuit is used to obtain and output a target signal based on the voltage signal. The pixel unit provided in the embodiment of the present disclosure includes fewer components, has a simple structure, occupies a smaller area, and is more conducive to integrated distribution in a chip; in addition, it directly outputs a pulse signal, and subsequent matching of other circuits directly processes and calculates the pulse signal without a transcoding process, improving the efficiency of signal processing.

[0065] Figure 2The basic electrical characteristics of the variable resistive memory are shown. Before the voltage across the variable resistive memory gradually increases from 0 to Vth (the first preset voltage value), the current passing through the variable resistive memory is small, and the variable resistive memory exhibits a high-resistance state. When the voltage across the variable resistive memory exceeds Vth, the current passing through the variable resistive memory undergoes a sudden change, and the rate of increase of the current with the voltage becomes larger. At this time, the variable resistive memory exhibits a low-resistance state. In the case of the low-resistance state, the voltage across the variable resistive memory needs to be reduced to Vhold (the second preset voltage value), where Vhold < Vth, and the variable resistive memory will return to the high-resistance state. This embodiment does not limit the implementation manner of the variable resistive memory. No matter what material and mechanism are used to implement a device with the above-described resistance-variable electrical characteristics, it is within the protection scope of this patent.

[0066] Based on the above electrical characteristics, the variable resistive memory 120 provided in this embodiment receives a voltage signal. In response to the voltage signal rising to the first preset voltage value (Vth), the variable resistive memory 120 controls the output of the voltage signal to the signal output circuit 130; in response to the voltage signal decreasing from the first preset voltage value to the second preset voltage value (Vhold), the variable resistive memory 120 controls the photodiode 120 to perform a reset; the second preset voltage value is less than the first preset voltage value.

[0067] In this embodiment, whenever the voltage signal output by the photodiode reaches the first preset voltage value, the variable resistive memory becomes a high-resistance state, and the voltage signal output by the photodiode is output as an output signal; whenever the voltage signal output by the photodiode decreases to the second preset voltage value, the variable resistive memory becomes a low-resistance state. At this time, the photodiode is grounded to achieve the reset of the photodiode. In an alternative example, Figure 3 The photoelectric response characteristics of the sensor pixel unit are shown. As Figure 3 shown, when the pixel unit receives light, photo-generated charges are generated on the photodiode 110, and a voltage signal is accumulated. When the voltage signal Vs is less than the first preset voltage value Vth, since the variable resistive memory 120 is in a high-resistance state, the photo-generated charges are difficult to flow into the ground terminal. Therefore, they accumulate at the node connecting the photodiode 110 and the variable resistive memory 120, causing the voltage signal Vs to gradually rise. When the voltage signal Vs rises to the first preset voltage value Vth, the variable resistive memory 120 becomes a low-resistance state, and the accumulated photo-generated charges can quickly flow into the ground terminal, causing the voltage signal Vs to rapidly drop. When the voltage signal Vs drops to the second preset voltage value Vhold, the variable resistive memory 120 becomes a high-resistance state again. In this way, every time the voltage signal Vs reaches the first preset voltage value Vth, it is regarded as emitting a pulse signal.

[0068] Figure 3 From time 0 to t1, the light intensity is relatively strong, and the accumulation speed of photo-generated charges is relatively fast. Therefore, the voltage signal Vs rises relatively fast, and a total of 3 pulse signals are generated from 0 to t1. From t1 to 2*t1, the light intensity is relatively weak, and the accumulation speed of photo-generated charges is relatively slow. Therefore, the voltage signal Vs rises relatively slowly, and a total of 2 pulse signals are generated from t1 to 2*t1. Thus, it can be seen that within a certain time period, the emission frequency of the pulse signal can reflect the light intensity of the optical signal received by the pixel unit.

[0069] In some alternative embodiments, the target signal is a pulse signal;

[0070] The signal output circuit 130 includes two-stage inverters;

[0071] The two-stage inverters are used to convert the voltage signal to obtain a pulse signal.

[0072] In this embodiment, the conversion of the voltage signal is realized through two-stage inverters. For example, as Figure 4 shown, it is a schematic diagram of the pulse signal obtained after processing the voltage signal in the example shown by Figure 3 through two-stage inverters. In Figure 4 , every time the voltage signal reaches the first preset voltage value (Vth), a pulse signal Vout is output, and no pulse signal is output at other times, realizing the sorting of the voltage signal. The pixel unit provided in this embodiment does not require any external input signal, and can realize the conversion and output of the optical signal only based on the circuit structure, further simplifying the signal processing process.

[0073] Figure 5 is a schematic diagram of the circuit structure of the sensor pixel unit provided by another exemplary embodiment of the present disclosure. As Figure 5 shown, the two-stage inverters in the sensor pixel unit provided in this embodiment include a first inverter 131 and a second inverter 132 connected in series;

[0074] The input end of the first inverter 131 is connected to the photodiode 110 and the variable resistive memory 120, and the output end is connected to the input end of the second inverter 132;

[0075] The input end of the second inverter 132 is connected to the output end of the first inverter 131, and the output end serves as the output end of the sensor pixel unit.

[0076] In this embodiment, converting the voltage signal into a pulse signal through two inverters facilitates the subsequent direct processing of the pulse signal. Since the pixel unit only includes 4 simple components, the structure is simple, and it is easier to industrialize and layout in integrated circuits, and can be better applied in sensors with a smaller volume.

[0077] Figure 6 This is a schematic diagram of the circuit structure of a pulse signal processing circuit provided by an exemplary embodiment of the present disclosure. As Figure 6 shown, the pulse signal processing circuit provided by the embodiments of the present disclosure includes: a pixel array 610 composed of sensor pixel units 611 provided in any of the above embodiments arranged in n rows and m columns, and a pulse processor 620.

[0078] Wherein, n and m are respectively integers greater than 1.

[0079] The pixel array 610 is configured to process the received optical signal to obtain a pulse signal. Each column of pixel units is connected in series to the pulse processor and sends the pulse signal to the pulse processor 620.

[0080] The pulse processor 620 is configured to process the pulse signal to obtain a processing result.

[0081] In the pulse signal processing circuit provided by this embodiment, the pulse processor directly performs arithmetic processing on the pulse signal output by the pixel array. There is no need for encoding and transcoding between photoelectric conversion and signal processing, which can effectively improve the efficiency of visual processing tasks. Both the pixel array and the pulse processor can be implemented based on variable resistor memories, so that they can be integrated on the same chip, eliminating the need for data transfer between visual perception and information processing to pass through an interface circuit and a transmission protocol, and improving the overall working efficiency of the visual perception and processing system.

[0082] In some alternative embodiments, the pulse processor 620 includes a neuron unit;

[0083] The neuron unit is configured to perform at least one arithmetic processing on the received input signal to obtain a processing result; wherein, the input signal is the pulse signal output by the pixel array 610.

[0084] In this embodiment, the pulse processor only includes one neuron unit, and the processing result is directly obtained by performing one-time processing on the pulse signal through this neuron unit. The neuron unit may include variable resistor memories distributed in an array. In this embodiment, the variable resistor memories still have the same electrical characteristics as the variable resistor memories provided in the above pixel units. By the variable resistor memories distributed in an array, some of the n*m pulse signals output from the pixel array are involved in the processing, and some pulse signals are not involved in the processing, so as to implement at least one arithmetic processing. The arithmetic processing may include but is not limited to at least one of the following: addition, subtraction, multiplication, division, etc.

[0085] In other alternative embodiments, the pulse processor 620 includes multiple neuron units;

[0086] The multiple neuron units include multiple pairs of neuron pairs, and each pair of neuron pairs includes a previous neuron unit and a next neuron unit;

[0087] Each neuron unit is configured to perform at least one arithmetic process on the received input signal to obtain an output signal; wherein, the input signal is a pulse signal output by a pixel array, or when the neuron unit is a next neuron unit, it is the output signal of the corresponding previous neuron unit;

[0088] In response to the neuron unit being the last neuron unit in the pulse processor, the output signal is used as the processing result.

[0089] In this embodiment, the pulse signal is processed by multiple neuron units to implement the processing of the pulse signal through a deep neural network model. The number and connection mode of the neuron units included in the pulse processor are determined by the corresponding deep neural network model, and the deep neural network model is determined by the corresponding specific application scenario. For example, in a classification scenario, the applied deep neural network model is a classification model; in a detection scenario, the applied deep neural network model is a detection model. In this embodiment, the neuron unit can directly process the pulse signal to implement various data processing methods. Each neuron unit corresponds to a network layer in the deep neural network model, and the processing of the network layer on data is implemented through different hardware structures and corresponding hardware parameters. When the neuron unit is not the last one, the obtained output signal is input to the next neuron unit to continue the processing, when corresponding to the deep neural network model.

[0090] Figure 7 It is a schematic circuit diagram of a neuron unit of a pulse signal processing circuit provided by an exemplary embodiment of the present disclosure. As Figure 7 shown, the neuron unit 70 includes a variable resistive memory 701 of i rows and j columns (an array composed of R11 to Rij); in the figure, S1 to Si are used to represent input signals, and P1 to Pj are used to represent output signals, without any referential meaning; each variable resistive memory 701 corresponds to trained calculation parameters, and the calculation parameters control whether the variable resistive memory is turned on. The variable resistive memory 701 provided in this embodiment also has the electrical characteristics of the variable resistive memory within a pixel unit, where the calculation parameter refers to the variable resistive memory 701 being in a high-resistance state or a low-configuration state; different application scenarios correspond to different calculation parameters. For example, a certain deep neural network model determines the calculation parameters corresponding to each variable resistive memory 701 in at least one corresponding neuron unit through training; the specific training process is not limited in this embodiment, and the training methods of existing neural network models can be used for the training of the calculation parameters in this embodiment.

[0091] Wherein, i and j are integers greater than or equal to 1 respectively.

[0092] The neuron unit 70 realizes at least one arithmetic processing of the input signal by turning on or off the variable resistor memory 701.

[0093] Wherein, the at least one arithmetic processing includes at least one of the following: addition, subtraction, multiplication, division.

[0094] The structure of the neuron unit provided in this embodiment is applicable to the pulse signal processing circuit provided in any of the above embodiments, and can be used to construct a pulse processor. In Figure 7 Among them, i pulse signals (when the pulse processor includes one neuron unit, or when the pulse processor includes multiple neuron units and this neuron unit is the first neuron unit, i = n*m) are input into the variable resistor memory array with i rows and j columns, and then j output signals are calculated and given to the next-level neuron unit for further arithmetic. Pre-trained calculation parameters are stored in the neuron unit, and these calculation parameters are embodied as the resistance values (high resistance state or low configuration state) of the variable resistor memory. For example, if a certain calculation parameter is 0, the corresponding variable resistor memory is in the high resistance state; if a certain calculation parameter is 1, the corresponding variable resistor memory is in the low resistance state. The pulse signal input to one end of the high resistance state variable resistor memory cannot be transmitted to the other end of the variable resistor memory, which is equivalent to completing a multiplication by 0 operation. The pulse signal input to one end of the low resistance state variable resistor memory can be transmitted to the other end of the variable resistor memory, which is equivalent to completing a multiplication by 1 operation. The signals on the same column of variable resistor memories are directly superimposed, which is equivalent to completing an addition operation. In this way, the neuron unit can complete the multiplication and addition operations between the input signal and the calculation parameters. Combining multiple neuron units (for example, in series, etc.) can complete a larger-scale deep neural network operation. Through the deep neural network operation, processing such as detection and recognition of visual information can be completed.

[0095] Since the components used in the pixel unit provided in the above embodiments of the present disclosure are few and the structure is simple, it is more convenient to provide a higher integration degree. The above Figure 6When the provided pulse signal processing circuit is integrated into a chip, a chip stacking process can be adopted, and multiple chips stacked vertically are used to integrate the pulse signal processing circuit. For example, a pixel array is fabricated on one chip (the first chip), and a pulse processor is fabricated on another chip (the second chip). By stacking the two chips and making signal connections between the first chip and the second chip at the output end of each pixel unit; the area occupied by the pulse signal processing circuit is further reduced by the chip stacking process, enabling the area of the pulse sensor to be further reduced. Optionally, when the number of neuron units included in the pulse processor is relatively large, in order to further reduce the area of the pulse sensor, multiple neuron units can be separately integrated on multiple chips (for example, each neuron unit is integrated on one chip, etc.), and signal connections between the chips are made at the output end of each neuron unit.

[0096] In addition, an embodiment of the present disclosure also provides an electronic device, including:

[0097] a processor, and a memory communicatively connected to the processor, further including the sensor pixel unit according to any one of the above embodiments or the pulse signal processing circuit according to any one of the above embodiments;

[0098] the memory stores computer-executable instructions;

[0099] the processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the pulse signal processing circuit.

[0100] The electronic device provided by the present disclosure can be incorporated into any one of the following: an image data acquisition device, an audio / video player, a navigation device, an entertainment device, a communication device, roadside traffic facilities, a device in a motor vehicle, an industrial detection device, a flight device, a medical device, a security device, etc.

[0101] The electronic device provided by the present disclosure can be applied to any one of the following: an image data acquisition device, an audio / video player, a navigation device, an entertainment device, a communication device, roadside traffic facilities, a device in a motor vehicle, an industrial detection device, a flight device, a medical device, a security device, etc.

[0102] Figure 8 It is a schematic structural diagram of an application embodiment of the electronic device of the present disclosure. Next, refer to Figure 8 to describe the electronic device according to an embodiment of the present disclosure. The electronic device can be either the first device or the second device or both, or a stand-alone device independent of them, and the stand-alone device can communicate with the first device and the second device to receive the input signals collected by them.

[0103] As Figure 8As shown, the electronic device includes one or more processors and a memory.

[0104] The processor can be a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and can control other components in the electronic device to perform desired functions.

[0105] The memory can store one or more computer program products. The memory can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. The non-volatile memory can include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer-readable storage media, and the processor can run the computer program products to implement the sensor pixel units, pulse signal processing circuits, and / or other desired functions of the various embodiments of the present disclosure described above.

[0106] In one example, the electronic device can further include: an input device and an output device, and these components are interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0107] In addition, the input device can include, for example, a keyboard, a mouse, and so on.

[0108] The output device can output various information to the outside, including the determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0109] Of course, for simplicity, Figure 8 only some of the components related to the present disclosure in the electronic device are shown, and components such as buses, input / output interfaces, etc. are omitted. In addition, according to specific application scenarios, the electronic device can further include any other appropriate components.

[0110] In addition to the above methods and devices, the embodiments of the present disclosure can also be computer program products, which include computer program instructions that, when run by a processor, cause the processor to execute the sensor pixel units or pulse signal processing circuits according to the various embodiments of the present disclosure described in the above part of this specification.

[0111] The computer program product can be written in any combination of one or more programming languages for programming code to perform the operations of the embodiments of the present disclosure. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The programming code can be executed entirely on the user's computing device, partially on the user's device, executed as an independent software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0112] In addition, an embodiment of the present disclosure can also be a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are run by a processor, the processor is caused to execute the sensor pixel unit or the pulse signal processing circuit according to various embodiments of the present disclosure described in the foregoing part of this specification.

[0113] The computer-readable storage medium can adopt any combination of one or more readable media. The readable media can be a readable signal medium or a readable storage medium. The readable storage medium can, for example, include but is not limited to an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0114] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present disclosure. In addition, the above-mentioned specific details are only for the purposes of illustration and facilitating understanding, rather than limitations. The above details do not limit the present disclosure to necessarily adopt the above specific details for implementation.

[0115] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments.

[0116] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The words "or" and "and" used herein refer to the phrase "and / or", and can be used interchangeably with it, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to", and can be used interchangeably with it.

[0117] The methods and apparatuses of this disclosure can be implemented in many ways. For example, the methods and apparatuses of this disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of the steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the specific order described above, unless otherwise specifically stated. In addition, in some embodiments, this disclosure can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the methods according to this disclosure. Therefore, this disclosure also covers the recording medium storing the programs for executing the methods according to this disclosure.

[0118] It should also be noted that in the apparatuses, equipment, and methods of this disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of this disclosure.

[0119] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0120] The above description has been given for purposes of illustration and description. In addition, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions, and sub-combinations thereof.

Claims

1. A sensor pixel unit, characterized in that: include: Photodiode, variable resistance memory and signal output circuit; One end of the photodiode is connected to the power signal, and the other end is connected to the variable resistance memory and the signal output circuit, and the photodiode is used to receive the light signal within the exposure time to generate a voltage signal; One end of the variable resistance memory is connected to the photodiode, and the other end is grounded; The signal output circuit is used to obtain and output a target signal based on the voltage signal.

2. The pixel unit according to claim 1, characterized in that: When the variable resistance memory is in a high resistance state, the variable resistance memory disconnects the photodiode from the ground; when the variable resistance memory is in a low resistance state, the variable resistance memory connects the photodiode to the ground.

3. The pixel unit according to claim 1 or 2, characterized in that: The target signal is a pulse signal; The signal output circuit includes a two-stage inverter; The two-stage inverter is used to convert the voltage signal to obtain the pulse signal.

4. The pixel unit according to claim 3, characterized in that: The two-stage inverter comprises a first inverter and a second inverter connected in series; The input end of the first inverter is connected to the photodiode and the variable resistance memory, and the output end is connected to the input end of the second inverter; The input end of the second inverter is connected to the output end of the first inverter, and the output end serves as the output end of the sensor pixel unit.

5. A pulse signal processing circuit, characterized in that: include: A pixel array and a pulse processor consisting of n rows and m columns of sensor pixel units according to any one of claims 1 to 4; wherein n and m are integers greater than 1 respectively; The pixel array is used to process the received light signal to obtain a pulse signal, each column of the pixel units is connected in series to the pulse processor, and the pulse signal is sent to the pulse processor; The pulse processor is used to receive the pulse signal and output a processing result corresponding to the pulse signal.

6. The pulse signal processing circuit according to claim 5, characterized in that: The pulse processor includes one neuron unit or a plurality of neuron units; The plurality of neuron units include a plurality of neuron pairs, each of the neuron pairs includes a previous neuron unit and a next neuron unit; Each of the neuron units is used to obtain an output signal for a received input signal; wherein the input signal is the pulse signal output by the pixel array, or the output signal of the corresponding previous neuron unit when the neuron unit serves as the next neuron unit; In response to the neuron unit being the last neuron unit in the pulse processor, the output signal is used as the processing result.

7. The pulse signal processing circuit according to claim 6, characterized in that: The neuron unit includes a variable resistance memory with i rows and j columns; each of the variable resistance memories corresponds to a trained calculation parameter, and the calculation parameter indicates that the state of the variable resistance memory is a high resistance state or a low resistance state; i and j are integers greater than or equal to 1 respectively; The neuron unit implements at least one operation processing on the input signal according to the state of the variable resistance memory; wherein the at least one operation processing includes at least one of the following: addition, subtraction, multiplication, and division.

8. The pulse signal processing circuit according to claim 6 or 7, characterized in that: Also includes: A first chip and a second chip stacked up and down; integrating the pixel array in the first chip; The pulse processor is integrated in the second chip, and a signal connection is made between the first chip and the second chip at the output end of each pixel unit.

9. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor, further comprising the sensor pixel unit according to any one of claims 1 to 4 or the pulse signal processing circuit according to any one of claims 5 to 8; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the pulse signal processing circuit.

10. The device according to claim 9, characterized in that The electronic device is included in any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial testing equipment, flight equipment, medical equipment, and security equipment.

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