Ferroelectric random access memory device

Abstract

The utility model provides a ferroelectric random access memory device, which comprises a transistor, and the transistor comprises a gate electrode; the ferroelectric layer is positioned on the gate electrode; the channel layer is positioned on the ferroelectric layer; a cap layer over the channel layer, where the cap layer includes one or more of CeOx, BeOx, InOx, GaOx, AlOx, SnOx, VOx, WOx, TiOx, ZrOx, NbOx, HfOx, SiOx, TaOx, a binary metal oxide based on any combination of the aforementioned metal oxides, or a ternary metal oxide based on any combination of the aforementioned metal oxides; the dielectric layer is positioned on the top cover layer; and a source and a drain contacting one or more of the cap layer, the channel layer, or the ferroelectric layer.

Description

Technical Field

[0001] The utility model relates to a ferroelectric random access memory device. Background Art

[0002] Many modern electronic devices include non-volatile memory. Non-volatile memory is an electronic memory that can store data without power. A promising candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic and thin-film transistor manufacturing processes. Summary of the Utility Model

[0003] The utility model provides a ferroelectric random access memory device, comprising: a transistor, including: a gate electrode; a ferroelectric layer located above the gate electrode; a channel layer located above the ferroelectric layer; a top cover layer located above the channel layer, wherein the top cover layer comprises one or more of the following: CeO x , BeO x , InO x , GaO x , AlO x , SnO x , VO x , WO x , TiO x , ZrO x , NbO x , HfO x , SiO x , TaO x , a binary metal oxide based on any combination of the foregoing metal oxides, or a ternary metal oxide based on any combination of the foregoing metal oxides; a dielectric layer located above the top cover layer; and a source electrode and a drain electrode contacting one or more of the top cover layer, the channel layer, or the ferroelectric layer. Description of the Drawings

[0004] Aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0005] Figure 1A is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0006] Figure 1B is a flowchart that is part of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0007] Figure 1C is a flowchart that is part of a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0008] Figure 1D is a flowchart that is part of a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0009] Figures 2 to 17 Schematically shows various stages of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0010] Figure 18 Schematically shows a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 19 Schematically shows a semiconductor device according to another embodiment of the present disclosure.

[0012] Figure 20 Schematically shows a semiconductor device according to another embodiment of the present disclosure.

[0013] Figure 21A Shows an in-situ thermal annealing process according to some embodiments of the present disclosure in the form of a diagram.

[0014] Figure 21B is a flowchart of a method of forming a seed layer according to some embodiments of the present disclosure.

[0015] Figure 21C is a flowchart of a method of forming a memory layer according to some embodiments of the present disclosure. Detailed Description

[0016] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. Such reuse is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and similar terms may be used herein to describe the relationship of one device or feature shown in the figures to another (other) device or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly as well.

[0018] The foregoing generally outlines some aspects of the embodiments described in the present disclosure. Those of ordinary skill in the art should readily understand other modifications that can be contemplated within the scope of the present disclosure. Additionally, although method embodiments may be described in a specific order, various other method embodiments may be implemented in any logical order and may include fewer or more steps than those described herein. In the present disclosure, depending on the context, the source / drain region may refer to the source or the drain individually or jointly.

[0019] Figure 1A is a flowchart of a method 100 of manufacturing a semiconductor device 200 (e.g., a ferroelectric random access memory (FeRAM) device) according to an embodiment of the present disclosure. Referring to Figures 2 to 17 the method 100 is described, Figures 2 to 17 schematically shows the various stages of manufacturing the semiconductor device 200. As will be described in more detail below, referring to Figures 18 to 20 the individual embodiments of the semiconductor device 200 shown in Figures 1B to 1D a part of the method 100 shown according to different embodiments of the present disclosure is described.

[0020] As Figure 2As shown in, at block 102 of method 100, a gate electrode 204 is formed over a substrate 202. For example, the gate electrode 204 may contact the surface (e.g., top surface) of the substrate 202. The substrate 202 is configured to form a semiconductor device 200 on the substrate 202. The substrate 202 may be any suitable substrate, such as a semiconductor substrate or a silicon-on-insulator (SOI) substrate including an insulator structure. In some embodiments, the gate electrode 204 may be formed over the substrate 202 by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), direct current sputtering, other suitable processes, and / or combinations thereof). In some embodiments, the gate electrode 204 may include one or more layers formed of a conductive material (e.g., polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof). In some embodiments, the gate electrode 204 is buried in the substrate 202.

[0021] As Figure 3 shown in, at block 104 of method 100, an optional Ta-containing layer 206 is formed over the gate electrode 204. For example, the optional Ta-containing layer 206 may contact the surface (e.g., top surface) of the gate electrode 204. In some embodiments, the optional Ta-containing layer 206 may be formed over the gate electrode 204 by a deposition process (e.g., PVD, plasma-enhanced CVD (PE-CVD), plasma-enhanced ALD (PE-ALD), other suitable processes, and / or combinations thereof). In some embodiments, the optional Ta-containing layer 206 may include tantalum, tantalum nitride, other suitable Ta-containing materials, and / or combinations thereof.

[0022] As Figures 4 to 6 shown in, at block 106 of method 100, a ferroelectric layer 208 is formed over the gate electrode 204. For example, the ferroelectric layer 208 may contact the surface (e.g., top surface) of the gate electrode 204. In some embodiments, for example, when the optional Ta-containing layer 206 is present, the ferroelectric layer 208 may be formed over the optional Ta-containing layer 206 and over the gate electrode 204. For example, the ferroelectric layer 208 may contact the surface (e.g., top surface) of the optional Ta-containing layer 206.

[0023] As shown Figure 4 in, at block 106a of method 100, a seed layer 210 is formed over the gate electrode 204. For example, the seed layer 210 may contact the surface (e.g., the top surface) of the gate electrode 204. In some embodiments, for example, when there is an optional Ta-containing layer 206, the seed layer 210 may be formed over the optional Ta-containing layer 206. For example, the seed layer 210 may contact the surface (e.g., the top surface) of the optional Ta-containing layer 206. The seed layer 210 may have a thickness in the range between about 0.1 nanometer and about 10 nanometers.

[0024] The seed layer 210 may be configured to promote crystallization and / or form a desired crystal structure in a layer (e.g., a memory layer 212, as shown Figure 5 in) of the ferroelectric layer 208 subsequently formed over the seed layer 210. For example, the seed layer 210 may promote an orthorhombic (O-phase) crystal phase in the memory layer 212 relative to monoclinic (m-phase), cubic (c-phase), and / or tetragonal (t-phase) crystal phases. In some embodiments, the seed layer 210 may inhibit the transformation of the O-phase crystal structure in the memory layer 212 into an m / t / c-phase crystal structure. In some embodiments, the ferroelectric properties of the memory layer 212 may be improved based on the presence of the seed layer 210. For example, the memory layer 212 may be characterized by an increase in remnant polarization (P R ).

[0025] In some embodiments, the seed layer 210 may be a metal oxide material (e.g., tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), TiO 2 , BaO, SrO, Y 2 O 3 , HfSiO 2 , zirconium oxide - yttrium oxide (ZrO 2 -Y 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium zirconium oxide (Hf x Zr 1-x O 2, where 0 ≦ x ≦ 1), other materials with higher dielectric constants that reduce the EIL, other suitable materials, and / or combinations thereof). The seed layer 210 may include a single layer formed of a metal oxide material or multiple layers formed of metal oxide materials that may have different compositions. In some embodiments, the material of the seed layer 210 may have a crystal structure including a cubic crystal phase, a tetragonal crystal phase, and / or an orthorhombic crystal phase.

[0026] In some embodiments, the seed layer 210 may be formed by a deposition process (such as ALD, pulsed laser deposition (PLD), other suitable processes, and / or combinations thereof). In some embodiments, the seed layer 210 may be formed by Figure 21A the in-situ thermal annealing process shown in the form of a diagram. The in-situ thermal annealing process may increase the crystallinity of the seed layer 210. Figure 21B Illustrates a method 300 for forming a seed layer 210 according to an embodiment of the present disclosure. At block 310 of method 300, H 2 O, O 2 or O 3 is deposited as a first pulse. The first pulse is used to provide O atoms to form the seed layer 210. At block 320 of method 300, the seed layer 210 is annealed by heating to a temperature in the range between about 400 °C and about 700 °C for about 1 minute to about 5 minutes.

[0027] As Figure 5 shown, at block 106b of method 100, a memory layer 212 is formed over the seed layer 210. For example, the memory layer 212 may contact the surface (such as the top surface) of the seed layer 210. The memory layer 212 may have a thickness in the range between about 1 nm and about 100 nm. In some embodiments, the memory layer 212 may include hafnium zirconium oxide (Hf x Zr 1-x O y , where 0 ≦ x ≦ 1 and y = 2x), Ta-doped HfO 2 , Al-doped HfO 2 , Si-doped HfO 2 , In-doped HfO 2 , Zr-doped HfO 2 , Sc-doped HfO 2 , Y-doped HfO 2 , Gd-doped HfO 2 , La-doped HfO 2 , Sr-doped HfO 2, other suitable materials and / or combinations thereof. In some embodiments, the memory layer 212 can be formed by a deposition process (such as ALD, PVD (such as co-sputtering PVD), other suitable processes, and / or combinations thereof). Figure 21C Illustrates a method 400 for forming a memory layer 212 according to an embodiment of the present disclosure. At block 410 of method 400, a first pulse of a Hf precursor (such as HfCl 4 ) is deposited by ALD. The first pulse is used to provide Hf atoms to form a part of the memory layer 212. At block 420 of method 400, a second pulse of H 2 O is deposited by ALD. The second pulse is used to provide O atoms to form a part of the memory layer 212. At block 430 of method 400, a third pulse of a Zr precursor (such as ZrCl 4 ) is deposited by ALD. The third pulse is used to provide Zr atoms to form a part of the memory layer 212. At block 440 of method 400, a fourth pulse of H 2 O is deposited by ALD. The fourth pulse is used to provide O atoms to form a part of the memory layer 212. In some embodiments, method 400 can be repeated to form a memory layer having a thickness in the range between about 10 nanometers and about 12 nanometers.

[0028] As Figure 6 shown, at block 106c of method 100, an interlayer 214 is formed over the memory layer 212. For example, the interlayer 214 can contact the surface (such as the top surface) of the memory layer 212. In some embodiments, the interlayer 214 can be a metal oxide material (such as tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), TiO 2 , BaO, SrO, Y 2 O 3 , HfSiO 2 , zirconium oxide - yttrium oxide (ZrO 2 - Y 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium zirconium oxide (Hf x Zr 1-x O 2 , where 0 ≦ x ≦ 1), other materials with higher dielectric constants that reduce the EIL, other suitable materials, and / or combinations thereof). In some embodiments, the interlayer 214 can include the same material as the seed layer 210. In other embodiments, the interlayer 214 can include one or more materials different from the seed layer 210.

[0029] In some embodiments, the interlayer 214 can be formed by a deposition process (such as ALD, pulsed laser deposition (PLD), other suitable processes, and / or combinations thereof). In some embodiments, similar to the process for the seed layer 210 described above, the interlayer 214 is formed by an in-situ thermal annealing process. In some embodiments, based on the annealing temperature, the process for forming the interlayer 214 can be different from the process for the seed layer 210. For example, the annealing temperature for the interlayer 214 can be lower than the annealing temperature for the seed layer 210. For example, the annealing temperature for the interlayer 214 can be lower than about 350 °C (e.g., in the range between about 300 °C and 350 °C).

[0030] In some embodiments, the interlayer 214 can promote the crystallization of the memory layer 212 and / or the channel layer 216 (such as increasing the crystallinity and / or forming a desired crystal phase), thereby improving device performance. For example, based on the contact with the interlayer 214 (e.g., compared to alternative materials, with tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), TiO 2 , BaO, SrO, Y 2 O 3 , HfSiO 2 , zirconium oxide - yttrium oxide (ZrO 2 - Y 2 O 3 ), aluminum oxide (Al 2 O 3 ), and / or hafnium zirconium oxide (Hf x Zr 1-x O 2 )) of the contact, the crystallization of the memory layer 212 and / or the channel layer 216 is enhanced.

[0031] As Figure 7 shown in, at block 108 of method 100, a channel layer 216 is formed over the ferroelectric layer 208. For example, the channel layer 216 can be formed over the interlayer 214 of the ferroelectric layer 208. For example, the channel layer 216 can contact the surface (such as the top surface) of the interlayer 214. In some embodiments, the channel layer 216 can be formed by a deposition process (such as PVD, CVD, ALD, DC sputtering, other suitable processes, and / or combinations thereof).

[0032] In some embodiments, the channel layer 216 may include amorphous indium gallium zinc oxide (a-IGZO), InO, ITO, GaZnO, InGaAs, GaN, AlGaAs, Si, Ge, C, SiC, SiGe, SiGeC, Ga 2 O 3 , II-VI compound semiconductors (such as CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, MgO or GdO, and other examples), III-V compound semiconductors (such as GaAs, InP, GaP, GaN, AlAs, AlGaAs, GaInP, AlInGaP or GaAsIn, and other examples), M x M′ y Zn z O (where 0 < (x, y, z) < 1, M may be a metal selected from the group consisting of indium (In) and tin (Sn) or a combination thereof, and M′ may be a metal selected from the group consisting of: gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La) and gadolinium (Gd) or a combination thereof), other suitable materials and / or combinations thereof. In some embodiments, the channel layer 216 may be a substituted form of amorphous indium gallium zinc oxide (a-IGZO), where indium may be partially or completely replaced by another metal (such as tin (Sn)), and the other metal may be configured to provide a high carrier mobility within the channel layer 216. As an alternative, or additionally, gallium may be partially or completely replaced by another metal (such as one or more of the following: hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La) or gadolinium (Gd)), and the other metal may be configured to reduce oxygen vacancies and lower surface states (D it ).

[0033] As Figure 8 shown in x , at block 110 of method 100, a capping layer 218 is formed over the channel layer 216. For example, the capping layer 218 may contact the surface (such as the top surface) of the channel layer 216. In some embodiments, the capping layer 218 may be formed by a deposition process (such as PVD, PE-CVD, PE-ALD, other suitable processes and / or combinations thereof). In some embodiments, the capping layer 218 may include a metal oxide having a bond dissociation energy greater than that of Zn-O (such as CeO x , BeO x , InO x , GaO x , AlO x , SnOx , WO x , TiO x , ZrO x , NbO x , HfO x , SiO x or TaO x , binary metal oxides based on any combination of the foregoing metal oxides (e.g., InGaO x or InAlO x , and other examples), ternary metal oxides based on any combination of the foregoing metal oxides, other suitable materials, and / or combinations thereof). In some embodiments, the capping layer 218 can be annealed by heating to a temperature below 350 °C (e.g., in a range between about 300 °C and 350 °C). In some embodiments, the heating time can be greater than about 1 hour (e.g., in a range between about 1 hour and about 1.5 hours). In some embodiments, similar to the processes for the seed layer 210 and the interlayer 214 described above, the capping layer 218 can be formed by an in-situ thermal annealing process. In some embodiments, the in-situ thermal annealing process can include a first pulse of O 2 deposited by ALD, followed by heating, and a second pulse of a metal precursor deposited by ALD.

[0034] After forming the capping layer 218 over the channel layer 216, one or more layers of the semiconductor device 200 can be patterned to form a multilayer structure 220. For example, the multilayer structure 220 can include a gate electrode 204, an optional Ta-containing layer 206, a ferroelectric layer 208 (e.g., a seed layer 210, a memory layer 212, and an interlayer 214), a channel layer 216, and a capping layer 218. The multilayer structure 220 can include a right sidewall, a left sidewall opposite the right sidewall, a bottom (e.g., corresponding to the gate electrode 204), and a top opposite the bottom and / or opposite the substrate 202 (e.g., corresponding to the capping layer 218). A recess 222 (e.g., a trench) can surround the multilayer structure 220 (e.g., beside the right sidewall and the left sidewall of the multilayer structure 220). For example, the recess 222 can be defined above the surface of the substrate 202 (e.g., above the top surface of the substrate 202 that can contact the gate electrode 204).

[0035] As described above, in some embodiments, the gate electrode 204 is buried in the substrate 202. An opening can be formed in the substrate 202, and the gate electrode 204 can be formed in the opening. Then, an optional Ta-containing layer 206, a ferroelectric layer 208, a channel layer 216, and a capping layer 218 are formed and patterned to form the multilayer structure 220.

[0036] As used herein, the terms "pattern", "patterned", and "patterning" may refer to a multi-step process including, for example, forming a mask over the upper surface of an individual layer, patterning the mask using photolithography to remove some portions of the mask and expose some portions of the upper surface of the individual layer, etching through the patterned mask to remove some portions of the individual layer, and / or removing the patterned mask using a suitable process (e.g., ashing or dissolving using a solvent among other examples).

[0037] As Figure 9 shown, at block 112 of method 100, a first interlayer dielectric (ILD) layer 224 is formed. For example, the first interlayer dielectric layer 224 may be formed in the recess 222 and / or the first interlayer dielectric layer 224 may surround the multi-layer structure 220. For example, the first interlayer dielectric layer 224 may contact the substrate 202 (e.g., the top surface of the substrate 202), the right sidewall and / or the left sidewall of the multi-layer structure 220.

[0038] In some embodiments, a portion of the first interlayer dielectric layer 224 may be formed over the capping layer 218. For example, the portion of the first interlayer dielectric layer 224 may contact the top surface of the capping layer 218. However, as Figure 9 shown, the portion of the first interlayer dielectric layer 224 that is formed over the capping layer 218 may be removed (e.g., during one or more subsequent steps) such that the capping layer 218 may define the top surface of the semiconductor device 200. For example, the portion of the first interlayer dielectric layer 224 that is formed over the capping layer 218 may be removed by one or more processes commonly used in the semiconductor manufacturing field for removing materials and / or material layers (e.g., chemical mechanical polishing and / or etching, among other examples).

[0039] At block 114 of method 100, after forming the capping layer 218, the semiconductor device 200 is annealed at a temperature below 350°C. In some embodiments, the semiconductor device 200 may be annealed after forming the first interlayer dielectric layer 224 as described above and / or after removing the portion of the first interlayer dielectric layer 224 that is formed over the capping layer 218. In some embodiments, the annealing process at block 114 may be the above-described annealing process used to form the capping layer 218 at block 110, or may be another annealing process that is also performed in addition to the above-described annealing process used to form the capping layer 218 at block 110. In other words, the annealing of the capping layer 218 may occur before or after patterning for forming the multi-layer structure 220 and / or before or after forming the first interlayer dielectric layer 224.

[0040] In some embodiments, one or more features associated with the semiconductor device 200 and / or the fabrication of the semiconductor device 200 set forth herein can increase the resistance to hydrogen diffusion from the surrounding layers into the multi-layer structure 220 (e.g., into the channel layer 216), which may also be referred to herein as "hydrogen resist", thereby improving device performance. In some embodiments, in the semiconductor device 200 (e.g., in one or more layers surrounding the multi-layer structure 220), the sources of hydrogen to be blocked may include the first interlayer dielectric layer 224, the second interlayer dielectric layer 228, and / or the third interlayer dielectric layer 246 (e.g., hydrogen-containing precursors in the respective layers). For example, based on the presence of the capping layer 218 (e.g., based on the properties and / or characteristics of the capping layer 218 regarding the above-described one or more deposition processes and / or material compositions of block 110), the semiconductor device 200 (e.g., the multi-layer structure 220) can be annealed (e.g., at block 114) at a temperature lower than other temperatures known in the art for annealing similar structures (e.g., lower than 350 °C). For example, based on the presence of the capping layer 218, the temperature required for the channel layer 216 to recrystallize to form a crystal structure (e.g., to increase crystallinity and / or form a desired crystal phase) can be reduced from the normal level. In some embodiments, annealing at a lower temperature (e.g., lower than 350 °C) can reduce and / or prevent H 2 from diffusing from the surrounding layers (e.g., from the first interlayer dielectric layer 224, the second interlayer dielectric layer 228, and / or the third interlayer dielectric layer 246) into the multi-layer structure 220 (e.g., into the channel layer 216).

[0041] As Figure 10 shown, at block 116 of method 100, a dielectric layer 226 (which may also be referred to herein as the "first dielectric layer") is formed over the capping layer 218. For example, the dielectric layer 226 can contact the top surface of the capping layer 218. In some embodiments, the dielectric layer 226 can be formed over the first interlayer dielectric layer 224. For example, the dielectric layer 226 can contact the surface (e.g., the top surface) of the first interlayer dielectric layer 224. In some embodiments, the dielectric layer 226 can be formed by a deposition process (e.g., PVD, CVD, ALD, sputtering (e.g., DC sputtering), other suitable processes, and / or combinations thereof). In some embodiments, the dielectric layer 226 can include AlO x (e.g., Al 2 O 3 ), SiN x (e.g., Si 3 N 4 ), TiC, TiO 2 , other suitable materials, and / or combinations thereof.

[0042] In some embodiments, dielectric layer 226 may be a hydrogen resistant layer configured to improve device performance. For example, dielectric layer 226 may reduce and / or prevent H 2 Diffusion from surrounding layers (e.g., one or more layers above dielectric layer 226, as described in more detail below) to one or more layers below dielectric layer 226 (e.g., one or more layers of multilayer structure 220, such as channel layer 216). For example, dielectric layer 226 may include AlO x (For example, Al 2 O 3 )、SiN x (For example, Si 3 N 4 ), TiC and / or TiO 2 The material composition may provide increased resistance to hydrogen diffusion compared to alternative compositions.

[0043] like Figure 11 As shown in FIG. 1 , at block 118 of method 100, a second interlayer dielectric layer 228 is formed. For example, the second interlayer dielectric layer 228 may be formed on the dielectric layer 226 and / or on the cap layer 218. For example, the second interlayer dielectric layer 228 may contact a surface (e.g., a top surface) of the dielectric layer 226.

[0044] After forming the second interlayer dielectric layer 228, one or more layers of the semiconductor device 200 may be patterned to form a source / drain (S / D) contact region 230 (which may also be referred to herein as a "first S / D contact region"). For example, Figure 11 As shown, the S / D contact region 230 may include a first recess (e.g., a first trench) and a second recess (e.g., a second trench). The S / D contact region 230 may include a surface 232 (e.g., a first (right) sidewall, a second (left) sidewall opposite to the first sidewall (e.g., facing away from the first sidewall), and / or a bottom wall). For example, the volume of the S / D contact region 230 may be defined between the first sidewall and the second sidewall and above the bottom wall. The S / D contact region 230 may extend to and / or within the multilayer structure 220. As described below with reference to Figures 1B to 1D In more detail, according to different embodiments of the present disclosure, the depths of the S / D contact region 230, the layer of the multilayer structure 220 defining the bottom wall of the S / D contact region 230, and / or the layer of the semiconductor device 200 defining the first sidewall and the second sidewall of the S / D contact region 230 may be different.

[0045] according to Figure 1B At block 118a of method 100, the dielectric layer 226 is patterned such that the bottom wall of the S / D contact region 230 is defined by the cap layer 218, as shown in FIG. Figure 11As shown. For example, the S / D contact region 230 may extend to the multi-layer structure 220 (e.g., to the top of the multi-layer structure 220 as described above), without extending into and / or through the capping layer 218 of the multi-layer structure 220. For example, the depth of the S / D contact region 230 may correspond to the combined depth of the second interlayer dielectric layer 228 and the dielectric layer 226. The first sidewall and the second sidewall of the S / D contact region 230 may be defined by the second interlayer dielectric layer 228 and the dielectric layer 226.

[0046] According to Figure 1C , at block 118a' of method 100, the dielectric layer 226 and the capping layer 218 are patterned such that the bottom wall of the S / D contact region 230 is defined by the channel layer 216, as Figure 19 shown. For example, the S / D contact region 230 may extend into the multi-layer structure 220 (e.g., through the capping layer 218), without extending into and / or through the channel layer 216. For example, the depth of the S / D contact region 230 may correspond to the combined depth of the second interlayer dielectric layer 228, the dielectric layer 226, and the capping layer 218. For example, the first sidewall and the second sidewall of the S / D contact region 230 may be defined by the second interlayer dielectric layer 228, the dielectric layer 226, and the capping layer 218.

[0047] According to Figure 1D , at block 118a'' of method 100, the dielectric layer 226, the capping layer 218, and the channel layer 216 are patterned such that the bottom wall of the S / D contact region 230 is defined by the ferroelectric layer 208 (e.g., defined by the dielectric layer 214 of the ferroelectric layer 208, as Figure 20 shown). For example, the S / D contact region 230 may extend into the multi-layer structure 220 (e.g., through the capping layer 218 and the channel layer 216), without extending into and / or through the dielectric layer 214. For example, the depth of the S / D contact region 230 may correspond to the combined depth of the second interlayer dielectric layer 228, the dielectric layer 226, the capping layer 218, and the channel layer 216. For example, the first sidewall and the second sidewall of the S / D contact region 230 may be defined by the second interlayer dielectric layer 228, the dielectric layer 226, the capping layer 218, and the channel layer 216.

[0048] As Figures 12 to 15 shown in, at block 120 of method 100, source contacts and drain contacts (collectively referred to as the S / D contact structure 234) are formed in the dielectric layer 226. The S / D contact structure 234 (which may also be referred to herein as the "first S / D contact structure") may be defined by the surface 232 of the S / D contact region 230. In some embodiments, the source contacts and the drain contacts may be formed to contact the capping layer 218 (e.g., according to Figure 1B, at block 120’, as Figure 15 shown), the channel layer 216 (e.g., according to Figure 1C , at block 120’’, as Figure 19 shown) and / or the ferroelectric layer 208 (e.g., according to Figure 1D , at block 120’’’, as Figure 20 shown). In some embodiments, the tightness and / or contact between the S / D contact structure 234 and the ferroelectric layer 208 may cause an increase in the polarization value of the ferroelectric layer 208, thereby improving device performance. For example, in Figure 19 , the S / D contact region 230 is over-etched to reach the channel layer 216, and forming the S / D contact structure 234 that contacts the channel layer 216 as compared to, for example, the S / D contact structure 234 that forms the contact capping layer 218 (as Figure 15 shown) may cause an increase in the polarization value of the ferroelectric layer 208. Similarly, in Figure 20 , the S / D contact region 230 is over-etched to reach the ferroelectric layer 208, and forming the S / D contact structure 234 that contacts the ferroelectric layer 208 as compared to, for example, the S / D contact structure 234 that forms the contact capping layer 218 (as Figure 15 shown) and the S / D contact structure 234 that forms the contact channel layer 216 (as Figure 19 shown) both may cause an increase in the polarization value of the ferroelectric layer 208. In other words, the polarization value of the ferroelectric layer 208 may be negatively correlated with the distance between the S / D contact structure 234 and the ferroelectric layer 208 (e.g., the polarization value of the S / D contact structure that contacts the ferroelectric layer > the polarization value of the S / D contact structure that contacts the channel layer > the polarization value of the S / D contact structure that contacts the capping layer).

[0049] In some embodiments, the S / D contact structure 234 may be a hydrogen-resistant layer configured to improve device performance. For example, the S / D contact structure 234 may reduce and / or prevent H 2 from diffusing from the surrounding layers (e.g., as will be described in more detail below, one or more layers above or beside the S / D contact structure 234, such as a subsequent interlayer dielectric layer formed using a precursor containing H 2 ) into one or more layers (e.g., one or more layers of the multilayer structure 220, such as the channel layer 216) located below the dielectric layer 226. For example, the material composition of the S / D contact structure 234 including a combination of the following material components may increase the resistance to hydrogen diffusion compared to alternative components.

[0050] As Figure 12As shown, at block 120a of method 100, a first conductive layer 236 is formed. As described above with reference to the source and drain contacts of the S / D contact structure 234, the first conductive layer 236 can be formed over the capping layer 218, the channel layer 216, and / or the ferroelectric layer 208. In some embodiments, the first conductive layer 236 can be formed by a deposition process (such as PVD, CVD, PE-CVD, ALD, PE-ALD, DC sputtering, other suitable processes, and / or combinations thereof). In some embodiments, the first conductive layer 236 can include TiN, TaN, WN, other suitable materials, and / or combinations thereof.

[0051] As Figure 13 shown, at block 120b of method 100, a second conductive layer 238 is formed over the first conductive layer 236. For example, the second conductive layer 238 can contact one or more surfaces of the first conductive layer 236 (such as the first (right) sidewall, the second (left) sidewall opposite the first sidewall (e.g., facing the first sidewall), and / or the top wall). In some embodiments, the second conductive layer 238 can be formed by a deposition process (such as PVD, CVD, PE-CVD, ALD, PE-ALD, DC sputtering, other suitable processes, and / or combinations thereof). In some embodiments, the second conductive layer 238 can include Ti, Zr, Th, V, Pd, Cu, W, other suitable materials, and / or combinations thereof.

[0052] As Figure 14 shown, at block 120c of method 100, a third conductive layer 240 is formed over the second conductive layer 238. For example, the third conductive layer 240 can contact one or more surfaces of the second conductive layer 238 (such as the first (right) sidewall, the second (left) sidewall opposite the first sidewall (e.g., facing the first sidewall), and / or the top wall). In some embodiments, the third conductive layer 240 can be formed by a deposition process (such as PVD, CVD, PE-CVD, ALD, PE-ALD, DC sputtering, other suitable processes, and / or combinations thereof). In some embodiments, the third conductive layer 240 can include TiN, TaN, WN, other suitable materials, and / or combinations thereof.

[0053] As Figure 15As shown, at block 120d of method 100, a conductive fill layer 242 is formed over the third conductive layer 240. For example, the conductive fill layer 242 may contact one or more surfaces of the third conductive layer 240 (e.g., a first (right) sidewall, a second (left) sidewall opposite (e.g., facing) the first sidewall, and / or a top wall). In some embodiments, the conductive fill layer 242 may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, PE-ALD, DC sputtering, other suitable processes, and / or combinations thereof). In some embodiments, the conductive fill layer 242 may comprise Ru, Al, Pt, Ag, Co, Fe, Sn, Ni, other suitable materials, and / or combinations thereof. In some embodiments, the conductive fill layer 242 may not comprise Cu. For example, a material composition of the conductive fill layer comprising Ru, Al, Pt, Ag, Co, Fe, Sn, and / or Ni and not comprising Cu may obviate the need for a barrier layer (e.g., one or more of the first conductive layer 236, the second conductive layer 238, or the third conductive layer 240), and thus the barrier layer may not be included to reduce and / or prevent Cu diffusion as compared to an alternative composition comprising Cu. However, embodiments of the present disclosure include a barrier layer for enhancing resistance to hydrogen diffusion.

[0054] As described above, the S / D contact structure 234 may be a hydrogen-resistant layer configured to improve device performance. In some embodiments, the presence of multiple independent hydrogen-resistant layers (e.g., the first conductive layer 236, the second conductive layer 238, the third conductive layer 240, and the conductive fill layer 242) may collectively increase the resistance to hydrogen diffusion as compared to a multi-layer or multi-metal structure having fewer independent hydrogen-resistant layers and / or an alternative composition of independent hydrogen-resistant layers.

[0055] As Figures 16 to 18 shown, at block 122 of method 100, the manufacturing steps associated with blocks 116, 118, and 120 are repeated. For example, one or more interconnection layers may be formed over the semiconductor device 200.

[0056] As Figure 16 shown, a second dielectric layer 244 is formed over the first S / D contact structure 234 and the second interlayer dielectric layer 228. The second dielectric layer 244 may contact the surface (e.g., the top surface) of the first S / D contact structure 234 and / or the second interlayer dielectric layer 228. As Figure 17As shown, a third interlayer dielectric layer 246 is formed. For example, the third interlayer dielectric layer 246 can be formed over the second dielectric layer 244 and / or over the first S / D contact structure 234. For example, the third interlayer dielectric layer 246 can contact the surface (e.g., the top surface) of the second dielectric layer 244. The second dielectric layer 244 can be formed by the same or similar techniques as described above for the first dielectric layer 226, and the second dielectric layer 244 can include the same or similar components as described above for the first dielectric layer 226.

[0057] After forming the third interlayer dielectric layer 246, one or more layers of the semiconductor device 200 can be patterned to form a second S / D contact region 248. For example, as Figure 17 shown, the second S / D contact region 248 can include a first recess (e.g., a first trench) and a second recess (e.g., a second trench). The second S / D contact region 248 can include a surface 250 (e.g., a first (right) sidewall, a second (left) sidewall opposite (e.g., facing away from) the first sidewall, and / or a bottom wall). For example, the volume of the second S / D contact region 248 can be defined between the first sidewall and the second sidewall and above the bottom wall. The second S / D contact region 248 can extend to and / or extend within the first S / D contact structure 234. The second dielectric layer 244 can be patterned such that the bottom wall of the second S / D contact region 248 is defined by the first S / D contact structure 234. For example, the second S / D contact region 248 can extend to the first S / D contact structure 234 (e.g., the top of the first S / D contact structure 234, as described above), but not into the first S / D contact structure 234. For example, the depth of the second S / D contact region 248 can correspond to the combined depth of the third interlayer dielectric layer 246 and the second dielectric layer 244.

[0058] As Figure 18As shown, source and drain contacts (collectively referred to as second S / D contact structure 252) are formed in the second dielectric layer 244. For example, the second S / D contact structure 252 can be defined by the surface 250 of the second S / D contact region 248. The source and drain contacts can be formed to contact the first S / D contact structure 234. A first conductive layer 254 can be formed over the top surface of the first S / D contact structure 234. For example, the first conductive layer 254 can contact the first sidewall, the second sidewall, and the bottom wall of the second S / D contact region 248 (e.g., corresponding to the top surface of the first S / D contact structure 234). A second conductive layer 256 can be formed over the first conductive layer 254. For example, the second conductive layer 256 can contact one or more surfaces of the first conductive layer 254 (e.g., the first (right) sidewall, the second (left) sidewall opposite the first sidewall (e.g., facing the first sidewall), and / or the top wall). A third conductive layer 258 can be formed over the second conductive layer 256. For example, the third conductive layer 258 can contact one or more surfaces of the second conductive layer 256 (e.g., the first (right) sidewall, the second (left) sidewall opposite the first sidewall (e.g., facing the first sidewall), and / or the top wall). A conductive fill layer 260 can be formed over the third conductive layer 258. For example, the conductive fill layer 260 can contact one or more surfaces of the third conductive layer 258 (e.g., the first (right) sidewall, the second (left) sidewall opposite the first sidewall (e.g., facing the first sidewall), and / or the top wall). The second S / D contact structure 252 can be formed by the same or similar techniques as described above for the first S / D contact structure 234, and the second S / D contact structure 252 can include the same or similar components as described above for the first S / D contact structure 234.

[0059] After forming the second S / D contact structure 252, the manufacturing steps associated with blocks 116, 118, and 120 can be repeated to form one or more additional conductive contact layers on the semiconductor device 200.

[0060] It should be understood that not all advantages may be discussed herein, that any particular advantage is not required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0061] Some embodiments of the present disclosure provide a method that includes: forming a gate electrode over a substrate; forming a ferroelectric layer over the gate electrode; forming a channel layer over the ferroelectric layer; forming a top cap layer over the channel layer, where the top cap layer includes one or more of the following: CeO x 、BeO x 、InO x 、GaO x 、AlO x 、SnO x, VO x , WO x , TiO x , ZrO x , NbO x , HfO x , SiO x , TaO x , a binary metal oxide based on any combination of the foregoing metal oxides, or a ternary metal oxide based on any combination of the foregoing metal oxides; after forming the top cover layer, annealing is performed at a temperature lower than 350 °C; a dielectric layer is formed on the top cover layer; and source and drain contact members are formed in the dielectric layer.

[0062] In an embodiment of the present disclosure, forming the source and drain contact members includes: patterning the dielectric layer; and forming the source and drain contact members in contact with the top cover layer.

[0063] In an embodiment of the present disclosure, forming the source and drain contact members includes: patterning the dielectric layer and the top cover layer; and forming the source and drain contact members in contact with the channel layer, where the channel layer includes one or more of the following: InGaZnO, InO, ITO, GaZnO, InGaAs, GaN, AlGaAs, Si, Ge, C, SiC, SiGe, SiGeC, Ga 2 O 3 , a II-VI group compound semiconductor, or a III-V group compound semiconductor.

[0064] In an embodiment of the present disclosure, forming the source and drain contact members includes: patterning the dielectric layer, the top cover layer, and the channel layer; and forming the source and drain contact members in contact with the ferroelectric layer.

[0065] In an embodiment of the present disclosure, forming the ferroelectric layer includes: forming a seed layer on the gate electrode, where the seed layer includes Ta 2 O 5 , ZrO 2 or HfO 2 one or more of; forming a memory layer on the seed layer, where the memory layer includes hafnium zirconium oxide or HfO 2 one or more of, the hafnium zirconium oxide or the HfO 2 doped with one or more of Ta, Al, Si, In, Zr, Sc, Y, Gd, La, Sr; and forming an intermediate layer on the memory layer, where the intermediate layer includes TiO 2 , Ta2 O 5 、 BaO, SrO, Y 2 O 3 、 HfO 2 、 ZrO 2 、 or HfSiO 2 or one or more of the above.

[0066] In an embodiment of the present disclosure, it further includes: annealing at a temperature below 350 °C after forming the ferroelectric layer and before forming the channel layer.

[0067] In an embodiment of the present disclosure, forming the source contact and the drain contact includes: forming a first conductive layer, where the first conductive layer includes one or more of TiN, TaN, or WN; forming a second conductive layer on the first conductive layer, where the second conductive layer includes one or more of Ti, Zr, Th, V, Pd, Cu, or W; forming a third conductive layer on the second conductive layer, where the third conductive layer includes one or more of TiN, TaN, or WN; and forming a conductive filling layer on the third conductive layer, where the conductive filling layer includes one or more of Ru, Al, Pt, Ag, Co, Fe, Sn, or Ni.

[0068] In an embodiment of the present disclosure, the dielectric layer includes AlO x 、 SiN x 、 TiC or TiO 2 or one or more of the above.

[0069] In an embodiment of the present disclosure, forming the capping layer includes one of the following methods: physical vapor deposition; plasma enhanced chemical vapor deposition; or plasma enhanced atomic layer deposition.

[0070] In an embodiment of the present disclosure, where the dielectric layer is a first dielectric layer, the source contact is a first source contact, and the drain contact is a first drain contact, the method further includes: forming a second dielectric layer on the first source contact and the first drain contact; and forming a second source contact and a second drain contact in the second dielectric layer.

[0071] Some embodiments of the present disclosure provide a ferroelectric random access memory (FeRAM) device including a transistor, the transistor including: a gate electrode; a ferroelectric layer located above the gate electrode; a channel layer located above the ferroelectric layer; a capping layer located above the channel layer, where the capping layer includes one or more of the following: CeOx, BeOx, InOx, GaO x 、 AlO x 、 SnO x 、 VO x, WO x , TiO x , ZrO x , NbO x , HfO x , SiO x , TaO x , A binary metal oxide based on any combination of the foregoing metal oxides, or a ternary metal oxide based on any combination of the foregoing metal oxides; a dielectric layer located above the top cover layer; and a source electrode and a drain electrode contacting one or more of the top cover layer, the channel layer, or the ferroelectric layer.

[0072] In an embodiment of the present disclosure, the source electrode and the drain electrode contact the top surface of the top cover layer.

[0073] In an embodiment of the present disclosure, the source electrode and the drain electrode contact the top surface of the channel layer, and the channel layer includes one or more of the following: InGaZnO, InO, ITO, GaZnO, InGaAs, GaN, AlGaAs, Si, Ge, C, SiC, SiGe, SiGeC, Ga 2 O 3 , a II-VI group compound semiconductor, or a III-V group compound semiconductor.

[0074] In an embodiment of the present disclosure, the source electrode and the drain electrode contact the top surface of the ferroelectric layer.

[0075] In an embodiment of the present disclosure, the ferroelectric layer includes: a seed layer located above the gate electrode, and the seed layer includes one or more of Ta 2 O 5 , ZrO 2 or HfO 2 ; a memory layer located above the seed layer, and the memory layer includes hafnium zirconium oxide or one or more of HfO 2 , and the hafnium zirconium oxide or the HfO 2 is doped with one or more of Ta, Al, Si, In, Zr, Sc, Y, Gd, La, Sr; and an intermediate layer located above the memory layer, and the intermediate layer includes one or more of TiO 2 , Ta 2 O 5 , BaO, SrO, Y 2 O 3 , HfO 2 , ZrO 2 , or HfSiO 2 .

[0076] Some embodiments of the present disclosure provide a method, the method comprising: forming a gate electrode over a substrate; forming a ferroelectric layer over the gate electrode, including: forming a seed layer over the gate electrode, forming a memory layer over the seed layer, and forming an interlayer over the memory layer; forming a channel layer over the interlayer; forming a cap layer over the channel layer; forming a dielectric layer over the cap layer; patterning the dielectric layer; and forming a source contact and a drain contact in the patterned dielectric layer, including: forming a first conductive layer, forming a second conductive layer over the first conductive layer, forming a third conductive layer over the second conductive layer, and forming a conductive fill layer over the third conductive layer.

[0077] In embodiments of the present disclosure, the seed layer comprises Ta 2 O 5 , ZrO 2 or HfO 2 or combinations thereof, the memory layer comprises hafnium zirconium oxide or HfO 2 or combinations thereof, the hafnium zirconium oxide or the HfO 2 is doped with one or more of Ta, Al, Si, In, Zr, Sc, Y, Gd, La, Sr, and the interlayer comprises TiO 2 , Ta 2 O 5 , BaO, SrO, Y 2 O 3 , HfO 2 , ZrO 2 , or HfSiO 2 or combinations thereof.

[0078] In embodiments of the present disclosure, the cap layer comprises one or more of the following: CeO x , BeO x , InO x , GaO x , AlO x , SnO x , VO x , WO x , TiO x , ZrO x , NbO x , HfO x , SiO x , TaO x , binary metal oxides based on any combination of the foregoing metal oxides, or ternary metal oxides based on any combination of the foregoing metal oxides.

[0079] In embodiments of the present disclosure, the first conductive layer includes one or more of TiN, TaN, or WN; the second conductive layer includes one or more of Ti, Zr, Th, V, Pd, Cu, or W; the third conductive layer includes one or more of TiN, TaN, or WN; and the conductive filling layer includes one or more of Ru, Al, Pt, Ag, Co, Fe, Sn, or Ni.

[0080] In embodiments of the present disclosure, further included is: after forming the top cover layer, annealing is performed at a temperature below 350 °C.

[0081] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A ferroelectric random access memory device, characterized in that: include: Transistors, including: Gate electrode; a ferroelectric layer, located on the gate electrode; A channel layer, located on the ferroelectric layer; A top cover layer, located above the channel layer; a dielectric layer located on the cap layer; and The source and the drain contact one or more of the cap layer, the channel layer or the ferroelectric layer.

2. The ferroelectric random access memory device according to claim 1, wherein: The source and the drain contact a top surface of the cap layer.

3. The ferroelectric random access memory device according to claim 1, wherein: The source and the drain are in contact with a top surface of the channel layer.

4. The ferroelectric random access memory device according to claim 1, wherein: The source and the drain contact a top surface of the ferroelectric layer.

5. The ferroelectric random access memory device according to claim 1, wherein: The ferroelectric layer comprises: A seed layer, located on the gate electrode; a memory layer located on the seed layer; and The interface layer is located on the memory layer.

6. The ferroelectric random access memory device according to claim 1, wherein: Further including: A first conductive layer, located on the top cover layer; a second conductive layer, located on the first conductive layer; a third conductive layer, located on the second conductive layer; as well as The conductive filling layer is located on the third conductive layer.

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