VDMOSFET device with low on-resistance

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device with lower on-resistance, which comprises a VDMOSFET structure formed by a plurality of MOS cells in parallel, the surface of the bottom layer of the VDMOSFET structure is in ohmic connection with a drain electrode, and the surface of the top layer of the VDMOSFET structure is in ohmic connection with a source electrode; a grid electrode is embedded between the semiconductor layer and the source electrode of the single MOS cell, and the height of the grid electrode accounts for 1 / 3 of the thickness of the VDMOSFET structure; the MOS cell comprises a sinking layer, a diffusion layer, a P-well layer and an N-well layer, and the N-well layer and the diffusion layer are separated through the P-well layer; the N well layer comprises a first lightly doped N well, a first heavily doped N well and a second heavily doped N well. According to the utility model, the longer grid electrode is embedded in the semiconductor, and the hardness of the grid electrode is uniform and relatively large, so that the problem of insufficient bonding strength of different well layers due to heat treatment can be solved when the MOS semiconductor is prepared, and the MOS device can adapt to higher temperature.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a VDMOSFET device with a lower on-resistance. Background Art

[0002] In semiconductor devices, the internal field plate structure usually refers to the structure of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). A MOSFET is a common semiconductor device used to control the flow of current. The internal field plate structure plays an important role in a MOSFET, affecting the performance and characteristics of the device.

[0003] The internal field plate structure in a MOSFET usually consists of the following parts: Gate, the gate is the control electrode of the MOSFET. By applying a voltage to the gate, the current flow between the source and the drain can be controlled. The gate is generally made of a metal material and covers an insulating layer. Insulating layer, the insulating layer is located between the gate and the semiconductor substrate, used to isolate the gate and the semiconductor substrate to prevent current leakage. The insulating layer is usually composed of materials such as silicon dioxide. Semiconductor substrate, the semiconductor substrate is the main part of the MOSFET, used to control the flow of current.

[0004] A prior patent discloses a VDMOS device with a body field plate structure (publication number CN107068758A). Each cell structure includes a metallized drain, an N+ substrate, an N- drift region, and a metallized source arranged in sequence from bottom to top; there is a groove-shaped field plate region in the N- drift region, and the groove-shaped field plate region includes a graded dielectric layer and a polysilicon field plate. P-type doped regions are respectively arranged on the left and right sides inside the N- drift region, and an N+ heavily doped source region is arranged above the P-type doped regions; a gate oxide layer is arranged on the upper surface of the N- drift region, and a gate electrode is arranged above the gate oxide layer. In the technology disclosed in this patent, since the preparation of MOS semiconductors necessarily goes through a heat treatment step, this will cause instability at the contact between the deposited oxide layer and the semiconductor when entering the high-temperature state; at the same time, it will also affect the response speed of the MOS semiconductor switch. Summary of the Invention

[0005] The main technical problem to be solved by the utility model is to provide a VDMOSFET device with a lower on-resistance, solving the problems in the above background art.

[0006] To solve the above technical problem, according to one aspect of the utility model, more specifically, a VDMOSFET device with a lower on-resistance includes a VDMOSFET structure composed of a plurality of MOS cells arranged in parallel. The bottom surface of the VDMOSFET structure is ohm-connected to a drain, and the top surface of the VDMOSFET structure is ohm-connected to a source;

[0007] A gate is embedded between the semiconductor layer and the source of a single MOS cell, and the height of the gate accounts for 1 / 3 of the thickness of the VDMOSFET structure.

[0008] The MOS cell includes a sinking layer, a diffusion layer, a P-well layer, and an N-well layer, where the N-well layer and the diffusion layer are separated by the P-well layer.

[0009] The N-well layer includes a lightly doped N-well 1, a heavily doped N-well 1, and a heavily doped N-well 2.

[0010] The P-well layer includes a lightly doped P-well 1, a heavily doped P-well 1, a heavily doped P-well 2, and a lightly doped P-well 2.

[0011] A doped N-well 3 is formed by ion implantation inside the diffusion layer, and the doped N-well 3 is in ohmic contact with the lightly doped P-well 2.

[0012] Furthermore, for the preparation of the substrate layer in a single MOS cell, ion implantation is used with less in the middle and more on both sides, and the sinking layer is in a shape with higher sides and lower middle.

[0013] Furthermore, when a voltage is applied to the gate, a depletion layer of the JFET region is formed inside its diffusion layer.

[0014] Furthermore, the thickness of the lightly doped P-well 2 is the same as that of the doped N-well 3.

[0015] Furthermore, an oxide layer is deposited on the surface of the gate. The oxide layer is composed of silicon dioxide, and the oxide layer is located between the gate and the semiconductor substrate to isolate the gate and the semiconductor substrate.

[0016] Furthermore, when the gate is connected to a gate voltage, the charges inside the lightly doped P-well 2 move closer to the oxide layer under the action of the gate electric field and form a charge channel.

[0017] Furthermore, the deposition thicknesses of the lightly doped N-well 1 and the heavily doped N-well 1 are the same, and both are located above the heavily doped N-well 2.

[0018] Furthermore, the top end of the lightly doped P-well 2 is embedded inside the heavily doped N-well 2.

[0019] Furthermore, the heavily doped P-well 2s between adjacent MOS cells are integrated, and the heavily doped P-well 2 is in ohmic contact with the source.

[0020] The beneficial effects of a VDMOSFET device with a lower on-resistance according to the present utility model are as follows:

[0021] 1. The utility model adopts a longer gate embedded inside the semiconductor. And due to the uniform and relatively large hardness of the gate, it can ensure that when the MOS semiconductor is prepared, the problem of insufficient bonding strength between different well layers caused by heat treatment can be compensated, so that the MOS device can adapt to higher temperatures.

[0022] 2. The utility model can increase the charge tolerance between the source and the drain by forming an N well through ion implantation in the diffusion layer, and can greatly reduce the on-resistance between them after forming a charge channel, thereby improving the switching response speed of the MOS semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following further describes the present utility model in detail with reference to the drawings and specific implementation methods.

[0024] Figure 1 It is a schematic diagram of a VDMOSFET device;

[0025] Figure 2 It is the present utility model Figure 1 A schematic diagram of a partial enlarged detail;

[0026] Figure 3 It is a schematic diagram of a dual-cell juxtaposed structure of the present utility model.

[0027] In the figure: 1. Drain; 2. Substrate layer; 3. Diffusion layer; 4. Source; 5. Oxide layer; 6. Gate; 7. Lightly doped N well 1; 8. Heavily doped N well 1; 9. Heavily doped N well 2; 10. Lightly doped P well 1; 11. Heavily doped P well 1; 12. Heavily doped P well 2; 13. Lightly doped P well 2; 14. Doped N well 3; 15. Charge channel; 16. JFET region. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The present utility model will be described in detail below with reference to the drawings and embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0029] As Figures 1-3 shown, according to one aspect of the present utility model, a VDMOSFET device with a lower on-resistance is provided, including a VDMOSFET structure composed of a plurality of MOS cells juxtaposed. The bottom surface of the VDMOSFET structure is ohm-connected to a drain 1, and the top surface of the VDMOSFET structure is ohm-connected to a source 4. A gate 6 is embedded between the semiconductor layer of a single MOS cell and the source 4, and the height of the gate 6 accounts for 1 / 3 of the thickness of the VDMOSFET structure (as Figure 1 shown). After the gate 6 is connected to a gate voltage, a path will be formed between the source 4 and the drain 1.

[0030] And the gate 6 adopts a longer design and is embedded inside the semiconductor. Since the hardness of the gate 6 is uniform and relatively large, this can ensure that when the MOS semiconductor is fabricated, the problem of insufficient bonding strength between different well layers due to heat treatment can be compensated, so that the MOS device can adapt to higher temperatures.

[0031] The MOS cell includes a substrate layer 2, a diffusion layer 3, a P-well layer, and an N-well layer. Among them, the N-well layer is separated from the diffusion layer 3 by the P-well layer. In this way, it can be ensured that when the gate 6 of the MOS semiconductor is not connected to a voltage, the P-well layer cuts off the connection between the N-well layer and the diffusion layer 3, so as to ensure that the source electrode 4 and the drain electrode 1 are in a blocked state.

[0032] The N-well layer includes a lightly doped N-well 7, a heavily doped N-well 8, and a heavily doped N-well 9; the P-well layer includes a lightly doped P-well 10, a heavily doped P-well 11, a heavily doped P-well 12, and a lightly doped P-well 13.

[0033] Among them, the doping concentrations of the heavily doped N-well 9 and the doped N-well 14 are both 5.3 - 6×10 18 mol / cm 3 ;

[0034] The doping concentration of the heavily doped N-well 8 is 7 - 9×10 18 mol / cm 3 ;

[0035] The doping concentration of the heavily doped P-well 11 is 4 - 6×10 18 mol / cm 3 ;

[0036] The doping concentration of the heavily doped P-well 12 is 2.1 - 3×10 18 mol / cm 3 .

[0037] In this embodiment, a doped N-well 14 is formed by ion implantation inside the diffusion layer 3, and the doped N-well 14 is in ohmic contact with the lightly doped P-well 13.

[0038] In this embodiment, the substrate layer 2 in a single MOS cell is fabricated by ion implantation with a small amount in the middle and a large amount on both sides. The substrate layer 2 has a shape that is high on both sides and low in the middle (as shown in Figure 1 ), and this shape design can not only improve the tolerance of the MOS semiconductor to the gate voltage, but also inhibit the diffusion of charges in the diffusion layer 3 to adjacent MOS cells.

[0039] In this embodiment, when a voltage is applied to the gate 6, a depletion layer of the JFET region 16 is formed inside its diffusion layer 3. By controlling the gate voltage, the conductivity of the JFET region 16 can be adjusted, so that the MOS semiconductor can meet different usage environments.

[0040] In this embodiment, the thickness of the lightly doped P-well II 13 is the same as that of the doped N-well III 14. An oxide layer 5 is deposited on the surface of the gate 6. The oxide layer 5 is composed of silicon dioxide, and the oxide layer 5 is located between the gate 6 and the semiconductor substrate to isolate the gate 6 and the semiconductor substrate. When the gate 6 is connected to the gate voltage, the charges inside the lightly doped P-well II 13 approach the oxide layer 5 under the action of the gate electric field and form a charge channel 15 (as Figure 3 shown). The doping concentration of the heavily doped N-well II 9 is the same as that of the doped N-well III 14. After the charge channel 15 is formed between the two, its on-resistance will also be minimized. And the doped N-well III 14 can absorb more charges in the diffusion layer 3, so as to improve the efficiency of the charges in the diffusion layer 3 flowing into the N-well layer.

[0041] The doping concentration of the heavily doped N-well I 8 is higher than that of the heavily doped N-well II 9, so as to ensure that the charges in the N-well layer mainly flow into the source 4 through the heavily doped N-well I 8.

[0042] In this embodiment, the deposition thicknesses of the lightly doped N-well I 7 and the heavily doped N-well I 8 are the same, and both are located above the heavily doped N-well II 9. The top of the lightly doped P-well II 13 is embedded inside the heavily doped N-well II 9. The heavily doped P-well II 12 between adjacent MOS cells is integrated, and the heavily doped P-well II 12 is in ohmic contact with the source 4. Among them, the lightly doped P-well I 10 can suppress the parasitic phenomenon of the charges in the P-well layer and reduce the attraction of the gate voltage to the charges in other regions of the P-well layer.

[0043] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by those of ordinary skill in the art within the scope of the essence of the present invention also belong to the protection scope of the present invention.

Claims

1. A VDMOSFET device with lower on-resistance, characterized in that: It comprises a VDMOSFET structure composed of a plurality of MOS cells arranged in parallel, wherein the bottom surface of the VDMOSFET structure is ohmically connected to a drain electrode (1), and the top surface of the VDMOSFET structure is ohmically connected to a source electrode (4); A gate (6) is embedded between the semiconductor layer and the source (4) of a single MOS cell, and the height of the gate (6) accounts for 1 / 3 of the thickness of the VDMOSFET structure; The MOS cell comprises a substrate layer (2), a diffusion layer (3), a P-well layer and an N-well layer, wherein the N-well layer and the diffusion layer (3) are separated by the P-well layer; The N-well layer includes a lightly doped N-well 1 (7), a heavily doped N-well 1 (8) and a heavily doped N-well 2 (9); The P-well layer includes a lightly doped P-well 1 (10), a heavily doped P-well 1 (11), a heavily doped P-well 2 (12) and a lightly doped P-well 2 (13); The diffusion layer (3) is internally ion-implanted to form a doped N-well three (14), and the doped N-well three (14) is in ohmic contact with the lightly doped P-well two (13).

2. The VDMOSFET device with lower on-resistance according to claim 1, characterized in that: The substrate layer (2) in a single MOS cell is prepared by ion implantation with a small amount in the middle and a large amount on both sides, and the substrate layer (2) is in a shape with high sides and a low middle.

3. The VDMOSFET device with lower on-resistance according to claim 1, characterized in that: When a voltage is applied to the gate (6), a depletion layer of the JFET region (16) is formed inside the diffusion layer (3).

4. The VDMOSFET device with lower on-resistance according to claim 1, characterized in that: The thickness of the lightly doped P-well 2 (13) is consistent with the thickness of the doped N-well 3 (14).

5. The VDMOSFET device with lower on-resistance according to claim 4, characterized in that: An oxide layer (5) is deposited on the surface of the gate (6), the oxide layer (5) is made of silicon dioxide, and the oxide layer (5) is located between the gate (6) and the semiconductor substrate for isolating the gate (6) from the semiconductor substrate.

6. The VDMOSFET device with lower on-resistance according to claim 5, characterized in that: When the gate (6) is connected to a gate voltage state, the charges inside the lightly doped P well 2 (13) move toward the oxide layer (5) under the action of the gate electric field and form a charge channel (15).

7. The VDMOSFET device with lower on-resistance according to claim 1, characterized in that: The deposition thickness of the lightly doped N-well 1 (7) and the heavily doped N-well 1 (8) are consistent, and both are located above the heavily doped N-well 2 (9).

8. The VDMOSFET device with lower on-resistance according to claim 1, characterized in that: The top of the lightly doped P well 2 (13) is embedded in the interior of the heavily doped N well 2 (9).

9. The VDMOSFET device with lower on-resistance according to claim 1, characterized in that: The heavily doped P wells 2 (12) between adjacent MOS cells are integrated, and the heavily doped P wells 2 (12) are in ohmic contact with the source electrode (4).

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