Power transistor
By designing multiple annular trenches and conductive layers in the power transistor and using the first and second gate conductors as field plates, the problem of how to maintain or increase the breakdown voltage when the component size is reduced is solved, and a higher breakdown voltage and a smaller layout area are achieved.
Patent Information
- Application Number
- CN202421877711.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-24
- Filing Date
- 2024-08-05
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-08-05
AI Technical Summary
With the improvement of integration and size of power transistors, how to maintain or increase the original breakdown voltage while the component size is reduced has become an important issue.
A power transistor is designed, including a substrate, a gate structure, annular trench, a conductive layer, an insulating layer, a doped region, a source conductor, a first gate conductor, and a second gate conductor. By providing a plurality of annular trenches and conductive layers, and using the first and second gate conductors as field plates, extending to the terminal area to increase the breakdown voltage.
It realizes that the breakdown voltage is maintained or increased when the component size is reduced, the layout area is reduced, and the performance of power transistors is effectively improved.
Smart Images
Figure CN222928731U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor component, in particular to a power transistor. Background Art
[0002] In current semiconductor technologies, power transistors are mainly applied to switching components, such as providing power switch switching in a power management device. Generally speaking, in a power transistor, in order to maintain the breakdown voltage of the terminals around the component, a plurality of floating trench-type conductive rings can be arranged in the terminal region. However, with the continuous improvement of the integration degree of power transistors, the size of power transistors has also been reduced accordingly. Therefore, how to maintain (or even improve) the original breakdown voltage under the condition of reducing the component size has become an important issue. Summary of the Utility Model
[0003] The utility model provides a power transistor, which can have a smaller layout area.
[0004] The power transistor of the utility model comprises a substrate, a gate structure, a plurality of annular trenches, a conductive layer, an insulating layer, a first doping region, a source conductor, a first gate conductor, a second gate conductor and a drain. The substrate has an active region and a terminal region surrounding the active region, and comprises a first surface and a second surface opposite to each other, wherein the substrate has a first conductivity type. The gate structure is arranged in the substrate in the active region and extends in a first direction. The plurality of annular trenches are sequentially arranged in the substrate in the terminal region in a direction outward from the active region and surround the active region. The conductive layer is arranged in the plurality of annular trenches. The insulating layer is arranged between the gate structure and the substrate and between the conductive layer and the substrate. The first doping region is arranged in the substrate in the terminal region and is located between adjacent annular trenches and between the annular trenches and the gate structure, wherein the first doping region has a second conductivity type opposite to the first conductivity type. The source conductor is arranged on the first surface, extends in a second direction intersecting with the first direction, and is electrically connected to the gate structure. The first gate conductor and the second gate conductor are arranged on the first surface, extend in the second direction, are respectively located on opposite sides of the source conductor in the first direction, and are electrically connected to the gate structure. The drain is arranged at the second surface.
[0005] In an embodiment of the power transistor of the present utility model, the gate structure includes a first gate, a second gate and an inter-gate insulating layer. The first gate and the second gate are disposed in the substrate in the active region, wherein the first gate extends in a first direction, and the second gate surrounds the side and bottom surfaces of the first gate. The inter-gate insulating layer is disposed between the first gate and the second gate. The first gate is electrically connected to the first gate conductor and the second gate conductor, and the second gate is electrically connected to the source conductor.
[0006] In an embodiment of the power transistor of the present utility model, the bottom surface of the first doped region is higher than the bottom of the annular trench.
[0007] In an embodiment of the power transistor of the present utility model, it further includes a second doped region, which is disposed in the substrate below the annular trench and in the substrate below the gate structure and adjacent to the boundary between the active region and the terminal region, wherein the second doped region has the second conductivity type.
[0008] In an embodiment of the power transistor of the present utility model, the second doped region contacts the bottom of the annular trench and the bottom of the gate structure, and is electrically separated from the gate structure.
[0009] In an embodiment of the power transistor of the present utility model, the second doped region is separated from the bottom of the annular trench and the bottom of the gate structure.
[0010] In an embodiment of the power transistor of the present utility model, the potential of the conductive layer in the annular trench is floating.
[0011] In an embodiment of the power transistor of the present utility model, the substrate includes an epitaxial layer adjacent to the first surface and a silicon layer adjacent to the second surface, wherein the gate structure and the annular trench are located in the epitaxial layer.
[0012] In an embodiment of the power transistor of the present utility model, the drain includes a doped region having the first conductivity type.
[0013] In an embodiment of the power transistor of the present utility model, the first gate conductor and the second gate conductor serve as a field plate.
[0014] Based on the above, in the power transistor of the present utility model, the first gate conductor and the second gate conductor are respectively disposed on opposite sides of the source conductor. Therefore, the power transistor of the present utility model only includes one source conductor as a shared source, thus effectively reducing the layout area. In addition, the first gate conductor and the second gate conductor extend into the terminal region, so the first gate conductor and the second gate conductor can serve as field plates. In this way, the depletion region formed during the operation of the power transistor of the present utility model can extend to the outermost floating conductive trench to increase the breakdown voltage of the power transistor.
[0015] To make the above features and advantages of the present utility model more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings
[0016] Figure 1A is a top view schematic diagram of a power transistor according to a first embodiment of the present utility model;
[0017] Figure 1B is along Figure 1A the I-I cross-section line in
[0018] Figure 2 is a cross-sectional schematic diagram of a power transistor according to a second embodiment of the present utility model;
[0019] Figure 3 is a cross-sectional schematic diagram of a power transistor according to a third embodiment of the present utility model. Detailed Description of the Embodiments
[0020] Specific embodiments are listed below and described in detail in conjunction with the accompanying drawings, but the provided embodiments are not intended to limit the scope covered by the present utility model. In addition, the accompanying drawings are for illustrative purposes only and are not drawn to the original size. For the convenience of understanding, the same components will be labeled with the same symbols in the following description.
[0021] Regarding the terms "comprising", "including", "having", etc. used in the text, they are all open-ended terms, that is, "including but not limited to".
[0022] When using terms such as "first", "second", etc. to describe components, they are only used to distinguish these components from each other and do not limit the order or importance of these components. Therefore, in some cases, the first component can also be called the second component, and the second component can also be called the first component, and this does not deviate from the scope of the present utility model.
[0023] Figure 1A is a top view schematic diagram of a power transistor according to a first embodiment of the present utility model. Figure 1B is alongFigure 1A Schematic cross-sectional view of the I-I cutting line in Figure 1A , for clarity of illustration and ease of explanation, only some components are shown.
[0024] Please also refer to Figure 1A and Figure 1B , the power transistor 10 of this embodiment includes a substrate 100, a gate structure GS, a plurality of annular trenches TR, a conductive layer 102, an insulating layer IL2, a first doped region 106, a source conductor 108, a first gate conductor 110, a second gate conductor 112, and a drain D.
[0025] The substrate 100 has an active region AA and a terminal region TE surrounding the active region AA. Generally, the active region AA may be located at the center of the power transistor 10, which is a region for forming the gate structure, while the terminal region TE is located at the edge of the power transistor 10 to surround the active region AA. In addition, the substrate 100 has a first surface S1 and a second surface S2 opposite to each other. In this embodiment, the first surface S1 can be regarded as the front surface of the substrate 100, and the second surface S2 can be regarded as the back surface of the substrate 100.
[0026] In addition, in this embodiment, the substrate 100 includes a silicon layer 100a and an epitaxial layer 100b, but the present invention is not limited thereto. Specifically, in this embodiment, the substrate 100 has a first conductivity type, which includes a first conductivity type silicon layer 100a and a first conductivity type epitaxial layer 100b disposed on the silicon layer 100a, such that the silicon layer 100a is adjacent to the second surface S2, and the epitaxial layer 100b is adjacent to the first surface S1. The doping concentration of the first conductivity type dopant in the silicon layer 100a can be greater than the doping concentration of the first conductivity type dopant in the epitaxial layer 100b. The first conductivity type can be one of N-type and P-type, and the second conductivity type opposite to the first conductivity type is the other of N-type and P-type.
[0027] The drain D is disposed at the second surface S2 of the substrate 100. In this embodiment, the drain D can be a doped region of the first conductivity type disposed in the silicon layer 100a and adjacent to the second surface S2, but the present invention is not limited thereto. In other embodiments, the drain D can be a conductive layer disposed on the second surface S2.
[0028] The gate structure GS is disposed in the epitaxial layer 100b of the substrate 100 in the active region AA and extends in the first direction DR1. Specifically, in the present embodiment, the gate structure GS includes a plurality of first gates G1 extending in the first direction DR1, a second gate G2 surrounding these first gates G1 around and at the bottom, a gate insulating layer GI disposed between the first gate G1 and the second gate G2, and an insulating layer IL1 disposed between the second gate G2 and the epitaxial layer 100b of the substrate 100. In the present embodiment, the insulating layer IL1 may be located at the boundary BD between the active region AA and the terminal region TE, but the present invention is not limited thereto. In other embodiments, the insulating layer IL1 may be spaced apart from the boundary BD between the active region AA and the terminal region TE by a certain distance.
[0029] As Figure 1A shown, when viewed from the top direction above the substrate 100, each first gate G1 extends in the first direction DR1, and the annular second gate G2 surrounds all the first gates G1. In addition, as Figure 1B shown, the second gate G2 is below these first gates G1 and extends in the planar direction of the substrate 100. In this way, the second gate G2 surrounds the side and bottom surfaces of the first gate G1 in the epitaxial layer 100b, and the first gate G1 and the second gate G2 are separated by the gate insulating layer GI. That is to say, in the present embodiment, the gate structure GS is a split-gate type gate structure well-known in the art. In the present embodiment, the gate insulating layer GI may be a silicon oxide layer, and the insulating layer IL1 may also be a silicon oxide layer, but the present invention is not limited thereto. In addition, in other embodiments, the gate structure GS may be a split-gate type gate structure with other architectures, and the present invention does not limit this.
[0030] A plurality of annular trenches TR are sequentially disposed in the epitaxial layer 100b of the substrate 100 in the terminal region TE in the direction outward from the active region AA and surround the active region AA. Specifically, in the present embodiment, the plurality of annular trenches TR are disposed in the terminal region TE in a manner similar to concentric circles and surround the gate structure GS in the active region AA. In addition, the innermost annular trench TR is spaced apart from the insulating layer IL1 in the gate structure GS by a certain distance. That is to say, the annular trenches TR are only disposed in the terminal region TE, and there are no annular trenches TR in the active region AA.
[0031] The conductive layer 102 is disposed in each of the annular trenches TR, and the insulating layer IL2 is disposed between the conductive layer 102 and the epitaxial layer 100b of the substrate 100. That is, the conductive layer 102 in the annular trench TR is separated from the epitaxial layer 100b of the substrate 100 by the insulating layer IL2. In this way, the conductive trench CTR in the present embodiment is formed. In other words, in the present embodiment, a plurality of annular conductive trenches CTR are sequentially disposed in the epitaxial layer 100b of the substrate 100 in the terminal region TE in the direction outward from the active region AA to surround the active region AA, and each conductive trench CTR is composed of the conductive layer 102 and the insulating layer IL2 surrounding the conductive layer 102. In the present embodiment, the insulating layer IL2 may be a silicon oxide layer, but the present invention is not limited thereto.
[0032] The first doped region 106 of the second conductivity type is disposed in the epitaxial layer 100b of the substrate 100 in the terminal region TE, and is located between adjacent annular trenches TR and between the innermost annular trench TR and the insulating layer IL1 of the gate structure GS. The bottom surface of the first doped region 106 is higher than the bottom of the annular trench TR. In this way, in the present embodiment, adjacent conductive trenches CTR are spaced apart from each other by the first doped region 106, and the innermost conductive trench CTR is spaced apart from the gate structure GS by the first doped region 106, so that the potential of the conductive trench CTR disposed in the epitaxial layer 100b of the substrate 100 in the terminal region TE is floating.
[0033] In addition, in the present embodiment, the insulating layer IL3 may be disposed on the first surface S1 of the substrate 100 to cover the gate structure GS, the first doped region 106, and the conductive trench CTR. The source conductor 108 is disposed on the insulating layer IL3 and extends in a second direction DR2 that intersects the first direction DR1. The material of the source conductor 108 may be a metal. The source conductor 108 may be electrically connected to the second gate G2 of the gate structure GS through a contact (not shown in the figure) disposed in the insulating layer IL3.
[0034] The first gate conductor 110 and the second gate conductor 112 are disposed on the insulating layer IL3 and extend in the second direction DR2, and are respectively located on opposite sides of the source conductor 108 in the first direction DR1. The materials of the first gate conductor 110 and the second gate conductor 112 may be metals. A plurality of contacts CT are disposed in the insulating layer IL3, so that the first gate conductor 110 and the second gate conductor 112 can be respectively electrically connected to the first gate G1 of the gate structure GS through the contacts CT disposed in the insulating layer IL3. In the present embodiment, the first gate conductor 110 and the second gate conductor 112 may extend to the terminal region TE and be located above a part of the conductive trenches CTR.
[0035] In the power transistor 10, asFigure 1A As shown, the source conductor 108, the first gate conductor 110, and the second gate conductor 112 extend in the second direction DR2, and the first gate conductor 110 and the second gate conductor 112 are respectively located on opposite sides of the source conductor 108 in the first direction DR1. That is, in the power transistor 10, only one source conductor 108 needs to be provided as a shared source, so the layout area of the power transistor 10 can be effectively reduced.
[0036] In addition, in the power transistor 10, the first gate conductor 110 and the second gate conductor 112 extend into the terminal region TE. In this way, the first gate conductor 110 and the second gate conductor 112 can act as field plates, and as Figure 1B shown, the depletion region DP formed during the operation of the power transistor 10 can extend to the outermost floating conductive trench CTR to increase the breakdown voltage of the power transistor 10.
[0037] Figure 2 is a cross-sectional schematic view of a power transistor according to the second embodiment of the present invention. In this embodiment, components identical to those in the first embodiment will be denoted by the same reference numerals and will not be described again.
[0038] Please refer to Figure 2 , the difference between the power transistor 20 of this embodiment and the power transistor 10 is that: in this embodiment, the second doping region 114 of the second conductivity type is provided in the epitaxial silicon layer 100b of the substrate 100 under the annular trench TR, and in the epitaxial silicon layer 100b under the second gate G2 of the gate structure GS and adjacent to the boundary BD between the active region AA and the terminal region TE. In addition, the second doping region 114 contacts the bottom of the annular trench TR and the bottom of the insulating layer IL1 of the gate structure GS.
[0039] In the power transistor 20, due to the provision of the second doping region 114 of the second conductivity type, the electric field at the bottom of the annular trench TR can be effectively reduced, thereby increasing the breakdown voltage withstand.
[0040] Figure 3 is a cross-sectional schematic view of a power transistor according to the third embodiment of the present invention. In this embodiment, components identical to those in the second embodiment will be denoted by the same reference numerals and will not be described again.
[0041] Please refer to Figure 3, the difference between the power transistor 30 of this embodiment and the power transistor 20 lies in that: in this embodiment, the second doping region 114 of the second conductivity type is separated from the bottom of the annular trench TR by the bottom of the insulating layer IL1 of the gate structure GS. That is to say, the second doping region 114 is located between the bottom of the annular trench TR and the silicon layer 100a and does not contact the bottom of the annular trench TR.
[0042] In the power transistor 30, since there is a second doping region 114 of the second conductivity type, the electric field at the bottom of the annular trench TR can be effectively reduced, thereby improving the breakdown voltage. In addition, since the second doping region 114 is located between the bottom of the annular trench TR and the silicon layer 100a and does not contact the bottom of the annular trench TR, the electric field at the bottom of the annular trench TR can be further effectively reduced, thereby improving the breakdown voltage.
[0043] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A power transistor, characterized in that: include: A substrate having an active region and a terminal region surrounding the active region, and comprising a first surface and a second surface opposite to each other, wherein the substrate has a first conductivity type; a gate structure disposed in the substrate in the active region and extending in a first direction; A plurality of annular grooves are sequentially disposed in the substrate in the terminal region in a direction outward from the active region and surround the active region; A conductive layer is disposed in the plurality of annular grooves; an insulating layer, disposed between the gate structure and the substrate and between the conductive layer and the substrate; A first doped region, disposed in the substrate of the terminal region and located between adjacent annular trenches and between the annular trenches and the gate structure, wherein the first doped region has a second conductivity type opposite to the first conductivity type; A source conductor, disposed on the first surface, extending in a second direction intersecting with the first direction, and electrically connected to the gate structure; A first gate conductor and a second gate conductor are disposed on the first surface, extend in the second direction, are respectively located on opposite sides of the source conductor in the first direction, and are electrically connected to the gate structure; and The drain is arranged on the second surface.
2. The power transistor according to claim 1, characterized in that: The gate structure comprises: A first gate and a second gate are disposed in the substrate in the active region, wherein the first gate extends in a first direction, and the second gate surrounds a side surface and a bottom surface of the first gate; and an inter-gate insulating layer, disposed between the first gate and the second gate, The first gate is electrically connected to the first gate conductor and the second gate conductor, and the second gate is electrically connected to the source conductor.
3. The power transistor according to claim 1, characterized in that: The bottom surface of the first doping region is higher than the bottom of the annular trench.
4. The power transistor according to claim 1, characterized in that: It also includes a second doped region, which is arranged in the substrate below the annular trench and in the substrate below the gate structure and adjacent to the boundary between the active region and the terminal region, wherein the second doped region has the second conductivity type.
5. The power transistor according to claim 4, characterized in that: The second doping region contacts the bottom of the annular trench and the bottom of the gate structure, and is electrically separated from the gate structure.
6. The power transistor according to claim 4, characterized in that: The second doping region is separated from the bottom of the annular trench and the bottom of the gate structure.
7. The power transistor according to claim 1, characterized in that: The potential of the conductive layer in the annular trench is floating.
8. The power transistor according to claim 1, characterized in that: The substrate includes an epitaxial layer adjacent to the first surface and a silicon layer adjacent to the second surface, wherein the gate structure and the annular trench are located in the epitaxial layer.
9. The power transistor according to claim 1, characterized in that: The drain includes a doped region having the first conductivity type.
10. The power transistor according to claim 1, characterized in that: The first gate conductor and the second gate conductor serve as field plates.