MOS field effect transistor
By designing multiple spaced isolation trenches and non-linear channels in the MOS field effect transistor, the leakage current and local overheating problems caused by straight lines in the traditional electron migration path are solved, and a more uniform current distribution and higher device reliability and life are achieved.
Patent Information
- Application Number
- CN202421673541.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-15
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-07-15
AI Technical Summary
In the prior art, electron migration paths are usually straight lines, which may lead to increased leakage current and local overheating, affecting the overall performance and life of the device.
A MOS field effect transistor is designed, including a plurality of isolation trenches arranged spaced apart, each isolation trenches are formed on both sides of each isolation trenches, and a plurality of inner convex areas are provided on the side wall surface of the isolation trenches to optimize electric field distribution and heat dissipation.
Through the design of multiple isolation trenches and non-linear channels, the uniform distribution of current in multiple channels is achieved, which reduces the problems of local overheating and excessive current density, and improves the reliability and life of the device.
Smart Images
Figure CN222928732U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular, to a MOS field-effect transistor. Background Art
[0002] With the continuous development of semiconductor devices, the requirements for their performance and reliability are also getting higher and higher. In semiconductor devices, the electron migration path directly affects the efficiency and stability of the device. The traditional electron migration path is usually a straight line, which can achieve the basic current transmission function. However, in some high-performance applications, such a path design may have certain limitations.
[0003] For example, in the related art, isolation trenches are formed in the epitaxial layer, isolation gate electrodes are formed in the isolation trenches. After the potential of the isolation gate electrodes changes, the epitaxial layers on both sides of the isolation trenches are inverted into channels for electrons to pass through. This channel is the electron migration path, which is usually a straight line.
[0004] And this electron migration path is a straight line, and the electric field may be concentrated in some regions of this path, resulting in too high electric field intensity in these regions, thereby causing local overheating phenomena, and further affecting the overall performance and lifespan of the device. Summary of the Utility Model
[0005] This application aims to at least solve the technical problems in the prior art that the electron migration path is usually a straight line, which may lead to increased leakage current, local overheating, etc., thus affecting the overall performance and lifespan of the device. For this purpose, this application proposes a MOS field-effect transistor.
[0006] This application provides a MOS field-effect transistor, including:
[0007] A drain substrate, an epitaxial layer is formed on the drain substrate, a plurality of spaced-apart isolation trenches are formed in the epitaxial layer, multiple partial regions of the sidewall surfaces of the isolation trenches respectively protrude into the isolation trenches, and an isolation gate electrode is formed in the isolation trenches;
[0008] An active layer, the active layer is formed in the epitaxial layer, and the active layer includes channels located on both sides of each isolation trench;
[0009] A source layer, the source layer is formed on the active layer.
[0010] According to an embodiment of this application, the sidewall surface of the isolation trench has a first region and a second region, the first region protrudes into the isolation trench, and the second region protrudes in a direction away from the inside of the isolation trench.
[0011] According to an embodiment of this application, the first region and the second region are spaced apart.
[0012] According to an embodiment of the present application, there are multiple of the first regions and the second regions, and the first regions are disposed between two adjacent second regions.
[0013] According to an embodiment of the present application, it further includes an inner dielectric layer;
[0014] The inner dielectric layer is formed on a side of the isolation gate electrode facing away from the drain substrate, so that the isolation gate electrode is an embedded structure.
[0015] According to an embodiment of the present application, the source layer further covers the inner dielectric layer, and a side of the inner dielectric layer facing the source layer is recessed toward the isolation gate electrode.
[0016] According to an embodiment of the present application, a first oxide layer is formed at the bottom of the isolation trench, and the first oxide layer is used to isolate the isolation gate electrode and the epitaxial layer.
[0017] According to an embodiment of the present application, a second oxide layer is formed on the first oxide layer, and the second oxide layer adheres to a side wall surface of the isolation trench, and a thickness of the second oxide layer is less than that of the first oxide layer.
[0018] According to an embodiment of the present application, a receiving groove is formed in a middle portion of the first oxide layer, and the second oxide layer is formed on a wall surface of the receiving groove.
[0019] According to an embodiment of the present application, both the first oxide layer and the second oxide layer are silicon dioxide layers.
[0020] In summary, the present application includes at least one of the following beneficial technical effects: the number of isolation trenches is multiple, and the multiple isolation trenches are spaced apart, and the channels are on both sides of each isolation trench, which can make the current distributed in multiple channels, effectively avoiding problems such as local overheating or too high current density caused by excessive current concentration in a single channel; multiple partial regions on the side wall surface of the isolation trench respectively protrude into the isolation trench, and the channels are on both sides of each isolation trench, and the channels are not linear. On the one hand, this can effectively change the electric field distribution, making the electric field more evenly distributed in the channel region. This uniform electric field distribution helps to reduce the enhancement effect of the local electric field, thereby reducing the risk of local overheating; on the other hand, it can increase the surface area of the electron flowing through the channel, which helps to dissipate heat. When electrons move on a longer migration path, the heat generated by them can be more effectively diffused, reducing the risk of local overheating. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is one of the structural schematic diagrams of the MOS field effect transistor provided by the embodiment of the present application;
[0022] Figure 2 It is the second structural schematic diagram of the MOS field effect transistor provided by the embodiment of the present application;
[0023] Figure 3 It is the third structural schematic diagram of the MOS field effect transistor provided by the embodiment of the present application;
[0024] Reference numerals:
[0025] 100, drain substrate; 110, epitaxial layer; 120, isolation trench; 130, isolation gate electrode; 121, first region; 122, second region; 200, active layer; 300, source layer; 400, inner dielectric layer; 510, first oxide layer; 520, second oxide layer; a, channel. Detailed implementation manners
[0026] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.
[0027] Reference is made below to Figures 1 - 3 Describe a MOS field effect transistor according to an embodiment of the present application.
[0028] As Figure 1 shown, the MOS field effect transistor includes: a drain substrate 100, an active layer 200, and a source layer 300.
[0029] The drain substrate 100 is used to receive carriers output downward by the active layer 200.
[0030] For example, the MOS field effect transistor can be an N-MOS transistor, the drain substrate 100 is N-type, and the carriers are negatively charged electrons; the MOS field effect transistor can also be a P-MOS transistor, the drain substrate 100 can be P-type, and the carriers are positively charged holes. This embodiment does not limit this.
[0031] As Figure 2 and Figure 3 shown, an epitaxial layer 110 is formed on the drain substrate 100. A plurality of spaced-apart isolation trenches 120 are formed in the epitaxial layer 110. A plurality of partial regions on the side wall surface of the isolation trench 120 respectively protrude toward the inside of the isolation trench 120, and an isolation gate electrode 130 is formed in the isolation trench 120.
[0032] In actual implementation, the isolation gate electrode 130 is specifically conductive, and its material can be polycrystalline conductive silicon or other conductive semiconductor materials, and has the same or similar thermal expansion adaptability as the drain substrate 100.
[0033] Of course, in other examples, other conductive materials used in semiconductor processes can also be adopted, such as tungsten, copper, and aluminum, and tungsten is commonly used.
[0034] As Figure 1 shown, the active layer 200 is formed in the epitaxial layer 110, and the active layer 200 includes channels a on both sides of each isolation trench 120, and the source layer 300 is formed on the active layer 200.
[0035] In the related art, the channels a on both sides of the isolation trench 120 are usually straight, and the design of the straight channels a easily causes the current density in some areas to be too large, thus causing local overheating.
[0036] In the above embodiments of the present application, since multiple partial regions of the side wall surface of the isolation trench 120 protrude into the isolation trench 120 respectively, and the channels a are located on both sides of each isolation trench 120, the channels a are not straight.
[0037] In this way, on the one hand, the electric field distribution can be effectively changed, so that the electric field is more evenly distributed in the channel a region. This uniform electric field distribution helps to reduce the enhancement effect of the local electric field, thereby reducing the risk of local overheating; on the other hand, it can increase the surface area of the electron flowing through the channel a, which helps to dissipate heat. When electrons move on a longer migration path, the heat generated by them can be more effectively diffused, reducing the risk of local overheating.
[0038] It should be noted that the number of the isolation trenches 120 is multiple, the multiple isolation trenches 120 are arranged at intervals, and the channels a are located on both sides of each isolation trench 120.
[0039] Such a design can increase the number of channels a formed. By forming channels a on both sides of each isolation trench 120, the current can be distributed in multiple channels a, thereby achieving a more uniform current distribution. This can effectively avoid the problems of local overheating or too high current density caused by the over-concentration of current in a single channel a, and improve the reliability and lifespan of the device.
[0040] In summary, the number of isolation trenches 120 is multiple, and the multiple isolation trenches 120 are arranged at intervals. The channel a is located on both sides of each isolation trench 120, which can distribute the current in the multiple channels a. This can effectively avoid the problems of local overheating or too high current density caused by excessive current concentration in a single channel a. Multiple partial regions of the side wall surface of the isolation trench 120 protrude inwardly into the isolation trench 120, and the channel a is located on both sides of each isolation trench 120. The channel a is not straight. On the one hand, this can effectively change the electric field distribution, making the electric field more evenly distributed in the channel a region. This uniform electric field distribution helps to reduce the enhancement effect of the local electric field, thereby reducing the risk of local overheating. On the other hand, it can increase the surface area of the electron flowing through the channel a, which helps to dissipate heat. When the electrons move on a longer migration path, the heat generated by them can be more effectively diffused, reducing the risk of local overheating.
[0041] As Figure 1 and Figure 2 shown, in some embodiments, the side wall surface of the isolation trench 120 has a first region 121 and a second region 122. The first region 121 protrudes inwardly into the isolation trench 120, and the second region 122 protrudes in a direction away from the inside of the isolation trench 120.
[0042] In this embodiment, the first region 121 protruding inwardly into the isolation trench 120 can have a homogenizing effect on the electric field.
[0043] The protruding first region 121 can expand the distribution of the electric field lines, reducing the excessive concentration of the electric field lines in a certain narrow region, thereby reducing the enhancement effect of the local electric field.
[0044] It should be noted that local overheating is usually caused by the excessive concentration of the electric field. Therefore, by increasing the uniformity of the electric field distribution, the peak value of the local temperature can be effectively reduced, and the heat accumulation caused by the electric field enhancement effect can be reduced.
[0045] The second region 122 protruding in a direction away from the isolation trench 120 can further optimize the electric field distribution.
[0046] This design reduces the concentration effect of the electric field in a specific region by increasing the path length and complexity of the electric field distribution.
[0047] By optimizing the electric field distribution, the problem of too high current density can be reduced. In the case where there is no protruding second region 122, the current may concentrate in some narrow regions, resulting in too high current density in these regions and causing local overheating. By increasing the electric field distribution path and surface area, the current can be evenly distributed in a larger region, reducing the risk of too high current density.
[0048] Meanwhile, the combined design of the first region 121 and the second region 122 increases the surface area through which electrons flow in the channel a. When electrons move along a longer migration path, the heat generated can be more effectively dissipated, reducing the risk of local overheating.
[0049] As Figure 1 and Figure 2 shown, in some embodiments, the first region 121 and the second region 122 are spaced apart.
[0050] In this embodiment, by spacing apart the first region 121 and the second region 122, the electric field distribution can be made more uniform. The spaced design allows the electric fields in different regions to compensate for each other, avoiding excessive concentration of the local electric field and thus reducing the risk of voltage breakdown caused by the electric field tip effect.
[0051] In some embodiments, there are multiple first regions 121 and multiple second regions 122, and the first regions 121 are disposed between two adjacent second regions 122.
[0052] In this embodiment, by arranging multiple first regions 121 between two adjacent second regions 122, the distribution of the electric field can be made more refined and uniform. This alternating design helps to reduce the concentration effect of the electric field, making the electric field in the entire channel a region more uniform and reducing the risk of voltage breakdown.
[0053] As Figure 1 and Figure 2 shown, in some embodiments, the MOS field effect transistor further includes an inner dielectric layer 400.
[0054] The inner dielectric layer 400 is formed on the side of the isolation gate electrode 130 facing away from the drain substrate 100, so that the isolation gate electrode 130 is an embedded structure.
[0055] In this embodiment, the inner dielectric layer 400 can effectively control and shield the electric field around the isolation gate electrode 130. This design can prevent electric field leakage, thereby improving the control accuracy of the electric field and ensuring the stability and reliability of the device.
[0056] In some embodiments, the source layer 300 also covers the inner dielectric layer 400, and the side of the inner dielectric layer 400 facing the source layer 300 is recessed toward the isolation gate electrode 130.
[0057] In this embodiment, the recessed inner dielectric layer 400 structure increases the heat conduction path, contributing to more effective heat dissipation. By extending the heat diffusion path, local overheating can be reduced, improving the reliability of the device under high power conditions.
[0058] Meanwhile, the covering structure of the inner dielectric layer 400 and the source layer 300 enhances the mechanical stability of the overall structure. The recessed structure can provide more buffer space during thermal expansion and contraction, reducing physical deformation caused by stress.
[0059] As Figure 1 and Figure 2 shown, in some embodiments, a first oxide layer 510 is formed at the bottom of the isolation trench 120, and the first oxide layer 510 is used to isolate the isolation gate electrode 130 and the epitaxial layer 110.
[0060] In this embodiment, the formation of the first oxide layer 510 at the bottom of the isolation trench 120 can effectively electrically isolate the isolation gate electrode 130 from the epitaxial layer 110. This isolation can prevent current leakage and improve the electrical performance and stability of the device.
[0061] As Figure 1 and Figure 2 shown, in some embodiments, a second oxide layer 520 is formed on the first oxide layer 510, and the second oxide layer 520 adheres to the side wall surface of the isolation trench 120, and the thickness of the second oxide layer 520 is less than that of the first oxide layer 510.
[0062] In this embodiment, the second oxide layer 520 covers the first oxide layer 510, especially adheres to the side wall surface of the isolation trench 120, which can further enhance the electrical isolation effect between the isolation gate electrode 130 and the epitaxial layer 110. This multi-layer oxide layer structure can effectively prevent current leakage and improve the electrical performance and stability of the device.
[0063] In high-frequency applications, the presence of the second oxide layer 520 can provide additional isolation, thereby further reducing the parasitic capacitance, increasing the switching speed, and reducing the power consumption.
[0064] As Figure 1 and Figure 2 shown, in some embodiments, a receiving groove is formed in the middle of the first oxide layer 510, and the second oxide layer 520 is formed on the wall surface of the receiving groove.
[0065] In this embodiment, the receiving groove structure increases the path of heat dissipation, which helps to dissipate heat more effectively. By optimizing the heat conduction path, local overheating can be reduced, and the reliability of the device under high-power conditions can be improved.
[0066] In actual implementation, both the first oxide layer 510 and the second oxide layer 520 are silicon dioxide layers.
[0067] In some embodiments, the active layer 200 may include an N+ well region and a P- well region. Meanwhile, a P+ well region may be fabricated within the P- well region, where the source layer 300 extends to be connected to the P+ well region, and the source layer 300 is also directly connected to the N+ well region.
[0068] In this way, the carriers flowing out from the source layer 300 can enter the channel a on both sides of the isolation trench 120 from the N+ well region, and then flow from the channel a to the drain substrate 100.
[0069] As Figure 3 shown, a plurality of isolation gate electrodes 130 may all be connected to the gate.
[0070] The above are all the preferred embodiments of the present application. It does not limit the protection scope of the present application accordingly. Therefore, all equivalent changes made according to the structure, shape, and principle of the present application should be covered within the protection scope of the present application.
Claims
1. A MOS field effect transistor, characterized in that: include: A drain substrate (100), an epitaxial layer (110) formed on the drain substrate (100), a plurality of isolation trenches (120) spaced apart from each other formed in the epitaxial layer (110), a plurality of partial regions of the sidewall surface of the isolation trench (120) protruding into the isolation trench (120), and an isolation gate electrode (130) formed in the isolation trench (120); An active layer (200), the active layer (200) being formed in the epitaxial layer (110), and the active layer (200) comprising channels (a) located on both sides of each of the isolation trenches (120); A source layer (300), wherein the source layer (300) is formed on the active layer (200).
2. The MOS field effect transistor according to claim 1, characterized in that: The side wall surface of the isolation trench (120) comprises a first region (121) and a second region (122), wherein the first region (121) is protruded toward the inside of the isolation trench (120), and the second region (122) is protruded in a direction away from the inside of the isolation trench (120).
3. The MOS field effect transistor according to claim 2, characterized in that: The first region (121) and the second region (122) are arranged to be spaced apart from each other.
4. The MOS field effect transistor according to claim 2, characterized in that: There are a plurality of the first region (121) and a plurality of the second region (122), and the first region (121) is arranged between two adjacent second regions (122).
5. The MOS field effect transistor according to claim 1, characterized in that: Also comprising an inner dielectric layer (400); The inner dielectric layer (400) is formed on a side of the isolation gate electrode (130) away from the drain substrate (100), so that the isolation gate electrode (130) is a buried structure.
6. The MOS field effect transistor according to claim 5, characterized in that: The source layer (300) also covers the inner dielectric layer (400), and a side of the inner dielectric layer (400) facing the source layer (300) is recessed toward the isolation gate electrode (130).
7. The MOS field effect transistor according to any one of claims 1 to 6, characterized in that: A first oxide layer (510) is formed at the bottom of the isolation trench (120), and the first oxide layer (510) is used to isolate the isolation gate electrode (130) and the epitaxial layer (110).
8. The MOS field effect transistor according to claim 7, characterized in that: A second oxide layer (520) is formed on the first oxide layer (510), and the second oxide layer (520) is attached to the side wall surface of the isolation trench (120), and the thickness of the second oxide layer (520) is smaller than that of the first oxide layer (510).
9. The MOS field effect transistor according to claim 8, characterized in that: A receiving groove is formed in the middle of the first oxide layer (510), and the second oxide layer (520) is formed on the wall surface of the receiving groove.
10. The MOS field effect transistor according to claim 8, characterized in that: The first oxide layer (510) and the second oxide layer (520) are both silicon dioxide layers.