Depletion mode and enhancement mode GaN monolithic integrated device
By introducing isolation layers into GaN devices, the key levels of enhanced devices and depleted devices are isolated, and the problem of interference between devices after increasing integration is solved, improving the integration and performance stability of devices.
Patent Information
- Application Number
- CN202421678780.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-15
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-07-15
AI Technical Summary
As the integration of GaN devices gradually increases, depletion devices and enhanced devices are prone to interfere with each other, affecting the performance and reliability of the devices.
The first channel layer, the first barrier layer, and the first gate metal of the enhancement device are isolated from the second channel layer, the second barrier layer, and the second gate metal of the depletion device to prevent mutual interference.
Through the design of the isolation layer, the enhanced device and the depletion device are not easily interfere with each other, which improves the integration and performance stability of GaN devices.
Smart Images
Figure CN222928735U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor devices, and particularly to a depletion-mode and enhancement-mode GaN monolithic integrated device. Background Art
[0002] GaN devices are high-performance electronic devices based on GaN materials. As a wide-bandgap semiconductor material, GaN has characteristics such as a large bandgap width, a high electron drift velocity, a high breakdown electric field, a high thermal conductivity, stable chemical properties, and radiation resistance. It is an ideal material for manufacturing high-temperature, high-power, and high-frequency electronic devices, and has obvious advantages in microwave high-power and high-temperature applications.
[0003] In the existing related technologies, GaN devices can be divided into depletion-mode devices and enhancement-mode devices according to the working mode. Depletion-mode devices are normally-closed devices while enhancement-mode devices are normally-open devices. In view of the above-mentioned related technologies, as the integration degree of GaN devices gradually increases, it is easy for depletion-mode devices and enhancement-mode devices to interfere with each other. Summary of the Invention
[0004] In order to improve the integration degree of GaN devices and make it difficult for enhancement-mode devices and depletion-mode devices to interfere with each other, the present application provides a depletion-mode and enhancement-mode GaN monolithic integrated device.
[0005] The depletion-mode and enhancement-mode GaN monolithic integrated device provided by the present application adopts the following technical solutions:
[0006] A depletion-mode and enhancement-mode GaN monolithic integrated device, comprising:
[0007] A substrate;
[0008] A buffer layer formed on the substrate;
[0009] An enhancement-mode device, which includes a first channel layer, a first barrier layer, a first gate electrode, and a first gate metal. The first channel layer is formed on the buffer layer, the first barrier layer is formed on the buffer layer, the first gate electrode is formed on the first barrier layer, and the first gate metal is formed on the first gate electrode;
[0010] A depletion-mode device, which includes a second channel layer, a second barrier layer, a second gate electrode, and a second gate metal. The second channel layer is formed on the buffer layer, the second barrier layer is formed on the buffer layer, the second gate electrode is formed on the second barrier layer, and the second gate metal is formed on the second gate electrode;
[0011] An isolation layer is located between the enhancement-mode device and the depletion-mode device, and the isolation layer is used to isolate the first channel layer, the first barrier layer, and the first gate metal of the enhancement-mode device from the second channel layer, the second barrier layer, and the second gate metal of the depletion-mode device.
[0012] By adopting the above technical solution, the isolation layer isolates the first channel layer, the first barrier layer, and the first gate metal of the enhancement-mode device from the second channel layer, the second barrier layer, and the second gate metal of the depletion-mode device, making it difficult for the enhancement-mode device and the depletion-mode device to interfere with each other, and improving the integration degree of the GaN device.
[0013] Optionally, one end of the isolation layer extends into the buffer layer.
[0014] By adopting the above technical solution, it is beneficial to improve the isolation effect between the enhancement-mode device and the depletion-mode device through the buffer layer, thereby improving the integration degree of the GaN device.
[0015] Optionally, the depth dimension of the isolation layer extending into the buffer layer is more than 1 / 3 of the thickness dimension of the buffer layer.
[0016] By adopting the above technical solution, it is beneficial to further improve the isolation effect between the enhancement-mode device and the depletion-mode device through the buffer layer, thereby improving the integration degree of the GaN device.
[0017] Optionally, the first gate electrode includes a first electrode metal and a P-type capping layer, the P-type capping layer is formed on the first barrier layer, and the first electrode metal is formed on the P-type capping layer.
[0018] By adopting the above technical solution, the manufacturing process of the P-type capping layer is relatively simple, and the parasitic conductance is small, making it easier to produce and use.
[0019] Optionally, the first gate metal includes a first metal layer and a second metal layer, the first metal layer is formed on the first gate electrode, the second metal layer is formed on the first metal layer, and the first metal layer and the second metal layer are connected by a first connection line;
[0020] And / or, the second gate metal includes a third metal layer and a fourth metal layer, the third metal layer is formed on the second gate electrode, the fourth metal layer is formed on the third metal layer, and the third metal layer and the fourth metal layer are connected by a second connection line.
[0021] Optionally, a first passivation layer is formed on the second metal layer, the first passivation layer is provided with a first groove, and the bottom of the first groove is formed on the second metal layer;
[0022] And / or, a second passivation layer is formed on the fourth metal layer, and a second groove is formed in the second passivation layer, and the bottom of the second groove is formed on the fourth metal layer.
[0023] Optionally, a plurality of the first gate electrodes are provided, and the enhancement-mode device further includes a first connection metal formed on the plurality of first gate electrodes;
[0024] And / or, a plurality of the second gate electrodes are provided, and the depletion-mode device further includes a second connection metal formed on the plurality of second gate electrodes.
[0025] Optionally, the first connection metal and the first gate metal are connected by a first filling metal;
[0026] And / or, the second connection metal and the second gate metal are connected by a second filling metal.
[0027] In summary, the present application includes at least one of the following beneficial technical effects:
[0028] 1. The isolation layer isolates the first channel layer, the first barrier layer, and the first gate metal of the enhancement-mode device from the second channel layer, the second barrier layer, and the second gate metal of the depletion-mode device, so that it is not easy for the enhancement-mode device and the depletion-mode device to interfere with each other, and the integration degree of the GaN device is improved. Description of the Drawings
[0029] Figure 1 is a schematic structural diagram of the overall structure of an embodiment of the present application.
[0030] Description of the reference numerals: 1, substrate; 2, nucleation layer; 3, buffer layer; 4, enhancement-mode device; 41, first channel layer; 42, first barrier layer; 43, first source electrode; 44, first drain electrode; 45, first electrode metal; 46, P-type cap layer; 47, first connection metal; 471, first filling metal; 48, first metal layer; 481, first connection line; 49, second metal layer; 491, first passivation layer; 492, first groove; 5, depletion-mode device; 51, second channel layer; 52, second barrier layer; 53, second source electrode; 54, second drain electrode; 55, second electrode metal; 56, second connection metal; 561, second filling metal; 57, third metal layer; 571, second connection line; 58, fourth metal layer; 581, second passivation layer; 582, second groove; 6, isolation layer. Detailed Description of the Embodiment
[0031] The following is a further detailed description of the present application in conjunction with the attached Figure 1 drawings.
[0032] An embodiment of the present application discloses a depletion-mode and enhancement-mode GaN monolithic integrated device. Refer to Figure 1 , the depletion-mode and enhancement-mode GaN monolithic integrated device includes a substrate 1, a nucleation layer 2, a buffer layer 3, an enhancement-mode device 4, a depletion-mode device 5, and an isolation layer 6.
[0033] Refer to Figure 1 , the material of the substrate 1 is a semiconductor material, such as silicon, silicon carbide, or sapphire, etc. The nucleation layer 2 is formed on the substrate 1, and the material of the nucleation layer 2 is a semiconductor material, such as AlN, GaN, or AlGaN. The buffer layer 3 is formed on the nucleation layer 2, and the material of the buffer layer 3 is a semiconductor material, such as AlGaAs, GaN, AlN, or AlGaN. Specifically, in the embodiment of the present application, the material of the substrate 1 is silicon, the material of the nucleation layer 2 is GaN, and the material of the buffer layer 3 is GaN. The enhancement-mode device 4 and the depletion-mode device 5 are both formed on the buffer layer 3, and the isolation layer 6 is located between the enhancement-mode device 4 and the depletion-mode device 5.
[0034] The enhancement-mode device 4 includes a first channel layer 41, a first barrier layer 42, a first source electrode 43, a first drain electrode 44, a first gate electrode, a first connecting metal 47, and a first gate metal. The first channel layer 41 is formed on the buffer layer 3, and the material of the first channel layer 41 is a semiconductor material, such as GaN or a GaN alloy. The first barrier layer 42 is formed on the first channel layer 41, and the material of the first barrier layer 42 is a semiconductor material, such as a ternary or quaternary alloy compound based on gallium nitride. Specifically, in the embodiment of the present application, the material of the first channel layer 41 is GaN, and the material of the first barrier layer 42 is AlGaN. The first source electrode 43 is formed on one side of the first barrier layer 42, and the first drain electrode 44 is formed on the other side of the first barrier layer 42.
[0035] There are two first gate electrodes, and both of the two first gate electrodes are formed on the first barrier layer 42; the first gate electrode includes a first electrode metal 45 and a P-type cap layer 46. The P-type cap layer 46 is formed on the first barrier layer 42, and the first electrode metal 45 is formed on the P-type cap layer 46. A first dielectric layer is formed on the first electrode metal 45, the first connecting metal 47 is formed on the first dielectric layer, and several first gate electrodes are all within the area covered by the first connecting metal 47, and the edge of the first connecting metal 47 extends and protrudes beyond the first gate electrode.
[0036] The first gate metal includes a first metal layer 48 and a second metal layer 49. The first metal layer 48 and the first connection metal 47 are connected by two first filling metals 471 respectively corresponding to each first gate electrode. The first metal layer 48 is formed on the first gate electrode, the second metal layer 49 is formed on the first metal layer 48, and the first metal layer 48 and the second metal layer 49 are connected by a first connection line 481. A first passivation layer 491 is formed on the second metal layer 49. The first passivation layer 491 is provided with a first groove 492. The bottom of the first groove 492 is formed on the second metal layer 49, and the first connection line 481 is located in the area covered by the first groove 492.
[0037] Referring to Figure 1 , the enhancement device 4 includes a second channel layer 51, a second barrier layer 52, a second source electrode 53, a second drain electrode 54, a second gate electrode, a second connection metal 56 and a second gate metal. The second channel layer 51 is formed on the buffer layer 3. The material of the second channel layer 51 is a semiconductor material, such as GaN or a GaN alloy. The second barrier layer 52 is formed on the second channel layer 51. The material of the second barrier layer 52 is a semiconductor material, such as a ternary or quaternary alloy compound based on gallium nitride. Specifically, in the embodiment of the present application, the material of the second channel layer 51 is GaN, and the material of the second barrier layer 52 is AlGaN. The second source electrode 53 is formed on one side of the second barrier layer 52, and the second drain electrode 54 is formed on the other side of the second barrier layer 52.
[0038] There are two second gate electrodes, and both second gate electrodes are formed on the second barrier layer 52; the second gate electrode includes a second electrode metal 55, and the second electrode metal 55 is formed on the second barrier layer 52. A second dielectric layer is formed on the second electrode metal 55, the second connection metal 56 is formed on the second dielectric layer, and several second gate electrodes are all within the area covered by the second connection metal 56, and the edge of the second connection metal 56 extends and protrudes beyond the second gate electrode.
[0039] The second gate metal includes a third metal layer 57 and a fourth metal layer 58. The third metal layer 57 and the first connection metal 47 are connected by two first filling metals 471 respectively corresponding to each first gate electrode. The third metal layer 57 is formed on the first gate electrode, the fourth metal layer 58 is formed on the third metal layer 57, and the third metal layer 57 and the fourth metal layer 58 are connected by a second connection line 571. A first passivation layer 491 is formed on the fourth metal layer 58. The first passivation layer 491 is provided with a second groove 582. The bottom of the second groove 582 is formed on the fourth metal layer 58, and the second connection line 571 is located in the area covered by the second groove 582.
[0040] Referring to Figure 1, the isolation layer 6 is formed by an ion implantation process or an isolation process that can be used. The isolation layer 6 extends from the first passivation layer 491 and the second passivation layer 581 into the buffer layer 3, and the isolation layer 6 isolates the first channel layer 41, the first barrier layer 42, the first metal layer 48, the second metal layer 49, and the first gate metal of the enhancement-mode device 4 from the second channel layer 51, the second barrier layer 52, the third metal layer 57, the fourth metal layer 58, and the second gate metal of the depletion-mode device 5. The depth dimension of the isolation layer 6 extending into the buffer layer 3 is more than 1 / 3 of the thickness dimension of the buffer layer 3, and the depth dimension of the isolation layer 6 extending into the buffer layer 3 is 0 - 200 nm.
[0041] The manufacturing method of the above-mentioned depletion-mode and enhancement-mode GaN monolithic integrated device includes the following steps:
[0042] S1. Epitaxially grow a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer, a first barrier layer 42, and a second barrier layer 52 in sequence.
[0043] S2. Deposit and etch to form a P-type cap layer, and then etch and deposit to form a first gate metal and a second gate metal.
[0044] S3. Deposit to form a first dielectric layer and a second dielectric layer.
[0045] S4. Deposit and etch to form a first source electrode 43, a first drain electrode 44, a first gate metal, a second source electrode 53, a second drain electrode 54, and a second gate metal.
[0046] S5. Deposit to form a third dielectric layer and a fourth dielectric layer.
[0047] S6. Etch to open openings for a first filling metal 471 and a second filling metal 561, and deposit and etch to form the first filling metal 471 and the second filling metal 561.
[0048] S7. Deposit to form a first metal layer 48 and a third metal layer 57.
[0049] S8. Etch to open openings for a first connection line 481 and a second connection line 571, and deposit and etch to form the first connection line 481 and the second connection line 571.
[0050] S9. Deposit to form a second metal layer 49 and a fourth metal layer 58, make both the first metal layer 48 and the second metal layer 49 in ohmic contact with the first connection line 481, and make both the third metal layer 57 and the fourth metal layer 58 in ohmic contact with the second connection line 571.
[0051] S10. Deposit to form a first passivation layer 491 and a second passivation layer 581, and then etch to open a first groove 492 and a second groove 582.
[0052] S11. Form an isolation layer 6 by means of ion implantation.
[0053] The implementation principle of a depletion-mode and enhancement-mode GaN monolithic integrated device in an embodiment of the present application is as follows: The isolation layer 6 isolates the first channel layer 41, the first barrier layer 42, the first metal layer 48, the second metal layer 49, and the first gate metal of the enhancement-mode device 4 from the second channel layer 51, the second barrier layer 52, the third metal layer 57, the fourth metal layer 58, and the second gate metal of the depletion-mode device 5, making it difficult for the enhancement-mode device 4 and the depletion-mode device 5 to interfere with each other, and improving the integration degree of the GaN device.
[0054] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereby. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application shall be covered within the protection scope of the present application.
Claims
1. A depletion-mode and enhancement-mode GaN monolithic integrated device, characterized in that: include: Substrate (1); A buffer layer (3), wherein the buffer layer (3) is formed on the substrate (1); An enhancement-mode device (4), the enhancement-mode device (4) comprising a first channel layer (41), a first barrier layer (42), a first gate electrode and a first gate metal, the first channel layer (41) being formed on a buffer layer (3), the first barrier layer (42) being formed on the buffer layer (3), the first gate electrode being formed on the first barrier layer (42), and the first gate metal being formed on the first gate electrode; A depletion-type device (5), the depletion-type device (5) comprising a second channel layer (51), a second barrier layer (52), a second gate electrode and a second gate metal, the second channel layer (51) being formed on a buffer layer (3), the second barrier layer (52) being formed on the buffer layer (3), the second gate electrode being formed on the second barrier layer (52), and the second gate metal being formed on the second gate electrode; An isolation layer (6), the isolation layer (6) being located between the enhancement-type device (4) and the depletion-type device (5), the isolation layer (6) being used to isolate a first channel layer (41), a first barrier layer (42) and a first gate metal of the enhancement-type device (4) from a second channel layer (51), a second barrier layer (52) and a second gate metal of the depletion-type device (5).
2. A depletion-mode and enhancement-mode GaN monolithic integrated device according to claim 1, characterized in that: One end of the isolation layer (6) extends into the buffer layer (3).
3. A depletion-mode and enhancement-mode GaN monolithic integrated device according to claim 2, characterized in that: The depth dimension of the isolation layer (6) extending into the buffer layer (3) is more than 1 / 3 of the thickness dimension of the buffer layer (3).
4. The depletion-mode and enhancement-mode GaN monolithic integrated device according to claim 1, characterized in that: The first gate electrode comprises a first electrode metal (45) and a P-type cap layer (46), wherein the P-type cap layer (46) is formed on the first barrier layer (42), and the first electrode metal (45) is formed on the P-type cap layer (46).
5. The depletion-mode and enhancement-mode GaN monolithic integrated device according to claim 1, characterized in that: The first gate metal comprises a first metal layer (48) and a second metal layer (49), the first metal layer (48) is formed on the first gate electrode, the second metal layer (49) is formed on the first metal layer (48), and the first metal layer (48) and the second metal layer (49) are connected via a first connecting line (481); And / or, the second gate metal includes a third metal layer (57) and a fourth metal layer (58), the third metal layer (57) is formed on the second gate electrode, the fourth metal layer (58) is formed on the third metal layer (57), and the third metal layer (57) and the fourth metal layer (58) are connected via a second connecting line (571).
6. A depletion-mode and enhancement-mode GaN monolithic integrated device according to claim 5, characterized in that: A first passivation layer (491) is formed on the second metal layer (49), the first passivation layer (491) is provided with a first groove (492), and the bottom of the first groove (492) is formed on the second metal layer (49); And / or, a second passivation layer (581) is formed on the fourth metal layer (58), the second passivation layer (581) is provided with a second groove (582), and the bottom of the second groove (582) is formed on the fourth metal layer (58).
7. The depletion-mode and enhancement-mode GaN monolithic integrated device according to claim 1, characterized in that: The first gate electrodes are provided with a plurality of them, and the enhancement mode device (4) further comprises a first connection metal (47), wherein the first connection metal (47) is formed on the plurality of first gate electrodes; And / or, the second gate electrode is provided with a plurality of second gate electrodes, the depletion-mode device (5) further comprises a second connection metal (56), and the second connection metal (56) is formed on the plurality of second gate electrodes.
8. The depletion-mode and enhancement-mode GaN monolithic integrated device according to claim 7, characterized in that: The first connection metal (47) is connected to the first gate metal via a first filling metal (471); And / or, the second connection metal (56) is connected to the second gate metal via a second filling metal (561).