Gallium oxide MOSFET channel type device
By adopting the multi-layer structure design of gallium oxide MOSFET channel devices in SiC MOSFET devices, the problem of insufficient collapse voltage of existing SiC MOSFET devices is solved, and higher collapse voltage and better reliability are achieved. It is suitable for power switches and high-power devices in new energy vehicles.
Patent Information
- Application Number
- CN202422007149.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-19
AI Technical Summary
The collapse voltage of existing SiC MOSFET devices is insufficient, making it difficult to meet the needs of power switch driving and battery life of new energy vehicles.
Using gallium oxide MOSFET channel device, the Schottky contact area and collapse voltage are increased by setting the gallium oxide epitaxial layer on the substrate and constructing a multi-layer structure on it, including a drain metal layer, a protection ring layer, a P-type and N-type high-doping layer, a source hole etching layer, a gate hole and a checkerboard matrix gate oxide layer, etc.
It significantly improves the device's collapse voltage, is suitable for high-power devices, and uses the progressive protection ring and silicon oxide protection ring mesh layer design to prevent horizontal leakage and breakdown, improving the reliability of the overall device.
Smart Images
Figure CN222967299U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a gallium oxide MOSFET channel-type device. Background Art
[0002] In the field of new energy vehicles, common IGBT and silicon carbide MOSFET power switch chips are generally applied to charging piles, AC-DC converters, and motor modules. To increase the driving range of new energy vehicles, it is necessary to increase the number of chips or improve the breakdown voltage of a single chip in the power module to meet the requirements of power switch drive and battery endurance in the vehicle system. Currently, the known third-generation semiconductor wide-bandgap SiC MOSFET devices on the market are relatively mature technologies. Although the breakdown voltage of the packaged chips can reach 1200V, there is still room for improvement to further reduce the number of power switch chips. Content of the Utility Model
[0003] The purpose of the utility model is to improve the breakdown voltage of existing SiC MOSFET devices, and a gallium oxide MOSFET channel-type device is provided.
[0004] The purpose of the utility model is achieved through the following technical solutions:
[0005] A gallium oxide MOSFET channel-type device is provided, including a substrate and a gallium oxide epitaxial layer provided on the substrate;
[0006] A drain metal layer, a first layer of alignment mark layer, a protection ring layer, a P-type highly doped layer, an N-type highly doped layer, a source hole layer, a source metal contact layer, a gate hole and a gate oxide layer, a gate metal contact layer, a source-gate first via layer, a first connection metal layer, a source-gate second via layer, a second connection metal layer, and a top protection layer are provided on the gallium oxide epitaxial layer;
[0007] Among them, the gate hole and the gate oxide layer are of a checkerboard matrix structure.
[0008] As an optional item, the substrate and the gallium oxide epitaxial layer are bonded and connected through high-temperature nano-silver glue.
[0009] As an optional item, the substrate is a SiC substrate.
[0010] As an optional item, the gallium oxide epitaxial layer is a gallium trioxide epitaxial layer.
[0011] As an optional item, the protection ring layer is a silicon oxide protection ring mesh layer.
[0012] As an optional item, the source hole layer is arranged in a matrix.
[0013] As a preferred option, the source region corresponding to the source metal contact layer is square.
[0014] As a preferred option, the depth of the holes in the source metal contact layer exceeds the depth of the holes in the gate metal contact layer.
[0015] As a preferred option, the second connecting metal layer is disposed above the gallium oxide epitaxial layer.
[0016] As a preferred option, the substrate is an N-type substrate.
[0017] It should be further noted that the technical features corresponding to the above options can be combined or replaced with each other to form a new technical solution without conflict.
[0018] Compared with the prior art, the beneficial effects of the present utility model are as follows:
[0019] (1) The epitaxial structure of the present utility model uses gallium oxide, a super-wide bandgap semiconductor material, to increase the breakdown voltage of the device; at the same time, the gate holes and the gate oxide layer are in a checkerboard matrix structure, increasing the Schottky contact area of the gate metal and further improving the overall breakdown voltage of the device, which is suitable for high-power devices.
[0020] (2) In one example, the protection ring layer is a silicon oxide protection ring mesh layer. Through the gradient protection ring design and the silicon oxide protection ring mesh design, it can prevent horizontal leakage on the surface of the device and inside the device epitaxy, and prevent breakdown of adjacent devices.
[0021] (3) In one example, the source hole layer is arranged in an array matrix, increasing the area of the metal-oxide-semiconductor contact of the device, increasing the depletion region area of the transistor, and enabling the overall breakdown voltage of the device.
[0022] (4) In one example, the depth of the holes in the source metal contact layer exceeds the depth of the holes in the gate metal contact layer, which helps to disperse and reduce the peak electric field intensity at the gate and drain ends, and reduce the breakdown from the gate to the drain.
[0023] (5) In one example, the source region is square, increasing the depletion region area formed with the surrounding gates, so that the higher the breakdown voltage that the equivalent device can control.
[0024] (6) In one example, the second connecting metal layer is disposed above the gallium oxide epitaxial layer, so that the bonding pads for wire bonding are above the device, effectively reducing the device area, improving the area utilization rate, and also improving the heat dissipation efficiency of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 It is a schematic cross-sectional structure diagram of a gallium oxide MOSFET channel-type device shown in an embodiment of the present utility model;
[0026] Figure 2 This is a top - view structural schematic diagram of a gallium oxide MOSFET channel - type device shown in an embodiment of the present utility model;
[0027] Figures 3 - 18 This is a cross - sectional structural process schematic diagram of manufacturing a gallium oxide device shown in an embodiment of the present utility model;
[0028] Figures 19 - 34 This is a top - view structural process schematic diagram of manufacturing a gallium oxide device shown in an embodiment of the present utility model.
[0029] In the figure: 1 - drain metal layer; 2 - first layer of alignment mark layer; 3 - protection ring layer; 4 - P - type highly doped layer; 5 - N - type highly doped layer; 6 - source via layer; 7 - source metal contact layer; 8 - gate via and gate oxide layer; 9 - gate metal contact layer; 10 - first source - gate via layer; 11 - first connection metal layer; 12 - second source - gate via layer; 13 - second connection metal layer; 14 - top protective layer. Detailed implementation manners
[0030] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present utility model, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts belong to the scope of protection of the present utility model.
[0031] In the description of the present utility model, it should be noted that the directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings. These are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of the present utility model. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0032] In the description of the present utility model, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.
[0033] In addition, the technical features involved in different embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.
[0034] Referring to Figures 1 - 2 , in an exemplary embodiment, a gallium oxide MOSFET channel-type device is provided, including a substrate and a gallium oxide epitaxial layer disposed on the substrate;
[0035] A drain metal layer 1, a first layer of alignment mark layer 2, a guard ring layer 3, a P-type highly doped layer 4, an N-type highly doped layer 5, a source via layer 6, a source metal contact layer 7, a gate via and gate oxide layer 8, a gate metal contact layer 9, a first source-gate via layer 10, a first connecting metal layer 11, a second source-gate via layer 12, a second connecting metal layer 13, and a top protective layer 14 are disposed on the gallium oxide epitaxial layer;
[0036] Among them, the gate via and gate oxide layer 8 has a checkerboard matrix structure. Adopting this structure enables the device gate to be matrix-designed, which can increase the Schottky contact area of the gate metal by about half and improve the overall breakdown voltage of the device. At the same time, the epitaxial structure of the present utility model uses gallium oxide, a super-wide bandgap semiconductor material, to further improve the overall breakdown voltage of the device, which is suitable for high-power devices.
[0037] Further, the substrate and the gallium oxide epitaxial layer are bonded and connected by high-temperature nano-silver glue.
[0038] The substrate is a SiC substrate. In other embodiments, the substrate is not limited to silicon carbide, and can also be a gallium oxide substrate, a silicon substrate, a sapphire substrate, a high-resistance silicon substrate, an alumina substrate, a silicon-on-insulator (SOI) substrate, a diamond substrate, or a glass substrate;
[0039] Further, the gallium oxide epitaxial layer is a gallium trioxide epitaxial layer (Ga 2 O 3 = 4.5 eV), which raises the breakdown voltage of the device to 6.5 MV / cm.
[0040] Further, the guard ring layer 3 is a silicon oxide guard ring mesh layer. Specifically, the gradient guard ring design and the silicon oxide guard ring mesh design can prevent horizontal leakage on the surface of the device and inside the device epitaxy, and prevent breakdown of adjacent devices.
[0041] Further, the source via layer 6 is arranged in a matrix. Specifically, the MOSFET device array is arranged in a matrix design, which increases the area of the metal-oxide-semiconductor contact of the device. In other words, it increases the depletion region area of the transistor and improves the overall breakdown voltage of the device.
[0042] Further, the source region corresponding to the source metal contact layer 7 is square, and the depth of the holes in the source metal contact layer 7 exceeds the depth of the holes in the gate metal contact layer 9. Specifically, for the deep-hole design of the source region, from the perspective of the device's vertical direction, the depth of the deep holes in the source exceeds the depth of the gate channel, and it is closer to the bottom drain metal layer 1. It is similar to the source field plate in the vertical direction of the device, which helps to disperse and reduce the peak value of the electric field intensity between the gate and the drain, and reduce the breakdown from the gate to the drain. The square pattern design of the source increases the area of the equivalent depletion region formed with the surrounding gates. The larger the equivalent depletion region area, the higher the breakdown voltage that the equivalent device can control. In other embodiments, the source region is not limited to the square design. As long as it can increase the "perimeter" of the pattern and the area of the depletion region formed with the surrounding gates, such as rectangular, circular, regular hexagonal, etc., the breakdown voltage of the device can be improved.
[0043] Further, the second connecting metal layer 13 is disposed above the gallium oxide epitaxial layer, so that the bonding pads for wire bonding are above the device, effectively reducing the device area, improving the area utilization rate, and also improving the device heat dissipation efficiency.
[0044] Further, the substrate is an N-type substrate.
[0045] Refer to Figures 3 - 18 (or Figures 19 - 34 ), for this device, a corresponding manufacturing method is also designed. The process flow of a single gallium oxide MOSFET channel-type device includes:
[0046] S1. Use a heat-resistant nano silver glue and coat it on a 6-inch silicon carbide substrate. Bond the "crystal plane" of a 4-inch gallium oxide epitaxial wafer to the 6-inch silicon carbide substrate to complete the growth of the gallium oxide epitaxial structure of the ultra-wide bandgap material on the 4-inch silicon carbide substrate, and then bond it to the 6-inch silicon carbide substrate for device process development, as Figure 3 ; Among them, the high-temperature bonding material for the bonding process is not limited to high-temperature nano silver glue, including: gold-tin alloy with a ratio of 80-20%.
[0047] S2. Define the photolithography pattern of the drain region on the back of the 4-inch gallium oxide epitaxial wafer. After performing N-type high-temperature silicon ion implantation at 500-600 degrees, deposit ohmic metal to obtain the drain metal layer 1 and then remove the photoresist, as Figure 4 ;
[0048] S3. After debonding the 4-inch gallium oxide epitaxial wafer, perform high-temperature annealing to form an ohmic alloy, as Figure 5 ;
[0049] S4. Define the first-layer photolithography alignment pattern, sputter and deposit alignment metal to obtain the first-layer alignment mark layer 2, as Figure 6 ;
[0050] S5. Define the photolithography pattern for the source region on the gallium oxide epitaxy, perform P-type ion implantation with an ion implantation energy of approximately 250 keV and an implantation dose of approximately 1E15 / cm 2 with a deep implantation depth to form the device source isolation region and the guard ring region, obtaining the guard ring layer 3, as shown in Figure 7 ;
[0051] S6. After defining the photoresist patterns for the gate and source regions through photolithography, perform high-dose P-type boron or aluminum ion implantation and then remove the photoresist to obtain the P-type highly doped layer 4 and the source hole layer 6, as shown in Figure 8 ;
[0052] S7. After defining the photoresist patterns for the gate and source regions through photolithography, perform high-dose N-type nitrogen or phosphorus ion implantation and then remove the photoresist to obtain the N-type highly doped layer 5, as shown in Figure 9 ;
[0053] S8. Define the region of the device source through photolithography, dry-etch the source region, and then remove the photoresist, as shown in Figure 10 ;
[0054] S9. Define the region of the device source metal through photolithography, evaporate and deposit titanium, nickel, and silver metals, obtain the source metal contact layer 7, and then remove the photoresist. After using chemical polishing to planarize the excess metal on the surface, perform annealing at 500 - 600 degrees to form an ohmic alloy, as shown in Figure 11 ;
[0055] S10. Define the photoresist pattern for the channel-type gate through photolithography, dry-etch the gate region, then remove the photoresist, deposit a gate oxide film with a thickness of approximately 500 nm to obtain the gate hole and the gate oxide layer 8, as shown in Figure 12 ;
[0056] S11. Define the region of the device gate metal through photolithography, evaporate and deposit channel-type gate polysilicon, then remove the photoresist, deposit 100 nm of silicon nitride to obtain the gate metal contact layer 9, as shown in Figure 13 ;
[0057] S12. Define the first via layer 10 for the source and gate through photolithography, dry-etch 100 nm of silicon nitride, and then remove the photoresist, as shown in Figure 14 ;
[0058] S13. Define the region of the first connecting metal layer 11 through photolithography, evaporate and deposit a 2 - um - thick metal layer, then remove the photoresist, deposit 200 nm of silicon nitride, coat a 3 - um - thick photosensitive PBO polymer material, bake it dry, and use chemical polishing to planarize the excess PBO on the surface, as shown in Figure 15 ;
[0059] S14. Define the second source-gate via layer 12 using a lithography process. After dry etching 2 μm of photosensitive PBO and 200 nm of silicon nitride, the photoresist is then removed, as Figure 16 ;
[0060] S15. Define the area of the connecting metal layer 13 using a lithography process. Evaporate and deposit a 4-μm-thick metal layer, then remove the photoresist, deposit 300 nm of silicon nitride, coat a 5-μm-thick photosensitive PBO polymer material, bake it dry, and use chemical polishing to planarize the excess PBO on the surface, as Figure 17 ;
[0061] S16. Define the opening area of the top protective layer 14 using a lithography process. After dry etching 4 μm of photosensitive PBO polymer material and 300 nm of silicon nitride, the photoresist is then removed, as Figure 18 .
[0062] This process enables wafers with an epitaxial layer smaller than 6 inches, such as 4-inch epitaxial wafers, to be compatible with 6-inch semiconductor process flows. Not only can the fourth-generation semiconductor material replace the third-generation semiconductor material to increase the breakdown voltage of the device, but it can also be compatible with epitaxial wafers of different sizes. This manufacturing method will break the traditional process that can only perform process development on epitaxial wafers of the same size. The channel-type MOSFET device designed in this patent not only increases the utilization area of the device but also improves the overall breakdown voltage of the device.
[0063] The above specific embodiments are detailed descriptions of the present invention. It cannot be determined that the specific embodiments of the present invention are limited only to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions and substitutions can still be made, which should all be regarded as falling within the protection scope of the present invention.
Claims
1. A gallium oxide MOSFET channel device, characterized in that: It includes a substrate and a gallium oxide epitaxial layer disposed on the substrate; The gallium oxide epitaxial layer is provided with a drain metal layer, a first alignment mark layer, a guard ring layer, a P-type high-doped layer, an N-type high-doped layer, a source hole layer, a source metal contact layer, a gate hole and a gate oxide layer, a gate metal contact layer, a source gate first through hole layer, a first connection metal layer, a source gate second through hole layer, a second connection metal layer and a top protection layer; Wherein, the gate holes and the gate oxide layer are in a chessboard matrix structure.
2. A gallium oxide MOSFET channel device according to claim 1, characterized in that: The substrate and the gallium oxide epitaxial layer are bonded and connected via high-temperature nano silver glue.
3. A gallium oxide MOSFET channel device according to claim 1, characterized in that: The substrate is a SiC substrate.
4. The gallium oxide MOSFET channel device according to claim 1, characterized in that: The gallium oxide epitaxial layer is a gallium trioxide epitaxial layer.
5. The gallium oxide MOSFET channel device according to claim 1, characterized in that: The guard ring layer is a silicon oxide guard ring mesh layer.
6. The gallium oxide MOSFET channel device according to claim 1, characterized in that: The source electrode hole etching layers are arranged in a matrix.
7. A gallium oxide MOSFET channel device according to claim 6, characterized in that: The source region corresponding to the source metal contact layer is square.
8. The gallium oxide MOSFET channel device according to claim 1, characterized in that: The depth of the hole in the source metal contact layer exceeds the depth of the hole in the gate metal contact layer.
9. The gallium oxide MOSFET channel device according to claim 1, characterized in that: The second connection metal layer is disposed above the gallium oxide epitaxial layer.
10. The gallium oxide MOSFET channel device according to claim 1, characterized in that: The substrate is an N-type substrate.