SiC VDMOSFET device

Abstract

The utility model discloses a SiC VDMOSFET device, and relates to the technical field of semiconductors. According to the utility model, ion implantation is carried out on the SiC Drift layer at the middle bottom of the device gate to form a heavily doped PP region, and ohmic contact is realized on the top surface of the PP region through preparation, so that the gate Poly layer is connected with the PP region. When a driving voltage is applied to the gate Poly layer, the PP region can release a part of gate driving voltage stress, so that the voltage stress on the gate oxide layer is reduced, the gate oxide layer is protected, and in the device blocking process, the PP region is located at the bottom of the gate and can shield electric field concentration generated by drain voltage, and the gate oxide layer is protected again.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a SiC VDMOSFET device. Background Art

[0002] In high-power power device applications, Si-based IGBTs have always been the mainstay. Although the switching performance of IGBTs is weak, due to their special bipolar structure, they can withstand high voltages, and the conductivity modulation effect under high currents also reduces the internal resistance of the device, resulting in better static performance. However, with the continuous development of society, many markets are moving towards more high-voltage and more efficient technical fields, such as new energy vehicles, photovoltaic energy storage, charging piles, etc. This has imposed increasingly stringent requirements on power devices, and traditional Si-based devices can no longer meet these usage requirements.

[0003] As a typical product of the third-generation wide bandgap semiconductor devices, SiC MOSFETs have many advantages such as high breakdown voltage, low on-state loss, high switching frequency, and low thermal resistance in terms of performance. Therefore, they are considered to be the main products in the future high-voltage and high-power fields. However, in addition to the disadvantage of high cost, the quality of the gate oxide layer directly grown by thermal oxidation on SiC MOSFETs has always been a major problem. Since the gate oxide layer SiO2 grown on SiC materials is rich in many defects inside, such as clusters, vacancies, etc., this leads to the fact that during the long-term use of the device, if the design is improper, the gate oxide layer is prone to field strength concentration and breakdown failure. Therefore, how to better protect the gate oxide layer and improve the long-term use reliability of the gate oxide layer is crucial. Summary of the Utility Model

[0004] Aiming at the above problems, the utility model provides a SiC VDMOSFET device that reduces the voltage stress on the gate oxide layer, protects the gate oxide layer, and shields the electric field concentration generated by the drain voltage.

[0005] The technical solution of the utility model is as follows:

[0006] A SiC VDMOSFET device includes a SiC Sub layer, a SiC Drift layer, and a JFET region arranged in sequence from bottom to top;

[0007] On the JFET region are provided:

[0008] A P-body region extending downward from the top surface of the JFET region;

[0009] An NP region extending downward from the top surface of the P-body region, with a spacing from the bottom surface of the P-body region; that is, the depth of the P-body region is greater than the depth of the NP region;

[0010] The PP regions are respectively formed in the middle of the JFET region and in the P-body region; the PP region in the P-body region extends downward from the top surface of the NP region and is connected thereto;

[0011] The ohmic contact layer is formed on the top surface of the PP region in the JFET region;

[0012] The gate oxide layer is respectively formed on the top surfaces of the NP region, the P-body region and the PP region;

[0013] The Poly layer is formed on the top surfaces of the gate oxide layer and the ohmic contact layer;

[0014] The isolation dielectric layer wraps the gate oxide layer and the Poly layer, and its bottom surface is connected to the NP region.

[0015] Specifically, the bottom surface depth of the JFET region is 1.2 um - 2 um.

[0016] Specifically, the bottom surface depth of the P-body region is 0.8 um - 1.2 um.

[0017] Specifically, the bottom surface depth of the NP region is 0.3 um - 0.6 um.

[0018] Specifically, the bottom surface depth of the PP region is 0.4 um - 0.8 um.

[0019] Specifically, the thickness of the ohmic contact layer is 0.1 um - 0.5 um.

[0020] Specifically, the thickness of the gate oxide layer is 30 nm - 70 nm.

[0021] Specifically, the thickness of the Poly layer is 0.5 um - 1.2 um.

[0022] In order to better protect the gate oxide layer of the SiC MOSFET, the present utility model ion-implants the SiC Drift layer at the middle bottom of the device gate to form a heavily doped PP region, and realizes ohmic contact on the top surface of the PP region, so that the gate Poly layer is connected to the PP region. The advantage brought by this is that when the gate Poly layer is subjected to the driving voltage, the PP region can release a part of the gate driving voltage stress, thereby reducing the voltage stress on the gate oxide layer and protecting the gate oxide layer to a certain extent. During the device blocking process, since the PP region is at the bottom of the gate, it can also shield the electric field concentration generated by the drain voltage and protect the gate oxide layer again. Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of the SiC MOSFET of the present utility model;

[0024] Figure 2 It is a schematic structural diagram of step S100 of the present utility model;

[0025] Figure 3 It is a schematic structural diagram of step S200 of the present utility model;

[0026] Figure 4 It is a schematic structural diagram of step S300 of the present utility model;

[0027] Figure 5 It is a schematic structural diagram of step S400 of the present utility model;

[0028] Figure 6 It is a schematic structural diagram of step S500 of the present utility model;

[0029] Figure 7 It is a schematic structural diagram of step S700 of the present utility model;

[0030] Figure 8 It is a schematic structural diagram of step S800 of the present utility model;

[0031] Figure 9 It is a schematic structural diagram of step S900 of the present utility model;

[0032] Figure 10 It is a schematic structural diagram of step S1000 of the present utility model;

[0033] Figure 11 It is a schematic structural diagram of step S1100 of the present utility model;

[0034] In the figure, 1 is the SiC Sub layer, 2 is the SiC Drift layer, 3 is the JFET region, 4 is the P-body region, 5 is the NP region, 6 is the PP region, 7 is the ohmic contact layer, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the source ohmic contact layer, and 12 is the front electrode metal layer. Specific embodiments

[0035] The present utility model will be described in detail below with reference to specific actual cases. Examples of the embodiments are shown in the accompanying drawings. The illustrative embodiments and descriptions thereof of the present utility model are only used to explain the present utility model and shall not be construed as a limitation to the present utility model.

[0036] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present utility model. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0037] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0038] A method for fabricating a SiC VDMOSFET device includes the following steps:

[0039] S100, epitaxially grow a SiC Drift layer 2 on a SiC Sub layer 1; as Figure 2 shown;

[0040] S200, preliminarily form a JFET region 3 on the top surface of the SiC Drift layer 2 by oblique N ion implantation; as Figure 3 shown;

[0041] The bottom depth of the JFET region 3 in step S200 is 1.2 um - 2 um, and the doping concentration is 5E16 - 1E18 cm -2 .

[0042] S300, preliminarily form a P-body region 4 on the top surface of the JFET region 3 by oblique Al ion implantation; as Figure 4 shown;

[0043] The bottom depth of the P-body region 4 in step S300 is 0.8 um - 1.2 um, and the doping concentration is 1E17 - 3E18 cm -2 .

[0044] S400, preliminarily form an NP region 5 on the top surface of the P-body region 4 by oblique N ion implantation; as Figure 5 shown;

[0045] The bottom depth of the NP region 5 in step S400 is 0.3 um - 0.6 um, and the doping concentration is 1E18 - 1E19 cm-2 。

[0046] S500, initially form the PP region 6 by obliquely implanting Al ions on the top surfaces of the JFET region 3 and the P-body region 4; as Figure 6 shown;

[0047] The bottom surface depth of the PP region 6 in step S500 is 0.4um - 0.8um, and the doping concentration is 1E18 - 1E19 cm -2 。

[0048] S600, completely form the implanted regions of the JFET region 3, the P-body region 4, the NP region 5, and the PP region 6 through high-temperature ion activation;

[0049] The high-temperature activation annealing temperature in step S600 is 1600°C - 1900°C.

[0050] S700, form an ohmic contact layer 7 on the top surface of the PP region 6 in the JFET region 3 by Ni metal sputtering followed by thermal annealing; as Figure 7 shown;

[0051] The thickness of the Ni metal in step S700 is 0.1um - 0.5um.

[0052] S800, grow a gate oxide layer 8 on the top surfaces of the JFET region 3, the P-body region 4, and the NP region 5 by dry oxidation; as Figure 8 shown;

[0053] The thickness of the gate oxide layer 8 in step S800 is 30nm - 70nm.

[0054] S900, form a Poly layer 9 on the top surfaces of the ohmic contact layer 7 and the gate oxide layer 8 by polycrystalline silicon Poly deposition for use as the gate electrode of the device; as Figure 9 shown;

[0055] The thickness of the Poly layer 9 in step S900 is 0.5um - 1.2um.

[0056] S1000, form an isolation dielectric layer 10 on the top surfaces of the NP region 5 and the Poly layer 9 by oxide layer deposition for use as the dielectric to prevent short circuit between the gate electrode and the source electrode of the device; as Figure 10 shown;

[0057] S1100, form a source ohmic contact layer 11 on the top surfaces of the NP region 5 and the PP region 6 by Ni metal sputtering followed by thermal annealing; as Figure 11 shown;

[0058] The thickness of the Ni metal in step S1100 is 0.1um - 0.5um.

[0059] S1200, a front electrode metal layer 12 is formed on the top of the device by means of Ti / AlCu metal sputtering. As Figure 1 shown.

[0060] In the Ti / AlCu in step S1200, the thickness of the Ti metal is 0.1 um - 0.3 um, and the thickness of the AlCu metal is 3 um - 5 um.

[0061] A SiC VDMOSFET device includes an SiC Sub layer 1, an SiC Drift layer 2, and a JFET region 3 arranged in sequence from bottom to top;

[0062] On the JFET region 3 are provided:

[0063] A P-body region 4 extends downward from the top surface of the JFET region 3 and has a spacing from the bottom surface of the JFET region 3; that is, the depth of the P-body region 4 is less than the depth of the JFET region 3;

[0064] An NP region 5 extends downward from the top surface of the P-body region 4 and has a spacing from the bottom surface of the P-body region 4; that is, the depth of the P-body region 4 is greater than the depth of the NP region 5;

[0065] PP regions 6 are respectively formed in the middle of the JFET region 3 and in the P-body region 4; the PP region 6 in the P-body region 4 extends downward from the top surface of the NP region 5 and is connected thereto; the depth of the PP region 6 is greater than the depth of the NP region 5;

[0066] An ohmic contact layer 7 is formed on the top surface of the PP region 6 in the JFET region 3;

[0067] A gate oxide layer 8 is respectively formed on the top surfaces of the NP region 5, the P-body region 4, and the PP region 6;

[0068] A Poly layer 9 is formed on the top surfaces of the gate oxide layer 8 and the ohmic contact layer 7;

[0069] An isolation dielectric layer 10 wraps the gate oxide layer 8 and the Poly layer 9, the bottom surface is connected to the NP region 5, and the top surface is provided with a front electrode metal layer 12 connected thereto.

[0070] In order to better protect the gate oxide layer of the SiC MOSFET, a heavily doped PP region 6 is formed by ion implantation into the SiC Drift layer 2 at the middle bottom of the device gate, and an ohmic contact 7 is realized through preparation on the top surface of the PP region 6, so that the gate Poly layer is connected to the PP region 6. The benefit of this is that when the gate Poly layer is subjected to the driving voltage, the PP region 6 can release a part of the gate driving voltage stress, thereby reducing the voltage stress on the gate oxide layer and protecting the gate oxide layer to a certain extent. During the blocking process of the device, since the PP region 6 is at the bottom of the gate, it can also shield the electric field concentration generated by the drain voltage and protect the gate oxide layer again.

Claims

1. A SiC VDMOSFET device, characterized in that: It includes a SiC Sub layer (1), a SiC Drift layer (2) and a JFET region (3) which are arranged in sequence from bottom to top; The JFET region (3) is provided with: A P-body region (4) extending downward from a top surface of the JFET region (3); The NP region (5) extends downward from the top surface of the P-body region (4) and is spaced apart from the bottom surface of the P-body region (4); that is, the depth of the P-body region (4) is greater than the depth of the NP region (5); PP regions (6) are formed in the middle of the JFET region (3) and in the P-body region (4) respectively; the PP region (6) in the P-body region (4) extends downward from the top surface of the NP region (5) and is connected thereto; An ohmic contact layer (7) formed on the top surface of the PP region (6) in the JFET region (3); A gate oxide layer (8) is formed on the top surfaces of the NP region (5), the P-body region (4) and the PP region (6) respectively; A Poly layer (9) formed on the top surface of the gate oxide layer (8) and the ohmic contact layer (7); An isolation dielectric layer (10) is wrapped on the gate oxide layer (8) and the Poly layer (9), and the bottom surface is connected to the NP region (5).

2. A SiC VDMOSFET device according to claim 1, characterized in that: The bottom surface depth of the JFET region (3) is 1.2um-2um.

3. A SiC VDMOSFET device according to claim 1, characterized in that: The bottom surface depth of the P-body region (4) is 0.8um-1.2um.

4. A SiC VDMOSFET device according to claim 1, characterized in that: The bottom surface depth of the NP region (5) is 0.3um-0.6um.

5. A SiC VDMOSFET device according to claim 1, characterized in that: The bottom surface depth of the PP region (6) is 0.4um-0.8um.

6. A SiC VDMOSFET device according to claim 1, characterized in that: The ohmic contact layer (7) has a thickness of 0.1 um to 0.5 um.

7. A SiC VDMOSFET device according to claim 1, characterized in that: The gate oxide layer (8) has a thickness of 30 nm to 70 nm.

8. The SiC VDMOSFET device according to claim 1, characterized in that: The thickness of the Poly layer (9) is between 0.5um and 1.2um.

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