Semiconductor device

Abstract

The utility model discloses a semiconductor device, and relates to the technical field of semiconductor devices. The semiconductor device includes a substrate, a stacked structure, and a first capping layer. The stacked structure is arranged on the substrate and comprises an array part and a first step part, and the first step part is provided with a plurality of first step surfaces with the heights gradually decreased in the first direction. The first covering layer is arranged on the stacking structure, covers the array part and exposes the first step part, and the top surface of the first covering layer is higher than the topmost surface of the first step part; in a direction perpendicular to the substrate, the plurality of first stepped surfaces are simultaneously flush with sidewalls of the first capping layer. Therefore, the length ratio or the area ratio of the first step part relative to the array part is effectively reduced, so that the structure of the semiconductor device is more compact and stable, and the optimized operation performance can be achieved.

Description

Technical Field

[0001] The present application relates to a semiconductor device, and in particular to a semiconductor device. Background Art

[0002] Memory plays an indispensable and important role in modern electronic products. In addition to storing user data, memory is also responsible for storing program code executed by the central processing unit and information that needs to be temporarily saved during calculations. Memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory). Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). The data in these volatile memories disappears after power is removed and must be re-entered the next time power is applied. Non-volatile memory includes read-only memory (ROM) and flash memory. The data stored in these memories persists even after power is removed, so previously stored valid data can be directly read after power is restored.

[0003] With advancements in semiconductor manufacturing processes, memory has evolved from a planar structure to a three-dimensional (3D) stacked structure to achieve higher cell density per unit wafer area and meet the demand for higher storage capacity. 3D memory typically includes a staircase structure formed on one or more sides of the memory stack to fan out the wordlines at each layer to electrically connect to interconnect structures (such as wordline contact plugs). However, as the number of memory stack levels increases, the related manufacturing processes and device structures must be further refined to maintain good device performance while simplifying the manufacturing process. Utility Model Content

[0004] The present application aims to provide a semiconductor device in which a stepped portion, to be electrically connected to a plug, is disposed on one side of an array portion. This effectively reduces the length ratio or area ratio of the stepped portion relative to the array portion, thereby making the structure of the semiconductor device more compact and stable, and achieving more optimized operating performance.

[0005] One embodiment of the present application provides a semiconductor device comprising a substrate, a stacked structure, and a first covering layer. The stacked structure is disposed on the substrate and comprises an array portion and a first stepped portion, wherein the first stepped portion has a plurality of first stepped surfaces of gradually decreasing height along a first direction. The first covering layer is disposed on the stacked structure, covering the array portion and exposing the first stepped portion, wherein the bottom surface of the first covering layer is higher than the topmost surface of the first stepped portion. In a direction perpendicular to the substrate, the plurality of first stepped surfaces are simultaneously flush with the sidewalls of the first covering layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of these embodiments and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for ease of illustration and drawing. The same symbols in different embodiments represent corresponding or similar features.

[0007] Figure 1 Illustrated is a top view of a semiconductor device according to the first embodiment of the present application;

[0008] Figure 2 Illustrated is a schematic three-dimensional diagram of a semiconductor device according to the first embodiment of the present application;

[0009] Figure 3 Illustrated is a perspective schematic diagram of a method for manufacturing a semiconductor device after forming a first mask layer according to the first embodiment of the present application;

[0010] Figure 4 Illustrated are other schematic diagrams of the method for manufacturing a semiconductor device after forming a first mask layer according to the first embodiment of the present application;

[0011] Figure 5 Illustrated is a three-dimensional schematic diagram of the method for manufacturing a semiconductor device after performing an etching process according to the first embodiment of the present application;

[0012] Figure 6 Illustrated are other schematic diagrams of the method for manufacturing a semiconductor device according to the first embodiment of the present application after performing an etching process;

[0013] Figure 7 Illustrated is a schematic diagram of the method for manufacturing a semiconductor device after forming a second mask layer according to the first embodiment of the present application;

[0014] Figure 8 Illustrated is a schematic diagram of the method for manufacturing a semiconductor device after trimming the second mask layer according to the first embodiment of the present application;

[0015] Figure 9Illustrated is a schematic diagram of the method for manufacturing a semiconductor device according to the first embodiment of the present application after the second mask layer is trimmed again;

[0016] Figure 10 FIG2 is a schematic diagram of a method for manufacturing a semiconductor device after forming a stepped portion according to the first embodiment of the present application;

[0017] Figure 11 Illustrated is a schematic structural diagram of a semiconductor device according to a second embodiment of the present application;

[0018] Figure 12 Illustrated is a structural schematic diagram of a semiconductor device according to a third embodiment of the present application.

[0019] The description of the accompanying drawings is as follows:

[0020] 10, 30, 40 semiconductor devices

[0021] 100 substrate

[0022] 102 Stop Layer

[0023] 110 stacking structure

[0024] 112 First Step

[0025] 114 Array Department

[0026] 112s first step surface

[0027] 112t top surface

[0028] 112w sidewall

[0029] 114t top surface

[0030] 120 Conductive-dielectric layer pairs

[0031] 122 dielectric layer

[0032] 124 conductive layer

[0033] 130 Etch stop layer

[0034] 130a Etching stop material layer

[0035] 140 First Covering Layer

[0036] 140t top surface

[0037] 150 First Plug

[0038] 150t top surface

[0039] 160 Isolation Layer

[0040] 162 First Isolation Layer

[0041] 164 Second isolation layer

[0042] 166 electrical connectors

[0043] 166t top surface

[0044] 170 first mask layer

[0045] 172 second mask layer

[0046] 212, 312, 412 Second step

[0047] 212s, 312s, 412s second step surface

[0048] 212t, 312t top surface

[0049] 250 Second plug

[0050] 340 Second Covering Layer

[0051] A1 Zone 1

[0052] A2 Zone 2

[0053] A3 Zone 3

[0054] D1 First direction

[0055] D2 Second direction

[0056] D3 vertical direction

[0057] H1, H3, H5 distance

[0058] H2, H4, H6 distance

[0059] L1, L2 length

[0060] R1, R2, R3 gaps

[0061] S1, S3, S5 step surfaces

[0062] S2, S4, S6 step surfaces DETAILED DESCRIPTION

[0063] To help those skilled in the art to which this application relates to further understand this application, several preferred embodiments of this application are listed below, along with the accompanying drawings, to explain in detail the components and intended functions of this application. Those skilled in the art to which this application relates can, without departing from the spirit of this application, refer to the following embodiments and replace, reorganize, or combine the features of the various embodiments to create other embodiments.

[0064] Figures 1 to 2 The diagrams shown are schematic diagrams of a semiconductor device 10 according to an embodiment of the present application, which are respectively a top view and a perspective view of the semiconductor device 10. It should be readily understood by those skilled in the art that in order to clearly present the three-dimensional structure of each component in the semiconductor device 10, Figure 2 Only present Figure 1 The structure of a portion of the semiconductor device 10 is shown.

[0065] Please refer to Figure 1 and Figure 2 As shown, the semiconductor device 10 includes a substrate 100, a stacked structure 110, a plurality of electrical connectors 166, and a first cover layer 140. The substrate 100 is, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate composed of other suitable materials, while the stacked structure 110, the electrical connectors 166, and the first cover layer 140 are respectively disposed on the substrate 100, and the electrical connectors 166 pass through the stacked structure 110 to connect to the substrate 100.

[0066] The stacked structure 110 includes an array portion 114 and a first stepped portion 112 disposed on one side of the array portion 114. The first stepped portion 112 has a plurality of first stepped surfaces 112s with gradually decreasing heights along a first direction D1. In a direction perpendicular to the substrate 100, each first stepped surface 112s is flush with the sidewall of the first cover layer 140. It should be readily understood by those skilled in the art that the height of the first stepped surface 112s refers to the distance from the first stepped surface 112s of each layer to the top surface of the substrate 100. Figure 2 The distance H1 is shown, but is not limited thereto.

[0067] A plurality of electrical connectors 166 are disposed in the array portion 114 of the stacked structure 110, wherein the electrical connectors 166 are sequentially arranged along a first direction D1 and a second direction D2 perpendicular to the first direction D1 so as to be connected to the stacked structure 110. Figure 1 The top view shown shows a memory array.

[0068] It should be noted that the first covering layer 140 is additionally disposed on the stacked structure 110, covering the array portion 114 and exposing the first stepped portion 112, wherein the bottom surface of the first covering layer 140 is higher than the first stepped surface 112s of each layer. In this way, the arrangement of the first covering layer 140 can effectively cover and protect the array portion 114 of the stacked structure 110, and confine the first stepped portion 112 to one side of the array portion 114, significantly reducing the length or area occupied by the first stepped portion 112 in the stacked structure 110, making the structure of the semiconductor device 10 more compact and stable, and achieving more optimized operating performance.

[0069] In one embodiment, a ratio (L1 / L2) of a length L1 of the first stepped portion 112 of the stacked structure 110 in the second direction D2 to a length L2 of the array portion 114 of the stacked structure 110 in the second direction D2 is, for example, approximately 1 / 10 to 1 / 100, and an area ratio of the first stepped portion 112 to the array portion 114 may also be reduced accordingly, but is not limited thereto.

[0070] Specifically, the stacked structure 110 includes multiple dielectric layers 122 and multiple conductive layers 124 alternately stacked in a vertical direction D3 (e.g., a direction perpendicular to the substrate 100), and each conductive layer 124 and the dielectric layer 122 thereon together form a set of conductive-dielectric layer pairs 120, such as Figure 2 That is, the stacked structure 110 includes a plurality of conductive-dielectric layer pairs 120 stacked in sequence, wherein the dielectric layer 122 and each conductive layer 124 in each conductive-dielectric layer pair 120 extend completely across the entire array portion 114 and at least partially extend across the first stepped portion 112. The topmost surface 112t of the first stepped portion 112 is, for example, located at the same level as the top surface 114t of the array portion 114 and is higher than the first stepped surface 112s of each layer.

[0071] In one embodiment, the conductive layer 124 includes, for example, a conductive material such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), doped polysilicon, doped silicon, metal silicide, or any combination thereof. The dielectric layer 122 includes, for example, a dielectric material such as silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), or any combination thereof, but is not limited thereto.

[0072] For example Figure 1 and Figure 2 As shown, the semiconductor device 10 further includes a plurality of first plugs 150 disposed on the first stepped portion 112, and an isolation layer 160 sequentially disposed on the first capping layer 140. Specifically, the first plugs 150 are all disposed on one side of the electrical connector 166 in the second direction D2 and are sequentially arranged in the second direction D2, respectively corresponding to each first stepped surface 112s of the first stepped portion 112. Each first plug 150 is partially disposed in the isolation layer 160 and partially disposed within the first stepped portion 112 of the stacked structure 110. Each first plug 150 penetrates the dielectric layer 122 of a corresponding set of conductive-dielectric layer pairs 120, thereby physically contacting and electrically connecting to the conductive layer 124 of the same conductive-dielectric layer pair 120. On the other hand, each electrical connector 166 has a pillar shape (e.g., a cylindrical shape), and is partially disposed in the isolation layer 160 and partially disposed in the array portion 114 of the stacked structure 110. The electrical connector 166 penetrates the array portion 114 and is electrically connected to a plug (not shown) or a conductive structure (not shown) disposed in the substrate 100. Thus, the top surface 140t of the first cover layer 140 is lower than the top surface 150t of the first plug 150 or the top surface 166t of the electrical connector 166.

[0073] In one embodiment, each first plug 150 and each electrical connector 166 comprises, for example, a conductive material, such as a low-resistance metal conductive material such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, or copper, preferably tungsten, but not limited thereto. In another embodiment, the isolation layer 160 comprises, for example, a first isolation layer 162 and a second isolation layer 164 stacked in sequence, wherein the first isolation layer 162 and the second isolation layer 164 each comprise, for example, a dielectric material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0074] In addition, a pad layer (not shown) and a stop layer 102 may be additionally provided between the substrate 100 and the stacked structure 110, wherein the pad layer may include, for example, a material such as silicon oxide, and the stop layer 102 may include, for example, a dielectric material having etching selectivity with the dielectric layer 122 and the pad layer, such as aluminum oxide (Al2O3), but is not limited thereto.

[0075] Furthermore, in another embodiment, the stacked structure 110 of the semiconductor device 10 may further include a second stepped portion 212 also disposed on one side of the array portion 114. The semiconductor device 10 may additionally include an etch stop layer 130 disposed between the second stepped portion 212 and the first stepped portion 112 in the vertical direction D3, and a plurality of second plugs 250 disposed on the second stepped portion 212. Specifically, the second stepped portion 212 is, for example, disposed adjacent to the first stepped portion 112 and similarly exposed from the first cover layer 140, and has a plurality of second stepped surfaces 212s with gradually decreasing heights along the first direction D1. The topmost surface 212t of the second stepped portion 212 is, for example, located at the same level as the bottom surface of the etch stop layer 130 and is significantly lower than the bottom surface of the first cover layer 140, the top surface 114t of the array portion 114, or the topmost surface 112t of the first stepped portion 112. Those skilled in the art will readily understand that the height of the second stepped surface 212s refers to the distance from the second stepped surface 212s of each layer to the top surface of the substrate 100. Figure 2 The distance H2 is shown, but is not limited thereto.

[0076] On the other hand, the etch stop layer 130 is disposed within the stacked structure 110 and has sidewalls that are flush with the first stepped portion 112, such that the second stepped portion 212 is exposed from the etch stop layer 130. The etch stop layer 130 may comprise, for example, a dielectric material having etching selectivity with the dielectric layer 122 and the liner layer, such as aluminum oxide, but is not limited thereto.

[0077] The second plug 250 is arranged on one side of the electrical connector 166 in the second direction D2, adjacent to the first plug 150, and arranged in sequence in the second direction D2, and respectively aligned with each second step surface 212s of the second step portion 212. Each second plug 250 is also partially arranged in the isolation layer 160 and partially arranged in the second step portion 212 of the stacked structure 110, respectively penetrating the dielectric layer 122 in a corresponding group of conductive-dielectric layer pairs 120, and physically contacting and electrically connecting to the conductive layer 124 in the same group of conductive-dielectric layer pairs 120. In one embodiment, each second plug 250, for example, also includes a conductive material, such as a low-resistance metal conductive material such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, etc., preferably including tungsten, but not limited thereto. It should be noted that each second step surface 212s is, for example, arranged in alignment with each adjacent first step surface 112s in the second direction D2, such as Figure 2 As shown, each second plug 250 is staggered with each adjacent first plug 150 in the second direction D2, as shown in FIG. Figure 1As shown, a relatively sufficient process window is reserved for both the second plug 250 and the first plug 150 in subsequent manufacturing processes.

[0078] Because the first stepped portion 112 and / or the second stepped portion 212 of this embodiment are confined to one side of the array portion 114, the first plugs 150 and / or the second plugs 250 are also confined to one side of the array portion 114. This significantly reduces the length or area occupied by the first stepped portion 112 and / or the second stepped portion 212 in the stacked structure 110, making the semiconductor device 10 more compact and stable. Furthermore, because the first stepped portion 112 and the second stepped portion 212 of this embodiment are respectively disposed above and below the etch stop layer 130, each first plug 150 and each second plug 250 can alternately fan out from different regions on each first stepped surface 112s and each second stepped surface 212s, thereby avoiding compressing the fabrication space for the first plugs 150 and the second plug 250. This results in a more reliable device structure and optimized operating performance for the semiconductor device 10 of this embodiment.

[0079] However, those skilled in the art will readily understand that although the semiconductor device 10 of the aforementioned embodiment is described as having both the first stepped portion 112 and the second stepped portion 212 disposed on one side of the array portion 114 as an implementation aspect, the present invention is not limited thereto. Depending on actual device requirements, the first stepped portion 112 or the second stepped portion 212 may be disposed only on one side of the array portion 114, and the etch stop layer 130 may be omitted. In order to enable those skilled in the art to implement the semiconductor device 10 of the aforementioned embodiment of the present application, a method for fabricating the semiconductor device 10 is further described below.

[0080] Please refer to Figures 3 to 10 , which is a schematic diagram of the steps of the manufacturing method of the semiconductor device 10 according to the first embodiment of the present application, wherein, Figure 3 and Figure 5 is a three-dimensional schematic diagram of the semiconductor device 10 at different manufacturing stages, and the remaining figures are top-view schematic diagrams and cross-sectional schematic diagrams of the semiconductor device 10 at different manufacturing stages.

[0081] First, if Figure 3 and Figure 4As shown, a substrate 100 is provided, and a stop layer 102, a plurality of alternating dielectric layers 122 and conductive layers 124, an etch-stop material layer 130a, a plurality of alternating dielectric layers 122 and conductive layers 124, and a first capping layer 140 are sequentially formed on the substrate 100. Each conductive layer 124 and the dielectric layer 122 above it together form a set of conductive-dielectric layer pairs 120. Preferably, the number of dielectric layers 122 and conductive layers 124 stacked above and below the etch-stop material layer 130a is the same, and the number of conductive-dielectric layer pairs 120 disposed above and below the etch-stop material layer 130a is also the same, but this is not limiting. Next, a first mask layer 170 is formed on the first capping layer 140. In one embodiment, the first mask layer 170 comprises, for example, a photoresist material or other suitable material, but this is not limiting.

[0082] Those skilled in the art should be able to easily understand that Figure 4 1 is a schematic top view of the semiconductor device 10 of this embodiment after the first mask layer 170 is formed, and a schematic cross-sectional view along the cut line A-A' and the cut line BB'. It should be noted that the first covering layer 140 completely covers the second area A2 of the substrate 100, while exposing the first area A1 of the substrate 100, and the first mask layer 170 completely covers the second area A2 and a portion of the first area A1 of the substrate 100, while exposing the third area A3 of the substrate 100 (i.e., the portion of the first area A1 not covered by the first mask layer 170). Figure 3 and Figure 4 In one embodiment, the second area A2 and the first area A1 of the substrate 100 are disposed adjacent to each other in the second direction D2, for example. Figure 3 and Figure 4 As shown, but not limited thereto, in another embodiment, the first area A1 may be disposed on the other side of the second area A2 in the second direction D2 or on one side in the second direction D2 according to actual device requirements.

[0083] like Figure 5 and Figure 6 As shown, an etching process is performed with the aid of the first mask layer 170, such as a dry etching process or a wet etching process, to remove the dielectric layer 122 and the conductive layer 124 exposed from the first mask layer 170, that is, to remove the dielectric layer 122 and the conductive layer 124 located in the third area A3 of the substrate 100. It should be easily understood by those skilled in the art that Figure 61 is a schematic top view of the semiconductor device 10 of the present embodiment after the etching process and a schematic cross-sectional view thereof along the cut line A-A' and the cut line BB'. It should be noted that the etching process uses the etching stop material layer 130a as the etching stop layer. For this reason, the dielectric layer 122 and the conductive layer 124 located above the etching stop material layer 130a and within the third area A3 and exposed from the first mask layer 170 are completely removed. In addition, the etching stop material layer 130a is also partially removed to form the etching stop layer 130 whose sidewalls are flush with the first mask layer 170, as shown in FIG. Figure 5 and Figure 6 Then, the first mask layer 170 is completely removed.

[0084] like Figure 7 As shown, a second mask layer 172 is formed on the first cover layer 140, and then a first etching process is performed with the aid of the second mask layer 172, such as a dry etching process or a wet etching process. Figure 7 1 is a schematic top view of the semiconductor device 10 of this embodiment after the first etching process and a schematic cross-sectional view along the cut line A-A', the cut line B-B' and the cut line C-C'. It should be noted that the second mask layer 172 completely covers the second area A2 and most of the first area A1 of the substrate 100, and only the gap R1 of the second mask layer 172 exposes part of the first area A1 and part of the third area A3. The gap R1 is, for example, as shown in FIG. Figure 7 The rectangular opening shown is preferably located at Figure 7 The second mask layer 172 is shown as a corner thereof, but the present invention is not limited thereto. In this way, the dielectric layer 122 and the conductive layer 124 located on one side of the first area A1 and the third area A3 in the second direction D2 are exposed from the second mask layer 172. The dielectric layer 122 exposed from the notch R1 in the third area A3 is located below the etch stop layer 130, while the dielectric layer 122 exposed from the notch R1 in the first area A1 outside the third area A3 is located above the etch stop layer 130. Figure 7, as shown in a cross-sectional schematic diagram. Then, a first etching process is performed to simultaneously remove the conductive-dielectric layer pair 120 within the third area A3 and the conductive-dielectric layer pair 120 within the first area A1 outside the third area A3 from the gap R1. This forms a stepped surface S2 below the etch-stop layer 130 within the third area A3, and a stepped surface S1 above the etch-stop layer 130 within the first area A1 outside the third area A3. The height of the stepped surface S2 in the vertical direction D3 is lower than the bottom surface of the etch-stop layer 130, while the height of the stepped surface S1 in the vertical direction D3 is lower than the bottom surface of the first capping layer 140. In one embodiment, the second mask layer 172 comprises, for example, but not limited to, a photoresist material or other suitable materials.

[0085] like Figure 8 As shown, a trim-etching process is performed. First, the second mask layer 172 is trimmed, for example, by using a dry etching process or a wet etching process to further expand the size of the aforementioned gap R1 to form a gap R2, and then a second etching process is performed using the trimmed second mask layer 172. It should be easily understood by those skilled in the art that Figure 8 1 and 2 show a schematic top view of the semiconductor device 10 after the trim-etch process and a schematic cross-sectional view along the cutting line AA′, the cutting line BB′ and the cutting line CC′ of the semiconductor device 10 according to the present embodiment.

[0086] It should be noted that the enlarged size of the gap R1 refers to, for example, the enlarged length of the gap R1 in the first direction D1 and / or the second direction D2. Preferably, the length of the gap R1 in the first direction D1 and the second direction D2 is enlarged at the same time, so that the gap R2 has a length greater than the gap R1 in both the first direction D1 and the second direction D2. Figure 8 . Furthermore, during the trimming process, the thickness of the second mask layer 172 is also relatively reduced. Thus, the stepped surface S2 formed within the third area A3 and a portion of the dielectric layer 122 within the third area A3 are fully exposed from the notch R2. The stepped surface S1 formed within the first area A1 outside the third area A3 and a portion of the dielectric layer 122 within the first area A1 outside the third area A3 are also fully exposed. Furthermore, the first capping layer 140 is also partially exposed, but the present invention is not limited thereto.

[0087] The second etching process simultaneously removes the conductive-dielectric layer pair 120 downward from the dielectric layer 122 exposed by the notch R2 and the step surfaces S1 and S2, further forming a step surface S4 below the etch stop layer 130 in the third area A3, and a step surface S3 above the etch stop layer 130 in the first area A1 outside the third area A3. Furthermore, the heights of the step surfaces S1 and S2 decrease further downward. It should be noted that because the portion exposed by the notch R2 is covered by the first capping layer 140, the formation of the step surfaces S1, S2, S3, and S4 is confined to the first area A1, thereby enabling more efficient control over the formation range and position of the step surfaces S1, S2, S3, and S4.

[0088] like Figure 9 As shown, the trimming-etching process is performed again. First, the second mask layer 172 is trimmed again, for example, by using a dry etching process or a wet etching process to further expand the size of the aforementioned gap R2 to form a gap R3, and then a third etching process is performed to remove the portion exposed by the gap R3. It should be easily understood by those skilled in the art that Figure 9 1 and 2 show a schematic top view of the semiconductor device 10 after the trim-etch process and a schematic cross-sectional view along the cutting line AA′, the cutting line BB′ and the cutting line CC′ of the semiconductor device 10 according to the present embodiment.

[0089] It should be noted that the enlarged size of the gap R2 refers to, for example, the enlarged length of the gap R2 in the first direction D1 and / or the second direction D2. Preferably, only the length of the gap R2 in the first direction D1 is enlarged, so that the gap R3 has a length greater than the gap R2 in the second direction D2, such as Figure 9. As shown in the top view of FIG. Thus, the step surfaces S2 and S4 formed within the third area A3 and a portion of the dielectric layer 122 within the third area A3 are completely exposed through the notch R3. The step surfaces S1 and S3 formed within the first area A1 outside the third area A3 and a portion of the dielectric layer 122 within the first area A1 outside the third area A3 are also completely exposed. The first capping layer 140 is also partially exposed, but the present invention is not limited thereto. The third etching process simultaneously removes the conductive-dielectric layer pair 120 downward from the dielectric layer 122 and the step surfaces S1, S2, S3, and S4 exposed by the notch R3. This further forms a step surface S6 below the etch stop layer 130 within the third area A3 and a step surface S5 above the etch stop layer 130 within the first area A1 outside the third area A3. Furthermore, the heights of the step surfaces S1, S2, S3, and S4 decrease downward again. It should be noted that, since the portion exposed by the notch R3 is still covered by the first covering layer 140 , the stepped surfaces S1 , S2 , S3 , S4 , S5 , and S6 are only formed in the first area A1 .

[0090] In this way, after repeating the aforementioned trimming-etching process, the second mask layer 172 is completely removed, and new stepped surfaces can be gradually formed in the third area A3 and in the first area A1 outside the third area A3, and the heights of the stepped surfaces S1, S2, S3, S4, S5, and S6 formed above are further reduced. Finally, a plurality of second stepped surfaces 212s with gradually decreasing heights along the first direction D1 are formed in the third area A3, and a plurality of first stepped surfaces 112s with gradually decreasing heights along the first direction D1 are formed in the first area A1 outside the third area A3. The second area A2 covered by the first covering layer 140 can be used as the subsequent array portion 114, forming the following. Figure 10 The stacked structure 110 shown in FIG. Figure 10Also shown are a schematic top view of the semiconductor device 10 of this embodiment after repeated trim-etching processes and schematic cross-sectional views along the cut lines A-A', B-B', and C-C'. Specifically, the first stepped portion 112 and the second stepped portion 212 are adjacent to each other and are both formed on one side of the array portion 114. The first stepped surface 112s of each layer in the first stepped portion 112 is significantly lower than the bottom surface of the first cover layer 140. In a direction perpendicular to the substrate (i.e., in a top view), each first stepped surface 112s is flush with the sidewall of the first cover layer 140, and the distances H5, H3, and H1 from the first stepped surface 112s of each layer to the top surface of the substrate 100 gradually decrease in the first direction D1. The second stepped surface 212s of each layer in the second stepped portion 212 is also lower than the top surface 114t of the array portion 114, or lower than the bottom surface of the etch stop layer 130, and the distances H6, H4, and H2 from the second stepped surface 212s of each layer to the top surface of the substrate 100 also gradually decrease in the first direction D1.

[0091] Subsequently, an isolation layer 160 (including a first isolation layer 162 and a second isolation layer 164 stacked in sequence) may be further formed on the stacked structure 110, an electrical connection member 166 may be formed in the array portion 114 along the first direction D1 and the second direction D2, and a first plug 150 and a second plug 250 may be formed on the first step portion 112 and the second step portion 212, respectively, to form a stacked structure 110. Figure 1 and Figure 2 The semiconductor device 10 is shown.

[0092] With this operation, the fabrication of the semiconductor device 10 of this embodiment is completed. It should be noted that because the first capping layer 140 is pre-formed on the alternating multi-layer dielectric layer 122 and multi-layer conductive layer 124 to pre-define the array portion 114 of the stacked structure 110, the subsequent trim-etching process will also be affected by the coverage of the first capping layer 140 and will be confined to the first area A1 exposed outside the first capping layer 140. In other words, the first capping layer 140 can effectively protect the pre-defined array portion 114 from being subjected to the trim-etching process, so that the trim-etching process will only simultaneously etch the pre-defined first step portion 112 and / or second step portion 212 to form the step surfaces S1, S3, S5 and the step surfaces S2, S4, S6. As a result, the first stepped portion 112 and / or the second stepped portion 212 can be formed only on one side of the array portion 114, and the locations of the subsequently formed first plugs 150 and / or second plugs 250 can also be correspondingly limited to one side of the array portion 114. This significantly reduces the length or area occupied by the first stepped portion 112 and / or the second stepped portion 212 in the stacked structure 110, resulting in a more compact and stable structure for the semiconductor device 10 and achieving more optimized operating performance. Furthermore, because the first stepped portion 112 and the second stepped portion 212 of this embodiment are respectively disposed above and below the etch stop layer 130, the subsequently formed first plugs 150 and second plugs 250 can alternately fan out from different regions on the first stepped surface 112s and the second stepped surface 212s, thereby avoiding compression in the fabrication space for the first plugs 150 and second plugs 250 and providing a more reliable device structure.

[0093] Please refer to Figure 11 As shown, Figure 11 : This is a cross-sectional schematic diagram of a semiconductor device 30 according to a second embodiment of the present application. The structure and manufacturing method of the semiconductor device 30 according to this embodiment are generally the same as the structure and manufacturing method of the semiconductor device 10 according to the first embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 30 according to this embodiment and the aforementioned semiconductor device 10 is that it also includes a second covering layer 340 additionally disposed above the first covering layer 140, covering the top surface 140t of the first covering layer 140, the topmost surface 112t and multiple sidewalls 112w of the first stepped portion 112, and the first stepped surfaces 112s of each layer, and exposing the second stepped portion 312 of this embodiment.

[0094] In detail, the second stepped portion 312 of the present embodiment is also arranged adjacent to the first stepped portion 112, and has a plurality of second stepped surfaces 312s of gradually decreasing height along the first direction D1. In the direction perpendicular to the substrate, each second stepped surface 312s is flush with the sidewall of the second covering layer 340. Moreover, the topmost surface 312t of the second stepped portion 312 is, for example, also at the same horizontal height as the bottom surface of the etching stop layer 130, and is significantly lower than the top surface 114t of the array portion 114 or the topmost surface 112t of the first stepped portion 112. It should be noted that the second stepped portion 312 is made, for example, by forming the second covering layer 340 on the first covering layer 140 after the first stepped portion 112 is formed, thereby defining the formation area of ​​the second stepped portion 312 (i.e., Figure 5 Then, another mask layer (not shown) with a notch (not shown) is formed on the second cover layer 340, and an etching process and a trim-etching process are repeated under the cover of the other mask layer and the second cover layer 340 until the second stepped portion 312 of this embodiment is formed. In this operation, each of the formed second stepped surfaces 312s is preferably offset from each of the adjacent first stepped surfaces 112s in the second direction D2, as shown in FIG. Figure 11 As shown, each second plug 250 disposed on each second stepped surface 312s is also staggered relative to the adjacent first plugs 150 in the second direction D2, further improving the manufacturing space between the second plugs 250 and the first plugs 150 in subsequent manufacturing processes. Furthermore, because the second cover layer 340 also covers the topmost surface 112t and sidewalls 112w of the first stepped portion 112, it can provide additional protection for the first stepped portion 112 during the fabrication of the second stepped portion 312. Each second plug 250 penetrates the second cover layer 340 covering each first stepped surface 112s and contacts the corresponding conductive layer 124.

[0095] Since the present embodiment performs a two-stage trim-etching process on the first cover layer 140 and the second cover layer 340, the first step portion 112 and the second step portion 312 formed in the two-stage trim-etching process can have other configurations, not limited to the aforementioned configurations. For example, the step portions formed in the two-stage trim-etching process can be formed on opposite sides of the array portion 114, or the step surfaces formed in the two-stage trim-etching process can have gradually increasing heights along different directions, or the step surfaces can have different sizes, etc., but the present invention is not limited thereto.

[0096] According to the semiconductor device 30 of this embodiment, the first stepped portion 112 and / or the second stepped portion 312 are still confined to the same side of the array portion 114, so that the first plug 150 and / or the second plug 250 can still be located on the same side of the array portion 114, thereby providing relatively sufficient manufacturing space. As a result, in the semiconductor device 30 of this embodiment, the length or area occupied by the first stepped portion 112 and / or the second stepped portion 312 in the stacked structure 110 can be significantly reduced, further improving the manufacturing space for the first plug 150 and the second plug 250. This makes the semiconductor device 30 of this embodiment have a more reliable component structure and achieves more optimized operating performance.

[0097] Please refer to Figure 12 As shown, Figure 12 This is a cross-sectional schematic diagram of a semiconductor device 40 according to a third embodiment of the present application. The structure and fabrication method of the semiconductor device 40 according to this embodiment are substantially the same as those of the semiconductor device 20 according to the second embodiment, and the similarities are not further described here. The main difference between the semiconductor device 40 according to this embodiment and the aforementioned semiconductor device 30 is that the second stepped portion 412 according to this embodiment has a plurality of second stepped surfaces 412s with gradually increasing heights along the first direction D1.

[0098] Specifically, the second stepped portion 412 of this embodiment is also disposed adjacent to the first stepped portion 112, and is also formed by performing an etching process and a repeated trim-etching process under the cover of another mask layer and the second cover layer 340 after the first stepped portion 112 is formed. However, in this embodiment, the notch (not shown) on the other mask layer is formed at another corner of the other mask layer, so that the distances H2, H4, and H6 between the second stepped surface 412s of each layer in the second stepped portion 412 and the top surface of the substrate 100 gradually increase in the first direction D1, and are also staggered with the adjacent first stepped surfaces 112s, as shown in FIG. Figure 12 As shown. In this arrangement, each second plug 250 disposed on each second stepped surface 412s is also offset relative to the adjacent first plugs 150 in the second direction D2, thereby increasing the manufacturing space for the second plugs 250 and first plugs 150 in subsequent manufacturing processes. Furthermore, the second cover layer 340 can also provide additional protection for the first stepped portion 112 during the fabrication of the second stepped portion 412. Each second plug 250 penetrates the second cover layer 340 covering each first stepped surface 112s and contacts the corresponding conductive layer 124.

[0099] According to the semiconductor device 40 of this embodiment, the first stepped portion 112 and / or the second stepped portion 412 are still confined to the same side of the array portion 114, so that the first plug 150 and / or the second plug 250 can still be located on the same side of the array portion 114, thereby providing relatively sufficient manufacturing space. As a result, in the semiconductor device 40 of this embodiment, the length or area occupied by the first stepped portion 112 and / or the second stepped portion 412 in the stacked structure 110 can be significantly reduced, further improving the manufacturing space for the first plug 150 and the second plug 250. This makes the semiconductor device 40 of this embodiment have a more reliable component structure and achieves more optimized operating performance.

[0100] In general, the present application uses an additional covering layer to pre-define the arrangement positions of the array portion and the stepped portion of the stacked structure on the alternating dielectric layers and conductive layers. As a result, the covering layer can be used to further limit the area etched by the etching process and / or the trim-etching process in the subsequent processes. Therefore, the manufacturing method of the present application can significantly reduce the length or area occupied by the stepped portion in the formed stacked structure by providing the covering layer, so that the formed semiconductor device has a more compact and stable structure and can achieve more optimized operating performance. In addition, the plugs manufactured subsequently can also choose to fan out alternately from different areas of the stepped portion in sequence, thereby improving the manufacturing space of the plugs and forming a more reliable component structure. In this way, the semiconductor device of the present application can obtain more optimized structural integrity and enhance its component performance.

[0101] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0102] It should be noted that references in this specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; a stacked structure, disposed on the substrate, comprising an array portion and a first stepped portion, wherein the first stepped portion has a plurality of first stepped surfaces with gradually decreasing heights along a first direction; as well as a first covering layer, disposed on the stacked structure, covering the array portion and exposing the first stepped portion, wherein a top surface of the first covering layer is higher than a topmost surface of the first stepped portion; In a direction perpendicular to the substrate, the plurality of first step surfaces are simultaneously flush with sidewalls of the first covering layer.

2. The semiconductor device according to claim 1, wherein The stacked structure includes a plurality of conductive-dielectric layer pairs sequentially arranged in a vertical direction, and the semiconductor device further includes: a plurality of first plugs disposed on the first stepped portion and electrically connected to portions of the conductive layers of the conductive-dielectric layer pair; and An isolation layer covers the first covering layer and the topmost surface of the first stepped portion.

3. The semiconductor device according to claim 2, wherein The stacked structure further includes a second stepped portion having a plurality of second stepped surfaces with gradually decreasing heights along the first direction.

4. The semiconductor device according to claim 3, wherein Each of the second stepped surfaces and each of the first stepped surfaces are staggered with each other in a second direction, and the second direction is perpendicular to the first direction.

5. The semiconductor device according to claim 4, wherein Also includes: The second covering layer is disposed above the first covering layer, covers the top surface of the first covering layer, the topmost surface and a plurality of sidewalls of the first stepped portion, and exposes the second stepped portion.

6. The semiconductor device according to claim 2, wherein Also includes: a second stepped portion, disposed in the stacked structure and having a plurality of second stepped surfaces with gradually increasing heights along the first direction; An etch stop layer is disposed on the substrate and is located between the first stepped portion and the second stepped portion in the vertical direction; as well as The second covering layer is disposed above the first covering layer, covers the top surface of the first covering layer, the topmost surface and a plurality of sidewalls of the first stepped portion, and exposes the second stepped portion.

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