Equivalent impedance test circuit of chip
The test circuit, composed of a reference chip and an error amplifier, solves the problem of insufficient measurement accuracy of resistance, capacitance, and inductance in chip integration testing, and realizes fast and accurate equivalent impedance measurement, which is suitable for integrated circuits.
Patent Information
- Application Number
- CN202423097833.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2034-12-16
Smart Images
Figure CN223784429U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to chip test technical field, specifically, relate to a kind of equivalent impedance test circuit of chip. BACKGROUND
[0002] With the improvement of the requirement of chip integration, some components (such as inductance, capacitance, etc.) and chips are often packaged together, and the quality of such components is ensured only by measuring the test of their own and parasitic parameters. For example, in some application scenarios, the inductance reactance, capacitance reactance, inductance DC resistance DCR, capacitance equivalent series resistance ESR, or line impedance, capacitance reactance and / or inductance value, etc. need to be measured.
[0003] The resistance measurement circuit often uses a series circuit test (such as shown in Figure 1 ), and the measurement of capacitance reactance and inductance reactance often needs to build an oscillation circuit (such as shown in Figure 2 and Figure 3 ), or use a special RLC measuring instrument for testing. The precision of the conventional resistance measurement circuit cannot meet the measurement precision of the parasitic resistance, and the oscillation circuit test method for inductance reactance and capacitance reactance is relatively complex and easy to introduce errors. The LCR measuring instrument is heavy and not conducive to integration, and all of the three have certain limitations in integrated circuit testing and measurement. How to design a circuit to quickly and accurately measure the resistance, capacitance and inductance value is a problem to be solved at present. UTILITY MODEL CONTENT
[0004] The utility model aims at at least solving one of the above-mentioned technical problems in the prior art.
[0005] Therefore, the utility model provides an equivalent impedance test circuit of chip.
[0006] The equivalent impedance test circuit of chip provided by the utility model is used for testing the equivalent impedance between the first pin and the second pin of the to-be-tested chip, and the test circuit comprises a reference chip, a first error amplifier, a second error amplifier, a third error amplifier and a parameter calculation module.
[0007] The reference chip has a first pin and a second pin, and the reference chip is a chip of the same model as the to-be-tested chip and each parameter test is qualified. The first pin of the reference chip corresponds to the first pin of the to-be-tested chip, the second pin of the reference chip corresponds to the second pin of the to-be-tested chip, the first pin of the reference chip is coupled to the first end of the excitation source, the second pin of the reference chip is coupled to the first pin of the to-be-tested chip, and the second pin of the to-be-tested chip is coupled to the second end of the excitation source.
[0008] The first error amplifier has a first input end, a second input end and an output end, the first input end of the first error amplifier is coupled with the first pin of the reference chip, the second input end of the first error amplifier is coupled with the second pin of the reference chip, and the signal difference between the first pin and the second pin of the reference chip is collected through the first error amplifier.
[0009] The third error amplifier has a first input end, a second input end and an output end, the first input end of the third error amplifier is coupled with the output end of the first error amplifier, the second input end of the third error amplifier is coupled with the output end of the second error amplifier, and the output end of the third error amplifier provides a difference amplification signal, the difference amplification signal is used for representing the difference between the signal difference collected by the first error amplifier and the signal difference collected by the second error amplifier, and has a corresponding relationship with the equivalent impedance between the first pin and the second pin of the to-be-tested chip.
[0010] The parameter calculation module receives the difference amplification signal and calculates the equivalent impedance between the first pin and the second pin of the to-be-tested chip according to the difference amplification signal.
[0011] In summary, due to the adoption of the above technical features, the chip equivalent impedance test circuit and method have the following beneficial effects:
[0012] The chip equivalent impedance test circuit and method can quickly and accurately measure the equivalent impedance of the to-be-tested chip, and further reflect the resistance, capacitance and inductance values of the to-be-tested chip, and can measure resistive devices, inductive devices and capacitive devices based on the same test circuit. The reference chip is taken as a reference to obtain the error between the measurement signal of the to-be-tested chip and the measurement signal of the reference chip, and then the equivalent impedance of the to-be-tested chip is directly solved through the corresponding relationship between the error and the equivalent impedance of the to-be-tested chip. The measurement precision of the present disclosure is high, the circuit structure is simple and easy to implement, and is particularly suitable for integrated circuit measurement and test.
[0013] The additional aspects and advantages of the present application will become apparent from the following description with reference to the accompanying drawings, or can be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS
[0014] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, with reference to the following drawings, in which:
[0015] Figure 1 is a schematic structural diagram of a traditional chip resistance measurement circuit;
[0016] Figure 2 is a schematic diagram of a traditional chip capacitance reactance measurement circuit structure;
[0017] Figure 3 is a schematic diagram of a traditional chip inductance reactance measurement circuit structure;
[0018] Figure 4 is a circuit schematic diagram of an equivalent impedance test circuit of a chip according to an embodiment of the present application;
[0019] Figure 5 is a schematic diagram of a to-be-tested chip according to an embodiment of the present application.
[0020] wherein, Figures 1 to 5 the correspondence between the reference signs and the component names in the accompanying drawings is as follows:
[0021] 1, chip tester; 11, parameter calculation module; 12, abnormality indication module; 13, excitation signal transmission line; 14, data signal transmission line; 21, to-be-tested chip; 22, reference chip;
[0022] 211, control circuit. DETAILED DESCRIPTION
[0023] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The use of the terms "including," "containing," or "comprising" throughout this specification means "comprising" in the sense of non-limiting inclusion such that the
[0024] An equivalent impedance test circuit and method of a chip according to some embodiments of the application will be described below with reference to Figure 4 and Figure 5 .
[0025] Some embodiments of the application provide an equivalent impedance test circuit of a chip.
[0026] As shown in Figure 4 , the first embodiment of the application provides an equivalent impedance test circuit of a chip for testing the equivalent impedance between the first pin and the second pin of a to-be-tested chip 21, which at least comprises: a reference chip 22, a first error amplifier API, a second error amplifier AP2, a third error amplifier AP3, and a parameter calculation module 11.
[0027] The reference chip 22 has a first pin and a second pin. The reference chip 22 is a chip of the same type as the to-be-tested chip 21 and each phase parameter test is qualified. The first pin a1 of the reference chip 22 corresponds to the first pin a2 of the to-be-tested chip 21, and the second pin b1 of the reference chip 22 corresponds to the second pin b2 of the to-be-tested chip 21. The first pin a1 of the reference chip 22 is coupled to the first end of the excitation source, the second pin b1 of the reference chip 22 is coupled to the first pin a2 of the to-be-tested chip 21, and the second pin b2 of the to-be-tested chip 21 is coupled to the second end of the excitation source.
[0028] Specifically, the reference chip 22 and the to-be-tested chip 21 are the same chips of the same type. Generally, the reference chip 22 is a chip that has passed the test and has no problem, and the equivalent impedance of the parameters and the parasitic parameters between the pins has been obtained. The pin correspondence relationship of the reference chip 22 and the to-be-tested chip 21 can be understood as that the pins of the same function and the same structure are one-to-one corresponding. For example, when the first pin a1 of the reference chip 22 is an input pin, the first pin a2 of the to-be-tested chip 21 is also an input pin. When the second pin b1 of the reference chip 22 is a ground pin, the second pin b2 of the to-be-tested chip 21 is also a ground pin.
[0029] That is to say, the signal collected by the reference chip 22 can represent the signal of a qualified chip, and the equivalent impedance between the two pins of the reference chip 22 represents the equivalent impedance between the two pins of a qualified chip. In some embodiments, a chip classified as BIN1 by ATE (i.e., a qualified chip) can be selected as the reference chip 22, and the equivalent impedance of the parameters and the parasitic parameters between the pins of the single qualified chip is measured by an LCR meter to obtain the reference value.
[0030] In the present disclosure, the reference chip 22 and the to-be-tested chip 21 are connected in series under the same excitation source based on the reference chip 22. The excitation source includes a direct current source or an alternating current source. Specifically, the excitation source can be a direct current source, a direct voltage source, an alternating current source or an alternating voltage source. In some embodiments, the excitation source is provided by the chip tester 1, and the excitation source of the chip tester 1 is coupled to the reference chip 22 and the to-be-tested chip 21 through the excitation signal transmission line 13.
[0031] After the excitation source is applied, the difference amplification signal between the two chips is obtained through the first error amplifier AP1, the second error amplifier AP2 and the third error amplifier AP3. Specifically, the first error amplifier AP1 has a first input end, a second input end and an output end, the first input end of the first error amplifier AP1 is coupled to the first pin a1 of the reference chip 22, the second input end of the first error amplifier AP1 is coupled to the second pin b1 of the reference chip 22, and the signal difference between the first pin and the second pin of the reference chip 22 is collected and amplified through the first error amplifier AP1. The second error amplifier AP2 has a first input end, a second input end and an output end, the first input end of the second error amplifier AP2 is coupled to the first pin a2 of the to-be-tested chip 21, the second input end of the second error amplifier AP2 is coupled to the second pin b2 of the to-be-tested chip 21, and the signal difference between the first pin and the second pin of the to-be-tested chip 21 is collected and amplified through the second error amplifier AP2.
[0032] The third error amplifier AP3 has a first input end, a second input end and an output end, the first input end of the third error amplifier AP3 is coupled to the output end of the first error amplifier AP1, the second input end of the third error amplifier AP3 is coupled to the output end of the second error amplifier AP2, and the output end of the third error amplifier AP3 provides a difference amplification signal, which is used to represent the difference between the signal difference collected and amplified by the first error amplifier AP1 and the signal difference collected and amplified by the second error amplifier AP2.
[0033] In Figure 4 In the embodiment shown, the first input end of each error amplifier is shown as the non-inverting input end of the error amplifier, and the second input end of each error amplifier is shown as the inverting input end of the error amplifier. It can be understood that this setting is only illustrative in the embodiment of the present disclosure, and a person skilled in the art can make flexible choices as needed.
[0034] The parameter calculation module 11 receives the difference amplification signal and calculates the equivalent impedance between the first pin and the second pin of the to-be-tested chip 21 according to the difference amplification signal. It should be noted that in some cases, the finally measured equivalent impedance may include line impedance, capacitive reactance and inductive reactance, which is generally related to the circuit state inside the chip. In the case where the circuit state is controllable or known, the specific composition of the measured equivalent impedance value can be known.
[0035] In Figure 4 In the embodiment shown, the difference amplification signal and the equivalent impedance between the first pin and the second pin of the to-be-tested chip 21 have the following relationship:
[0036]
[0037] Wherein, VR represents the difference value amplification signal, A1 represents the amplification multiple of the first error amplifier AP1, I represents the excitation current provided by the excitation source, Z1 represents the equivalent impedance between the first pin and the second pin of the reference chip 22, A2 represents the amplification multiple of the second error amplifier AP2, Z2 represents the equivalent impedance between the first pin and the second pin of the chip under test 21, and A3 represents the amplification multiple of the third error amplifier AP3.
[0038] According to the above relationship, it can be determined that the calculation method of Z2 is as follows:
[0039]
[0040] Wherein, A1, A2, A3, I and Z1 are known quantities, and after obtaining the measured value of VR, the equivalent impedance Z2 between the first pin and the second pin of the chip under test 21 can be calculated. It can be understood that the above calculation method can be known by those skilled in the art according to the circuit structure proposed by the present disclosure, without the need for additional derivation and calculation, that is, the above calculation method is determined by the circuit structure provided by the present disclosure.
[0041] In some embodiments, the parameter calculation module 11 is arranged in the chip tester 1, and the chip tester 1 receives the difference value amplification signal through the data signal transmission line 14. In one embodiment, the parameter calculation module 11 includes a software program module, and the equivalent impedance Z2 between the first pin and the second pin of the chip under test 21 is calculated by writing A1, A2, A3, Z1, the value of the difference value amplification signal and the calculation rule (such as the calculation formula of Z2 above) into the software program module. As shown in Figure 4 The output end of the third error amplifier AP3 sends the difference value amplification signal to the parameter calculation module 11 in the chip tester 1 through the data signal transmission line 14.
[0042] In some embodiments, the abnormality indicating module 12 is also arranged in the test circuit, and is used to preliminarily determine whether the to-be-tested chip 21 has an obvious abnormality. Specifically, the abnormality indicating module 12 receives the difference amplification signal, and determines whether the difference amplification signal is within a reasonable range, and generates an abnormality indicating signal. It can be understood that the reasonable range is a pre-set threshold range, and when the difference amplification signal is out of the threshold range, it means that the signal level difference between the to-be-tested chip 21 and the reference chip 22 is too large, that is, the to-be-tested chip 21 has an abnormality. Generally, the abnormality reference signal VREF1 or VREF2 can be set in the abnormality indicating module 12, and when the difference amplification signal is greater than VREF1 or less than VREF2, it means that the to-be-tested chip 21 has an abnormality, and an abnormality indication or an abnormality alarm can be performed. For example, if the lead wire of the to-be-tested chip 21 is deformed when the lead wire is welded, the parasitic impedance of the to-be-tested chip 21 will be obviously increased, and the impedance of the to-be-tested chip 21 is found to be greatly different from that of the reference chip 22, so that the abnormality can be determined. Through the module, the trouble of using X-ray and ultrasonic chip to judge the lead wire deformation can be omitted, and the abnormality of the to-be-tested chip 21 can be directly judged by using the difference amplification signal.
[0043] In some embodiments, the abnormality indicating module 12 is arranged in the chip tester 1, and the chip tester 1 receives the difference amplification signal through the data signal transmission line 14. In an embodiment, the abnormality indicating module 12 can also be a software program module, and the value of the difference amplification signal, the value of the abnormality reference signal and the judgment rule are written into the software program module to determine whether there is an abnormality and generate an abnormality indicating signal. At this time, it can be determined whether the to-be-tested chip 21 has an abnormality first, and the parameter calculation is performed only when the chip has no abnormality, so as to reduce meaningless measurement. Specifically, when the abnormality indicating signal indicates that the difference amplification signal is within a reasonable range, the parameter calculation module 11 receives the difference amplification signal, and calculates the equivalent impedance between the first pin and the second pin of the to-be-tested chip 21 according to the difference amplification signal. It can be understood that the abnormality indicating module 12 can be arranged as needed in the present disclosure, and the arrangement of the abnormality indicating module 12 can save part of the process and reduce the waste of computing resources for unqualified workpieces. However, it can be understood that even if the abnormality indicating module 12 is not arranged, the equivalent impedance between the first pin and the second pin of the to-be-tested chip 21 can also be accurately measured.
[0044] In a specific embodiment, the structure of the to-be-tested chip 21 is as shown in Figure 5As shown, the chip under test (DUT) 21 includes a first transistor Q1, a second transistor Q2, and a control circuit 211. The DUT 21 has an input pin IN, a switching node pin SW, a ground pin GND, and a feedback pin FB. The first transistor Q1 and the second transistor Q2 are connected in series between the input pin IN and the ground terminal. The common terminal of the first transistor Q1 and the second transistor Q2 is connected to the switching node pin SW. The control terminals of both the first transistor Q1 and the second transistor Q2 are connected to the control circuit 211 to receive control signals. The control circuit 211 receives feedback signals through the feedback pin FB and then generates control signals based on the feedback signals. The first transistor Q1 and the second transistor Q2 are both schematically represented as MOSFETs, having a drain, a source, and a gate. The control terminal of the transistor corresponds to the gate of the MOSFET.
[0045] For example, in one embodiment, when it is necessary to measure the equivalent impedance of the second transistor Q2 after it is turned on between the switching node pin SW and the ground pin GND of the chip, the switching node pin SW of the chip is defined as the first pin a2 of the chip under test 21, and the ground pin GND of the chip is defined as the second pin b2 of the chip under test 21. Another chip with the same model as the chip under test 21 and which has passed the test is selected as the reference chip 22, and the test is performed after the test circuit is built according to the above embodiment. In this embodiment, the equivalent impedance between the first pin a2 and the second pin b2 is mainly the on-resistance of the second transistor Q2.
[0046] For example, in another embodiment, if it is necessary to measure the capacitive reactance of the parasitic capacitance between the drain and source of the second transistor Q2, the second transistor Q2 can be controlled to not conduct. The equivalent impedance measured by the test circuit can be used to represent the capacitive reactance of the parasitic capacitance between the drain and source of the second transistor Q2.
[0047] In the embodiments disclosed above, by using a reference chip for parameter comparison and an error amplifier to amplify the difference between the two, the test accuracy can be greatly improved, which is beneficial for the testing of parasitic parameters. Furthermore, when measuring capacitive and inductive reactance, it is not necessary to consider the phase difference between the current and voltage between the two pins of the chip under test; these can be directly derived from the relevant data and derivation formulas of the reference chip.
[0048] It is understandable that the above Figure 5 The chip under test 21 in the diagram is only illustrative. Those skilled in the art can use the test circuit provided in this disclosure to test the equivalent impedance of any suitable chip.
[0049] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0050] Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.
Claims
1. An equivalent impedance testing circuit for a chip, wherein the equivalent impedance testing circuit is used to test the equivalent impedance between a first pin and a second pin of the chip under test, characterized in that, The test circuit comprises: a reference chip having a first pin and a second pin, the reference chip being a chip of the same type as the chip to be tested and passing each-phase parameter test, the first pin of the reference chip corresponding to the first pin of the chip to be tested, the second pin of the reference chip corresponding to the second pin of the chip to be tested, the first pin of the reference chip being coupled to a first end of an excitation source, the second pin of the reference chip being coupled to the first pin of the chip to be tested, and the second pin of the chip to be tested being coupled to a second end of the excitation source; a first error amplifier having a first input end, a second input end and an output end, the first input end of the first error amplifier being coupled to the first pin of the reference chip, and the second input end of the first error amplifier being coupled to the second pin of the reference chip; a second error amplifier having a first input end, a second input end and an output end, the first input end of the second error amplifier being coupled to the first pin of the chip to be tested, and the second input end of the second error amplifier being coupled to the second pin of the chip to be tested; a third error amplifier having a first input end, a second input end and an output end, the first input end of the third error amplifier being coupled to the output end of the first error amplifier, the second input end of the third error amplifier being coupled to the output end of the second error amplifier, and the output end of the third error amplifier providing a difference-amplified signal; a parameter calculation module receiving the difference-amplified signal and calculating the equivalent impedance between the first pin and the second pin of the chip to be tested according to the difference-amplified signal.
2. The test circuit of claim 1, wherein, The parameter calculation module is arranged in a chip tester, and the chip tester receives the difference-amplified signal through a data signal transmission line and sends the difference-amplified signal to the parameter calculation module.
3. The test circuit of claim 2, wherein, The parameter calculation module comprises a first software program module, and the equivalent impedance between the first pin and the second pin of the chip to be tested is calculated by writing the amplification multiple of the first error amplifier, the amplification multiple of the second error amplifier, the amplification multiple of the third error amplifier, the equivalent impedance between the first pin and the second pin of the reference chip, the value of the difference-amplified signal and the calculation rule into the first software program module.
4. The test circuit of claim 1, wherein, The test circuit further comprises: an abnormality indication module receiving the difference-amplified signal and judging whether the difference-amplified signal is within a reasonable range and generating an abnormality indication signal.
5. The test circuit of claim 4, wherein, The abnormality indication module is arranged in the chip tester, and the chip tester receives the difference-amplified signal through the data signal transmission line and sends the difference-amplified signal to the abnormality indication module.
6. The test circuit of claim 5, wherein, The abnormality indication module comprises a second software program module, and whether there is an abnormality and the abnormality indication signal are determined by writing the value of the difference-amplified signal, the value of an abnormality reference signal and a judgment rule into the second software program module.
7. The test circuit of claim 5, wherein, When the abnormality indication signal indicates that the difference-amplified signal is within a reasonable range, the parameter calculation module receives the difference-amplified signal and calculates the equivalent impedance between the first pin and the second pin of the chip to be tested according to the difference-amplified signal.
8. The test circuit of claim 1, wherein, The excitation source comprises a direct current source.
9. The test circuit of claim 1, wherein, The excitation source comprises an alternating current source.
10. The test circuit of claim 1, wherein, The excitation source is provided by the chip tester, and the excitation source of the chip tester is coupled to the reference chip and the chip to be tested through an excitation signal transmission line.