Semiconductor structure

Abstract

A semiconductor structure is provided that includes a semiconductor die having a first region and a second region. The semiconductor die includes a device layer in the second region, an insulating material extending over the first region and the second region, and a plurality of metallization structures embedded in the insulating material and electrically connected to the device layer. The plurality of metallization structures includes a plurality of passive device structures in the first region and a plurality of thermal traces in the second region, and the plurality of passive device structures and the plurality of thermal traces are of the same material and are co-flush. The plurality of passive device structures are electrically connected to the device layer, and the plurality of thermal traces are electrically floating.

Description

Technical Field

[0001] Embodiments of this utility model relate to semiconductor structures. Background Technology

[0002] Smaller form factor and better reliability have driven advancements in packaging technology. Packaging and integrating different types of semiconductor dies or heterogeneous chiplets with other electronic devices is a significant challenge. Utility Model Content

[0003] This utility model provides a semiconductor structure including a semiconductor die having a first region and a second region located adjacent to the first region. The semiconductor die includes: a device layer located in the second region; an insulating material located above the device layer and extending above both the first and second regions; and a plurality of metallized structures embedded in the insulating material and electrically connected to the device layer. The plurality of metallized structures includes a plurality of passive device structures located in the first region and a plurality of thermal traces located in the second region. The plurality of passive device structures and the plurality of thermal traces are made of the same material and are located at the same level as the plurality of metallized structures. The plurality of passive device structures are electrically connected to the device layer, and the plurality of thermal traces are electrically floating.

[0004] This utility model provides a semiconductor structure including a first die having a first device region and a first peripheral region adjacent to the first device region; and a second die stacked on and bonded to the first die, wherein the second die has a second device region and a second peripheral region adjacent to the second device region. The first die includes: a first insulating material located above and extending over the first device region and the first peripheral region; and a plurality of first metallization structures embedded in the first insulating material, wherein the plurality of first metallization structures include a resistor structure located in the first peripheral region and a first thermal trace located in the first device region, the resistor structure and the first thermal trace being located at the same level in the plurality of first metallization structures, the resistor structure and the first thermal trace being made of a first metallic material, the first metallic material being different from the material of the plurality of first metallization structures, and the thermal conductivity of the first thermal trace being higher than the thermal conductivity of the first insulating material. The second die includes: a second insulating material located above and extending over the second device region and the second peripheral region; and a plurality of second metallized structures embedded in the second insulating material, wherein the plurality of second metallized structures includes a capacitor structure located in the second peripheral region and a plurality of second thermal traces located in the second device region, the capacitor structure and the plurality of second thermal traces being located at the same level in the plurality of second metallized structures, the capacitor structure and the plurality of second thermal traces being made of a second metallic material, the second metallic material being different from the material of the plurality of second metallized structures, and the thermal conductivity of the plurality of second thermal traces being higher than the thermal conductivity of the second insulating material. Attached Figure Description

[0005] The best understanding of all aspects of this invention will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 This is a schematic top view of an exemplary package component having multiple semiconductor dies according to some embodiments of the present disclosure.

[0007] Figures 2 to 6 These are schematic cross-sectional and top views illustrating various stages of a manufacturing method for forming a semiconductor structure according to some embodiments of the present disclosure.

[0008] Figure 7A , Figure 8A , Figure 7B and Figure 8BThese are schematic top and cross-sectional views illustrating the relative arrangement of multiple thermal traces and multiple heat pipes relative to the positions of multiple underlying heating points according to embodiments of the present disclosure.

[0009] Figure 9 A schematic cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present disclosure is shown.

[0010] Figure 10 A schematic cross-sectional view of an exemplary packaging structure according to some embodiments of the present disclosure is shown.

[0011] [Explanation of Symbols]

[0012] 10D: Semiconductor die

[0013] 50: Package structure

[0014] 50C, 60C: Capacitors

[0015] 50R, 60R: Resistors

[0016] 50T1, 50T2, 50T3, 60T1, 60T2, 60T3, TT1, TT2: Thermal traces

[0017] 100, W1, W2, W3, W4: Chips

[0018] 102, 502, 602: Semiconductor substrates

[0019] 103, 503, 603, DL1, DL2, DL3, DL4: Device Layer

[0020] 104, 504, 604: Local connection structure

[0021] 105, 505, 605: Perforation

[0022] 106: Dielectric Materials

[0023] 107: Insulating materials

[0024] 108, 508, 608: Metallized structure

[0025] 108BP: Bottom plate

[0026] 108C: Stacked capacitor structure

[0027] 108I: Insulator layer

[0028] 108II: Insulating Block

[0029] 108M1: First metal layer

[0030] 108M2: Second metal layer

[0031] 108MD: Fictitious metallic film pattern

[0032] 108MD1: First fictitious metallic film pattern

[0033] 108MD2: Second dummy metal film pattern

[0034] 108RD: Dummy resistive film pattern

[0035] 108RS: Thin resistive film structure

[0036] 108TP: Top panel

[0037] 120, HP1, HP2, HP3, HP5, HP6: Heat pipes

[0038] 500: First die

[0039] 510, 610, HB1, HB2, HB3, HB4: Joint structure

[0040] 600: Second die

[0041] 620: Rewire Layer

[0042] 621: Dielectric material layer

[0043] 622: Rewire Metal Pattern

[0044] 630: Conductive terminal

[0045] 631: Metal Pillar

[0046] 632: Bump

[0047] 1032: Semiconductor Device

[0048] 1071, 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079: Insulation layer

[0049] 1081, 1082, 1083, 1084, 1085, 1086, 108U1, 108U2: Internal wiring structure

[0050] 1081V, 1082V, 1083V, 1084V, 1085V, 1086V, 1087V: Metallic through-hole

[0051] BE1, BE2, BE3, BE4: Downstream process area

[0052] CL: Divider

[0053] DL: Cutting Track

[0054] Hs1, Hs2, Hs3, Hs4: heating points

[0055] L1, L2, L3, L4, L5, L6: Hierarchical levels

[0056] R1: Zone 1

[0057] R2: Second District

[0058] SW: Stacked structure

[0059] VV1, VV2, VV3, VV4: Semiconductor Through-hole Detailed Implementation

[0060] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0061] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0062] It should be understood that the following embodiments of this disclosure provide applicable concepts that can be embodied in various specific contexts. The specific embodiments discussed herein are merely illustrative and relate to three-dimensional (3D) integrated structures or components, and are not intended to limit the scope of this disclosure. Embodiments of this disclosure describe exemplary manufacturing processes for 3D stacked structures and 3D stacked structures manufactured therefrom. Some embodiments of this disclosure relate to 3D stacked structures formed by wafer bonding structures and stacked wafers and / or dies. Other embodiments relate to 3D integrated structures or components, including post-passivation interconnect (PPI) structures or interposers with other electrical connection components, including wafer-to-wafer assembly structures, die-to-wafer assembly structures, package stack assembly structures, die-to-die assembly structures, and die-to-substrate assembly structures. Wafers or dies may include one or more types of integrated circuits or electronic components located on a bulk semiconductor substrate or an insulating silicon / germanium substrate. These embodiments are intended to provide further illustration and are not intended to limit the scope of this disclosure.

[0063] Figure 1 This is a schematic top view of an exemplary package component having multiple semiconductor dies according to some embodiments of the present disclosure.

[0064] exist Figure 1 The present invention provides a packaging component that can be used to form a stacked semiconductor structure or a package structure in a packaging process. In some embodiments, the packaging component is a wafer 100 in which a plurality of semiconductor dies 10D are defined or formed. In some embodiments, the wafer 100 is a semiconductor bulk wafer in which active devices and optionally passive devices are formed. Figure 1 As shown, the multiple dashed lines represent multiple dicing channels (DL). In subsequent dicing processes, the wafer 100 will be diced through these dicing channels (DL) to obtain multiple semiconductor dies 10D that are separated from each other through the dicing process. It is understood that the number of multiple semiconductor dies 10D is merely exemplary, and the multiple semiconductor dies 10D may include dies of the same type or with the same function. In some embodiments, the multiple semiconductor dies 10D have the same design and perform the same function. In some embodiments, the multiple semiconductor dies of the wafer 100 have different designs and perform different functions.

[0065] Figures 2 to 6 These are schematic cross-sectional and top views illustrating various stages of a manufacturing method for forming a semiconductor stacked structure according to some embodiments of the present disclosure. Identical parts or elements with similar or identical structural configurations in the figures may be labeled with the same reference numerals.

[0066] Figure 2This is a schematic cross-sectional view illustrating an intermediate stage of a method for manufacturing a semiconductor stacked structure according to some embodiments of the present disclosure. Figure 3 A schematic top view shows an exemplary arrangement of multiple thin resistive film structures and multiple dummy resistive film patterns relative to an underlying element. Figure 2 In some embodiments, a wafer 100 is provided, and the wafer 100 is similar to the wafer 100 described in the preceding paragraphs. In some embodiments, the wafer 100 is a semiconductor wafer, and the wafer 100 includes a semiconductor substrate 102, a device layer 103 formed in or on the semiconductor substrate 102, a plurality of local connection structures 104 embedded in a dielectric material 106 formed on the semiconductor substrate 102 and connected to the device layer 103, and a plurality of through vias 105 extending from the plurality of local connection structures 104 into and through the semiconductor substrate 102.

[0067] In some embodiments, wafer 100 is a silicon wafer, or a bulk wafer made of other semiconductor materials (e.g., III-V group semiconductor materials, such as gallium nitride (GaN) or gallium arsenide (GaAs)). In some embodiments, semiconductor substrate 102 may be a single-crystal semiconductor substrate, such as a silicon substrate; an elemental semiconductor, such as germanium; a suitable compound semiconductor, such as silicon carbide (SiC), indium arsenide (InAs), or indium phosphide (InP), or a suitable alloy semiconductor, such as silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP). In some embodiments, semiconductor substrate 102 is or includes a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, semiconductor substrate 102 includes an oxide semiconductor material, such as indium tin oxide (ITO). In some embodiments, via 105 is or includes a metal semiconductor via (TSV), and via 105 connected to a plurality of local connection structures 104 is electrically connected to some semiconductor devices 1032 in device layer 103.

[0068] In some embodiments, device layer 103 includes a plurality of semiconductor devices 1032 formed in or on the semiconductor substrate 102 of wafer 100 during front-end (FEOL) processes. In some embodiments, semiconductor devices 1032 are or include active devices, such as transistors, memory, or power devices. In some embodiments, transistors include one or more types of transistors, such as field-effect transistors (FETs), including fin FETs, nanosheet FETs, nanowire FETs, gate-all-around FETs, fork-sheet FETs, or complementary FETs, and the configuration of the transistor structure may vary depending on design requirements. In exemplary embodiments, some or all of the plurality of semiconductor devices 1032 are electrically interconnected and electrically connected to a plurality of local connection structures 104. Here, in the drawings, detailed constructions and intermediate layers may be omitted and indicated by ellipsis dot.

[0069] In some embodiments, see Figure 2 Only a portion of wafer 100 is shown; for wafers comprising multiple dies or die units prior to dicing or monomerization, Figure 2 The image shows a portion of at least one die unit of wafer 100. 2. In some embodiments, for Figure 2 The die unit in a portion of the illustrated wafer 100 includes at least a first region R1 and a second region R2. In some embodiments, the second region R2 is or includes a main region in which multiple devices (primarily active devices and optionally passive devices) are formed, and the first region R1 is or includes a peripheral region in which passive devices are primarily formed but not active devices. In one embodiment, the first region R1 is located adjacent to the second region R2. In one embodiment, the first region R1 surrounds the second region R2. In some embodiments, the passive devices include capacitors, resistors, diodes, photodiodes, sensors, inductors, or fuses.

[0070] like Figure 2As shown, in some embodiments, insulating material 107 and a plurality of metallization structures 108 are formed on a plurality of local connection structures 104 and dielectric material 106. In some embodiments, the plurality of metallization structures 108 are embedded in insulating material 107 above semiconductor substrate 102. The plurality of metallization structures 108 are electrically connected to the plurality of local connection structures 104 and to device layer 103 through the plurality of local connection structures 104. In an exemplary embodiment, a plurality of semiconductor devices 1032 in device layer 103 are electrically connected to the plurality of metallization structures 108. For the plurality of semiconductor devices 1032 in device layer 103, the plurality of metallization structures 108 and the plurality of local connection structures 104 work together to provide front-side electrical connections, while the plurality of local connection structures 104, together with a plurality of through-holes 105, establish back-side electrical connections. In some embodiments, the plurality of local connection structures 104 and the plurality of metallization structures 108 are formed through middle-end (MEOL) and back-end (BEOL) processes, respectively.

[0071] In some embodiments, the material of the metallization structure 108 includes copper (Cu), copper alloys, titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), tungsten (W), their nitrides, or combinations thereof. In some embodiments, multiple metallization structures 108, including multilayer metallization structures and portions formed therebetween, are formed by the same metallization process and made of the same metallic material. In some embodiments, the metallization structure 108 is made of copper or a copper alloy. In some embodiments, the material of the insulating material 107 includes silicon oxide, spin-coated dielectric material, low-k dielectric material, or combinations thereof. In some embodiments, the insulating material 107 comprises a plurality of low-k dielectric layers, and examples of low-k dielectric materials include borophosporosilicate glass (BPSG), phosporosilicate glass (PSG), amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), polyimide, flare, xerogel, aerogel, hydrogen silsesquioxane (HSQ), fluorinated silicon oxide (SiOF), or combinations thereof. In some embodiments, the insulating material 107 comprises silicon oxide formed using a CVD process with tetraethoxysilane (TEOS).

[0072] In some embodiments, see Figure 2Multiple metallized structures 108 are formed in the insulating material 107, including the sequential formation of multiple first interconnect structures (also referred to as interconnect structures) 1081, the formation of an insulating layer 1071, the formation of multiple second interconnect structures (also referred to as interconnect structures) 1082, the formation of an insulating layer 1072, the formation of multiple third interconnect structures (also referred to as interconnect structures) 1083, and the formation of an insulating layer 1073. In some embodiments, the interconnect structures 1081, 1082, and 1083 include metal wires or traces interconnected through metal vias 1081V, 1082V, and 1083V. From the perspective of the formation sequence, the interconnect structures 1081, 1082, 1083 (and metal vias 1081V, 1082V, 1083V) embedded in the insulating layers 1071, 1072, 1073 can be referred to as the lower-level interconnect structures (i.e., layers L1, L2, L3) of the multiple metallized structures 108.

[0073] In some embodiments, reference Figure 2 After forming the first, second, and third interconnect structures 1081-1083 (layers L1, L2, L3), multiple thin resistive film structures 108RS and multiple dummy resistive film patterns 108RD are simultaneously formed on the insulating layer 1073 and in the first region R1 and the second region R2 above the multiple third interconnect structures 1083 (third layer L3). The formation of the thin resistive film structures 108RS and the dummy resistive film patterns 108RD involves forming a metal resistive layer (not shown) comprehensively on the insulating layer 1073 (over the entire first region R1 and the second region R2), and then patterning the metal resistive layer to form the multiple thin resistive film structures 108RS in the first region R1 and the multiple dummy resistive film patterns 108RD in the second region R2. Figure 2 It can be seen that the multiple thin resistive film structures 108RS in the first region R1 are physically separated from and isolated from the multiple dummy resistive film patterns 108RD in the second region R2. In addition, the multiple dummy resistive film patterns 108RD in the second region R2 are electrically isolated from the multiple thin resistive film structures 108RS in the first region R1.

[0074] In some embodiments, the material of the resistive layer includes titanium nitride (TiN), Ti, tantalum nitride (TaN), Ta, W, Co, Ni, aluminum (Al), rhodium (Rh), iridium (Ir), ruthenium (Ru), molybdenum (Mo), osmium (Os), silver (Ag), or gold (Au). In some embodiments, the metal material used to form the resistive layer of the thin resistive film structure 108RS and the dummy resistive film pattern 108RD includes TiN. In some embodiments, the metal material used to form the resistive layer of the thin resistive film structure 108RS and the dummy resistive film pattern 108RD includes TaN. In some embodiments, the resistive layer is formed by performing a deposition process, a plating process, or a combination thereof. The formation of the metal resistive layer involves electrochemical plating (ECP), electroless deposition (ELD), deposition including CVD, PVD, ion beam deposition (IBD), atomic layer deposition (ALD), or other suitable processes, such as molecular beam epitaxy (MBE).

[0075] refer to Figure 3 In some embodiments, multiple thin resistive film structures 108RS are formed as separate rectangular blocks arranged in an array in the first region R1. Figure 3 From the schematic top view, the bulk of multiple thin resistive film structures 108RS can be interconnected through multiple interconnect structures 108U1 in the upper layer and / or multiple through-holes beneath. Furthermore, in Figure 3 In some embodiments, multiple dummy resistive film patterns 108RD are formed as semi-open loop bands (or C-shaped rings). From Figure 3 As can be seen, the dummy resistive film pattern 108RD is formed as a semi-open loop surrounding multiple potential heat-generating points Hs1 (hot spots represented by dashed squares) in the lower part of the structure. It is worth noting that during operation, heat may be generated at certain locations within the second region R2 near the power device or memory device, becoming multiple heat-generating points in the structure. Multiple dummy resistive film patterns 108RD are arranged around or surround the potential heat-generating points to facilitate horizontal heat transfer from the heat-generating points to the surrounding environment.

[0076] refer to Figure 2Multiple thin resistive film structures 108RS are electrically connected to multiple third interconnect structures 1083 through multiple metal vias 1083V. In some embodiments, the multiple thin resistive film structures 108RS are electrically connected to multiple metallization structures 108, and are also electrically coupled to multiple semiconductor devices 1032 or other components through the multiple metallization structures 108. The multiple thin resistive film structures 108RS include at least one high-resistance metal film to provide higher resistance and function as a resistor. In some embodiments, multiple dummy resistive film patterns 108RD are formed in a second region R2 above the device layer 103. Reference Figure 2 and Figure 3 The multiple dummy resistive film patterns 108RD are not connected to the multiple third interconnect structures 1083, and the multiple dummy resistive film patterns 108RD are electrically isolated from and electrically floated by the multiple metallized structures 108.

[0077] In some embodiments, in the second region R2, a plurality of dummy resistive film patterns 108RD are electrically floating, although they may also be connected to a plurality of heat pipes (the positions of the plurality of heat pipes, which are formed later, are shown in elliptical or oval dashed circles). In some embodiments, the plurality of dummy resistive film patterns 108RD serve as thermal elements to improve horizontal thermal conductivity and enhance the effective heat dissipation of the structure. Figure 2 As shown, multiple dummy resistive film patterns 108RD and multiple thin resistive film structures 108RS are located at the same level and next to each other. Since the multiple dummy resistive film patterns 108RD and multiple thin resistive film structures 108RS are formed from the same material and the same layer during the same process, the bottom surfaces of the multiple dummy resistive film patterns 108RD and multiple thin resistive film structures 108RS are coplanar, and the multiple dummy resistive film patterns 108RD and multiple thin resistive film structures 108RS are flush with each other (commonly flush).

[0078] In some embodiments, the materials of the thin resistive film structure 108RS and the dummy resistive film pattern 108RD are different from the material of the metallized structure 108. Based on embodiments, the materials of the thin resistive film structure 108RS and the dummy resistive film pattern 108RD have a higher resistivity than the material of the metallized structure 108, and the materials of the thin resistive film structure 108RS and the dummy resistive film pattern 108RD have a lower thermal resistivity than the material of the insulating material 107. Thermal resistivity is the reciprocal of thermal conductivity, while resistivity is the reciprocal of electrical conductivity. In some embodiments, the thin resistive film structure 108RS has a higher resistance than the metallized structure 108 and functions as a resistor. In some embodiments, the electrically floating dummy resistive film pattern 108RD provides a higher thermal conductivity than the surrounding insulating material 107 and functions as a thermal trace extending horizontally above the surfaces of multiple insulating layers of the insulating material 107. Thermal traces and heat pipes are heat transfer / heat dissipation features or components (for heat dissipation purposes) but are not electrical functional elements.

[0079] For a thin resistive film structure 108RS containing a metal resistive layer on an insulating material support, the resistance value of the thin-film resistor (sheet resistance) can be adjusted by changing the length, width, and thickness of the resistor structure. For a dummy resistive film pattern 108RD containing the same metal resistive layer, the thermal resistance value of the film pattern can be adjusted by changing the thickness of the metal resistive layer. Compared to a structure without a dummy resistive film pattern (thermal trace), the formation of a dummy resistive film pattern (thermal trace) results in a reduction of approximately 10% to approximately 20% in the peak temperature of the on-chip temperature gradient. This temperature reduction may lead to a significant improvement in device reliability and performance.

[0080] Figure 4 This is a schematic cross-sectional view illustrating an intermediate stage of a manufacturing method for forming a semiconductor stacked structure according to some embodiments of the present disclosure. Figure 5 A schematic top view shows an exemplary arrangement of multiple stacked capacitor structures and multiple dummy metal film patterns relative to the underlying elements.

[0081] In some embodiments, reference Figure 4After forming multiple thin resistive film structures 108RS and multiple dummy resistive film patterns 108RD, an insulating layer 1074 is formed on top of and covering the multiple thin resistive film structures 108RS and multiple dummy resistive film patterns 108RD. For example, the insulating layer 1074 fills the spaces and gaps between the multiple thin resistive film structures 108RS and multiple dummy resistive film patterns 108RD. Alternatively, before forming the insulating layer 1074, another insulating layer may be formed to fill the spaces and gaps between the multiple thin resistive film structures 108RS and multiple dummy resistive film patterns 108RD. Subsequently, more interconnect structures are formed in the metallization structure 108, including the sequential formation of multiple fourth interconnect structures (also referred to as interconnect structures) 1084, the formation of an insulating layer 1075, the formation of multiple fifth interconnect structures (also referred to as interconnect structures) 1085, the formation of an insulating layer 1076, the formation of multiple sixth interconnect structures (also referred to as interconnect structures) 1086, and the formation of an insulating layer 1077. In some embodiments, the interconnect structures 1084, 1085, and 1086 include metal lines or traces interconnected through metal vias 1084V, 1085V, 1086V, and 1087V. From the perspective of the formation sequence, the interconnect structures 1084, 1085, and 1086 (as well as the metal vias 1084V-1087V) embedded in the insulating layers 1075, 1076, and 1077 can be referred to as higher-level interconnect structures (i.e., layers L4, L5, and L6) of the multiple metallized structures 108.

[0082] In some embodiments, reference Figure 4After forming the fourth, fifth, and sixth interconnect structures 1084-1086 (layers L4, L5, L6), multiple stacked capacitor structures 108C and multiple dummy metal film patterns 108MD are formed on the insulating layer 1077 and in the first region R1 and the second region R2 above the multiple sixth interconnect structures 1086 (sixth layer L6), respectively. The formation of the stacked capacitor structures 108C and the dummy metal film patterns 108MD includes sequentially forming a first metal layer 108M1 and an insulating layer 108I on the insulating layer 1077 (over the entire first region R1 and the second region R2), patterning the first metal layer 108M1 and the insulating layer 108I, and forming an insulating layer 1078. Subsequently, a second metal layer 108M2 is formed and patterned, and then an insulating layer 1079 is formed. Through a patterning process, the first metal layer 108M1 is patterned to form multiple first dummy metal film patterns 108MD1 in the second region R2. The first metal layer 108M1 retained in the first region R1 becomes multiple bottom plates 108BP in multiple stacked capacitor structures 108C. Through a patterning process, the insulating layer 108I is patterned to form multiple insulator blocks 108II in the first region R1. The insulating layer 108I in the second region R2 is completely removed, and the insulating layer 1078 fills the gaps and spaces between the multiple first dummy metal film patterns and the multiple bottom plates 108BP, as well as between the multiple insulator blocks 108II. Through a patterning process, the second metal layer 108M2 is patterned to form multiple second dummy metal film patterns 108MD2 in the second region R2. The second metal layer 108M2 retained in the first region R1 becomes multiple top plates 108TP in multiple stacked capacitor structures 108C.

[0083] refer to Figure 4 The upper left portion shows an exemplary partial top view of the stacked capacitor structure 108C, where the top plate 108TP has a smaller span but completely overlaps the span of the insulating block 108II, and the top plate 108TP partially covers the insulating block 108II. Similarly, see... Figure 4 The exemplary partial top view shown in the upper left shows that the span of the insulating block 108II is small but completely overlaps with the span of the bottom plate 108BP, the span of the top plate 108TP completely overlaps with the bottom plate 108BP, and the insulating block 108II partially covers the bottom plate 108BP.

[0084] In some embodiments, in the first region R1, a bottom plate 108BP, a top plate 108TP, and an insulating block 108II sandwiched between the top plate 108TP and the bottom plate 108BP form a stacked capacitor structure 108C. In some embodiments, in the second region R2, a horizontally extending first dummy metal film pattern 108MD1 and a second dummy metal film pattern 108MD2, separated by an insulating layer 1078, together form a dummy metal film pattern 108MD. In some embodiments, reference... Figure 4 The span of the first dummy metal film pattern 108MD1 and the span of the second dummy metal film pattern 108MD2 completely overlap (i.e., the vertical projections of the first and second dummy metal film patterns onto the underlying plane overlap). In some embodiments, the span of the first dummy metal film pattern 108MD1 and the second dummy metal film pattern 108MD2 are vertically aligned. From Figure 4 It can be seen that the stacked capacitor structure 108C in the first region R1 is physically separated from and isolated from the dummy metal film pattern 108MD in the second region R2. In addition, the dummy metal film pattern 108MD in the second region R2 is electrically isolated from the stacked capacitor structure 108C in the first region R1.

[0085] See Figure 4 Multiple stacked capacitor structures 108C are electrically connected to multiple underlying interconnect structures (e.g., a sixth interconnect structure 1086 through a metal via 1087V). In some embodiments, the multiple stacked capacitor structures 108C are electrically connected to multiple metallization structures 108, and are further electrically coupled to multiple semiconductor devices 1032 or other components through the multiple metallization structures 108. The stacked capacitor structures 108C include metal-insulator-metal capacitors and act as capacitors in the electrical path (in the circuit). In some embodiments, multiple dummy metal film patterns 108MD are formed in a second region R2 above the device layer 103. Reference Figure 4 Multiple dummy metal film patterns 108MD and multiple metallized structures 108 are electrically isolated, not connected to any other electrical components, and are electrically floating (not part of the electrical path).

[0086] Since the multiple first dummy metal film patterns 108MD1 and the multiple bottom plates 108BP are formed from the same layer in the same process, the bottom surfaces of the multiple first dummy metal film patterns 108MD1 and the multiple bottom plates 108BP are coplanar, and the multiple first dummy metal film patterns 108MD1 and the multiple bottom plates 108BP are flush with each other (commonly flush). Similarly, the multiple second dummy metal film patterns 108MD2 and the multiple top plates 108TP are formed from the same layer in the same process, and their bottom surfaces are coplanar and flush with each other (commonly flush). Figure 4As shown, multiple dummy metal film patterns 108MD are located next to multiple stacked capacitor structures 108C and at the same level as the multiple stacked capacitor structures 108C.

[0087] In some embodiments, the material of the first metal layer 108M1 or the second metal layer 108M2 is individually selected from TiN, Ti, TaN, Ta, W, Co, Ni, Al, Rh, Ir, Ru, Mo, Os, Ag, or Au. In some embodiments, the metal material of the first metal layer 108M1 includes TiN or TaN. In some embodiments, the metal material of the second metal layer 108M2 includes TaN or TiN. In some embodiments, the first metal layer 108M1 or the second metal layer 108M2 is formed by performing a deposition process, a plating process, or a combination thereof. The formation of the first metal layer 108M1 or the second metal layer 108M2 involves ECP, ELD, CVD, PVD, ion beam deposition (IBD), ALD, or other suitable processes, such as molecular beam epitaxy (MBE). In some embodiments, the materials of the first metal layer 108M1 and the second metal layer 108M2 are different. In some embodiments, the materials of the first metal layer 108M1 and the second metal layer 108M2 are substantially the same.

[0088] In some embodiments, the materials of the first metal layer 108M1 and the second metal layer 108M2 are different from the material of the metallization structure 108. In some embodiments, the first metal layer 108M1 has a higher thermal conductivity than the insulating material 107, and the second metal layer 108M2 has a higher thermal conductivity, such that the first dummy metal pattern 108MD1 and the second dummy metal pattern 108MD2 are thermal traces.

[0089] refer to Figure 5 In some embodiments, the multiple bottom plates 108BP of the multiple stacked capacitor structures 108C are formed as separate rectangular metal blocks arranged side-by-side or in an array in the first region R1. Figure 5 From the schematic top view, multiple bottom plate blocks 108BP can be interconnected through multiple internal interconnect structures 108U2 in the upper layer and / or multiple underlying through holes. In the second region R2, as... Figure 5 As shown, in some embodiments, the first dummy metal film pattern 108MD1 is formed as a partially-open loop band. From Figure 5As can be seen, the first dummy metal film pattern 108MD1 is formed as an integral open loop surrounding multiple potential heat-generating points Hs2 (hot spots represented by dashed squares) in the lower part of the structure. Multiple dummy metal film patterns 108MD are arranged around or surround the potential heat-generating points to facilitate horizontal heat transfer from the heat-generating points to the surrounding environment.

[0090] In some embodiments, in the second region R2, the electrically floated plurality of first dummy metal film patterns 108MD1 and plurality of second dummy metal film patterns 108MD2 are also connected to a plurality of heat pipes (the positions of the plurality of heat pipes formed later are...). Figure 5 (Illustrated in the image as an elliptical or oval dashed circle). In some embodiments, the dummy metal film pattern 108MD, made of a high thermal conductivity material, provides a higher thermal conductivity than the surrounding insulating material 107 and serves as a thermal trace. A thermal trace is a heat transfer / heat dissipation feature or component (for heat dissipation purposes) but not an electrical functional element. In some embodiments, the dummy metal film pattern 108MD serves as a thermal trace to improve horizontal thermal conductivity and enhance effective heat dissipation of the structure.

[0091] refer to Figure 6 In some embodiments, a plurality of heat pipes 120 are formed in the wafer 100. In some embodiments, such as Figure 6 As shown, the heat pipe extends downward from the top surface of the wafer 100, passing through multiple first dummy metal film patterns 108MD1 and multiple second dummy metal film patterns 108MD2, multiple dummy resistive film patterns 108RD, insulating material 107, dielectric material 106, and to the semiconductor substrate 102. Figure 6 As shown, multiple dummy resistive film patterns 108RD, multiple first dummy metal film patterns 108MD1, and multiple second dummy metal film patterns 108MD2 serve as thermal traces and are interconnected through multiple heat pipes 120 passing through them to establish a thermal path. Figure 6 The heat pipe 120 (indicated by arrows showing the direction of heat transfer) is used to assist in the transfer of heat from the hot spot to the semiconductor substrate 102 and the surrounding environment. Forming the heat pipe 120 includes drilling or etching to form a through-hole and filling the through-hole with a thermally conductive metal material to form the heat pipe 120. In some embodiments, the heat pipe 120 is not connected to the metallized structure 108 or other electrical components (electrically floated) and is not part of the electrical path.

[0092] Compare Figure 3 and Figure 5The schematic top view shows that the dummy resistive film pattern 108RD and the first dummy metal film pattern 108MD1 are configured differently, and the spans of the first dummy metal film pattern 108MD1 and the dummy resistive film pattern 108RD at least partially overlap, even if the locations of the heat pipes that may pass through them coincide. Since the first dummy metal film pattern 108MD1 (dummy metal film pattern 108MD) and the dummy resistive film pattern 108RD are located at different levels, their respective designs or configurations can be adjusted based on the distribution and location of the underlying heat-generating points.

[0093] Although the steps of the method are described and illustrated as a series of actions or events, it should be understood that the order of these actions or events should not be construed as limiting. Furthermore, not all of the illustrated processes or steps are necessary to implement one or more embodiments of this disclosure. Additionally, while the illustrated process pertains to wafer-on-wafer (WoW) processes and can be further fabricated into monolithic die units suitable for stacked packaging or chip-on-wafer-on-substrate (CoWoS) packaging, constructed wafers comprising multiple chips can also be used in the aforementioned processes.

[0094] Figure 7A , Figure 8A , Figure 7B and Figure 8B These are schematic top and cross-sectional views illustrating the relative arrangement of multiple thermal traces and multiple heat pipes relative to the positions of multiple underlying heating points according to embodiments of the present disclosure.

[0095] refer to Figure 7A and Figure 7B Multiple heat pipes HP1 pass through the heat trace TT1 and extend downwards from the heat trace TT1 towards multiple heating points Hs3, without directly contacting the multiple heating points Hs3. (Reference) Figure 7A The heat trace TT1 is formed as a horizontal strip that spans the span of multiple heating points Hs3, while multiple heat pipes HP1 are arranged next to or between the spans of multiple heating points Hs3.

[0096] It is understandable that multiple heat pipes are not uniformly distributed throughout the entire cell area, but rather arranged around multiple local hot spots. Compared to the cell area, the total area of ​​all heat pipes arranged around multiple local hot spots can be approximately 1.5% of the cell area. Through multiple thermal traces (including multiple dummy metal film patterns and multiple dummy resistive film patterns), better horizontal heat transfer efficiency is provided. Furthermore, through the layout design, pattern design, or configuration of multiple thermal traces, connecting multiple thermal traces to heat pipes in different locations makes heat pipe arrangement more flexible and achieves a more efficient heat dissipation solution.

[0097] See Figure 8A and Figure 8B The thermal trace TT2, as seen in the top view, forms a buckle-shaped pattern (multiple interconnected square rings), and multiple heat pipes HP2 are evenly arranged along the pattern of the thermal trace TT2. Figure 8B In the process, multiple heat pipes HP2 also pass through the heat trace TT2 and extend downwards from the heat trace TT2 to approach multiple heating points Hs4, without directly contacting the multiple heating points Hs4. (Reference) Figure 8A The heat trace TT2 is formed to surround multiple heating points Hs4, and the heat trace TT2 extends horizontally across the span of multiple heating points Hs4, while some heat pipes HP2 are arranged next to the span of multiple heating points Hs4, and some heat pipes HP2 are arranged directly above multiple heating points Hs4.

[0098] Figure 9 A schematic cross-sectional view of an exemplary stacked structure according to some embodiments of the present disclosure is shown.

[0099] In some embodiments, see Figure 9 Multiple wafers W1, W2, W3 and W4 are stacked in a wafer-on-wafer manner to form a wafer-type stacked structure SW. Figure 9Only a portion of the stacked structure SW, comprising at least two die units, is shown, and multiple cutting lanes CL are shown in dashed lines. It should be understood that for simplicity of the figures, detailed construction and intermediate layers may be omitted and indicated with ellipses. For individual wafers W1, W2, W3, or W4, there are back-end process regions BE1, BE2, BE3, or BE4 (enclosed by dashed lines) between the device layers DL1, DL2, DL3, or DL4 (formed via front-end processes) and the bonding structures HB1, HB2, HB3, HB4. In some embodiments, wafers W1, W2, W3, and W4 are front-to-back bonded via bonding structures HB1, HB2, and HB3. In some embodiments, wafers W1-W4 are bonded via hybrid interfacial bonding to form a wafer-stacked-on-wafer stacked structure SW. Electrical connections are established between device layers DL1-DL4 and wafers W1-W4 through semiconductor through-hole (TSV) vias VV1, VV2, VV3, and VV4 and bonding structures HB1, HB2, and HB3. As described in the preceding paragraphs, some or all of the wafers W1-W4 are similar to wafer 100 as described in the preceding paragraphs, and thermal traces as described above are formed within the back-end process regions BE1, BE2, BE3, and / or BE4 of the wafers W1-W4. Furthermore, multiple heat pipes HP3 are formed in the stacked structure SW, extending through the back-end process regions BE1, BE2, BE3, and BE4 to thermally connect the multiple thermal traces formed in the back-end process regions BE1, BE2, BE3, and / or BE4 to establish thermal pathways.

[0100] In some embodiments, the semiconductor stack structure may undergo further processing, and multiple global connection structures, including multiple redistribution structures and multiple connectors, may be formed on the semiconductor stack structure. Alternatively, the stack structure may be monolithized to form multiple die units or multiple stacked die structures.

[0101] Figure 10 A schematic cross-sectional view of an exemplary packaging structure according to some embodiments of the present disclosure is shown.

[0102] refer to Figure 10In some embodiments, the package structure 50 includes a first die 500 stacked on and bonded to the second die 600. In some embodiments, the stacked first die 500 and the second die 600 may be manufactured from a stacked structure SW in wafer form as described above, but with fewer stacked wafers (e.g., two stacked wafers) and a similar element and configuration design as shown in wafer 100. It should be understood that, for simplicity of the drawings, detailed constructions and intermediate layers may be omitted and indicated by ellipses. In some embodiments, the first die 500 includes a semiconductor substrate 502, a device layer 503 formed in or on the semiconductor substrate 502, a plurality of local connection structures 504 connected to the device layer 503, and a plurality of through-holes 505 extending from the plurality of local connection structures 504 into the semiconductor substrate 502. In some embodiments, the first die 500 also includes a plurality of metallization structures 508 and bonding structures 510. For the first die 500, according to the manufacturing method and steps described in forming the metallization structure 108, multiple hot traces 50T1 are formed together with multiple resistors 50R, and multiple hot traces 50T2, 50T3 are formed together with multiple capacitors 50C. In some embodiments, the hot traces 50T1 are flush with the resistors 50R, and the hot traces 50T2, 50T3 are flush with the capacitors 50C. Figure 10 As shown, multiple thermal traces 50T1-50T3 sandwiched between multiple metallized structures 508 are connected via multiple heat pipes HP5. In some embodiments, thermal traces 50T1, 50T2, and 50T3 are located in the main device region and above the device layer 503, while multiple resistors 50R and multiple capacitors 50C are located in the peripheral region of the die. In some embodiments, thermal traces 50T1, 50T2, and 50T3 at least partially overlap vertically or even completely overlap. In some embodiments, thermal traces 50T1, 50T2, and 50T3 overlap vertically and are vertically aligned in the thickness direction (stack direction).

[0103] In some embodiments, the second die 600 includes a semiconductor substrate 602, a device layer 603, a plurality of local connection structures 604 connected to the device layer 603, a plurality of through-holes 605, a plurality of metallization structures 608, and a bonding structure 610. Similarly, the metallization structure 608 can be formed according to the manufacturing methods and steps described for forming the metallization structure 108, forming a plurality of thermal traces 60T1 together with a plurality of resistors 60R, and forming a plurality of thermal traces 60T2, 60T3 together with a plurality of capacitors 60C. In some embodiments, the thermal traces 60T1 are flush with the resistors 60R, and the thermal traces 60T2, 60T3 are flush with the capacitors 60C, and the thermal traces 60T1-60T3 sandwiched between the plurality of metallization structures 608 are connected through a plurality of heat pipes HP6. In some embodiments, thermal traces 60T1, 60T2, and 60T3 are located in the main device region and above the device layer 603, while a plurality of resistors 60R and a plurality of capacitors 60C are located in the peripheral region of the die. In some embodiments, thermal traces 60T1, 60T2, and 60T3 at least partially overlap vertically or even completely overlap vertically. In some embodiments, thermal traces 60T1, 60T2, and 60T3 overlap vertically and are vertically aligned in the thickness direction (stack direction).

[0104] Hot traces 50T1-50T3 and 60T1-60T3 are electrically floating and not electrically connected to device layer 503 or any of the semiconductor devices in device layer 603. Figure 10 As can be seen, in some embodiments, thermal traces 50T1-50T3 and 60T1-60T3 are vertically overlapped or vertically aligned. However, it is worth noting that thermal traces 50T1-50T3 and 60T1-60T3 may not be vertically overlapped or vertically aligned for different dies with different layout designs.

[0105] In some embodiments, the first die 500 and the second die 600 have different functions. In some embodiments, the second die 600 includes a logic die, such as a central processing unit (CPU) die, a graphics processing unit (GPU) die, a micro control unit (MCU) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, the first die 500 includes a memory die, such as a high bandwidth memory (HBM) die, a dynamic random access memory (DRAM) die, or a static random access memory (SRAM) die.

[0106] refer to Figure 10 In some embodiments, a redistribution layer (RDL) 620 is formed on the back side of the second die 600, and the redistribution layer 620 is electrically connected to the second die 600 and the first die 500 through at least a plurality of through-holes 605, a plurality of metallization structures 608, a plurality of metallization structures 508, a bonding structure 610, and a bonding structure 510. In some embodiments, the redistribution layer 620 includes a plurality of redistribution metal patterns 622 embedded in a dielectric material layer 621. This disclosure does not limit the configuration of the redistribution metal patterns, and the dielectric material layer may include more than one layer of dielectric material. In some embodiments, the dielectric material layer 621 exposes some of the underlying redistribution metal patterns 622, and a plurality of conductive terminals 630 are formed on the exposed redistribution metal patterns 622. In some embodiments, the conductive terminals 630 include metal pillars 631 and bumps 632. In some embodiments, the dielectric layer 621 is made of silicon oxide, silicon nitride, a low-k dielectric material, benzocyclobutene (BCB), epoxy resin, polyimide (PI), or polybenzoxazole (PBO). In some embodiments, the metal pillar 631 is made of copper or a copper alloy, and the bump 632 is made of solder. In one embodiment, the metal pillar 631 and the bump 632 located on the metal pillar 631 constitute microbumps. In some embodiments, the conductive terminal 630 includes copper pillar bumps.

[0107] Furthermore, the aforementioned packaging structure 50 can also be bonded to a circuit substrate or used as a packaging unit to form a 3D stacked package or a CoWoS package. This disclosure is not limited to the packaging structure shown in the figures.

[0108] In some embodiments, in addition to the metallization structure formed through the BEOL process, additional thermal traces are formed at the same level along with the passive device using the same material. These thermal traces provide effective horizontal (on or in plane) thermal conductivity and achieve better heat dissipation. Furthermore, since the thermal traces are made from the same material layer used to form the passive device (e.g., resistors and capacitors), forming the thermal traces requires no additional cost or is minimal, and allows for a more uniform layout design.

[0109] Furthermore, by forming thermal traces extending horizontally along the plane, the configuration of vertically extending heat pipes can be more flexible, thereby establishing an effective local heat dissipation path through the interconnect structure formed by the BEOL process. The presence of thermal traces effectively promotes heat dissipation from local hot spots and mitigates the performance degradation that may be caused by local heat accumulation in semiconductor stack structures.

[0110] In some embodiments of this disclosure, a semiconductor structure is provided. This semiconductor structure includes a semiconductor die having a first region and a second region adjacent to the first region. The semiconductor die includes a device layer located in the second region, an insulating material located above the device layer and extending above the first and second regions, and a plurality of metallized structures embedded in the insulating material and electrically connected to the device layer. The plurality of metallized structures include a plurality of passive device structures located in the first region and a plurality of hot traces located in the second region. The plurality of passive device structures are made of the same material as the plurality of hot traces and are located at the same level as the plurality of metallized structures. The plurality of passive device structures are electrically connected to the device layer, and the plurality of hot traces are electrically floating.

[0111] In some embodiments of this disclosure, a semiconductor structure is provided. This semiconductor structure includes a first die having a first device region and a first peripheral region adjacent to the first device region, and a second die stacked on and bonded to the first die. The second die has a second device region and a second peripheral region adjacent to the second device region. The first die includes a first insulating material located on and extending over the first device region and the first peripheral region, and a plurality of first metallization structures embedded in the first insulating material. The plurality of first metallization structures include a resistor structure located in the first peripheral region and a first thermal trace located in the first device region, the resistor structure and the first thermal trace being located at the same level in the plurality of first metallization structures, the resistor structure and the first thermal trace being made of a first metallic material, the first metallic material being different from the material of the plurality of first metallization structures, and the thermal conductivity of the first thermal trace being higher than the thermal conductivity of the first insulating material. The second die includes a second insulating material located on and extending over the second device region and the second peripheral region, and a plurality of second metallization structures embedded in the second insulating material. The plurality of second metallization structures include a capacitor structure located in a second peripheral region and a plurality of second thermal traces located in a second device region. The capacitor structure and the plurality of second thermal traces are located at the same level in the plurality of second metallization structures. The capacitor structure and the plurality of second thermal traces are made of a second metal material, which is different from the material of the plurality of second metallization structures. The thermal conductivity of the plurality of second thermal traces is higher than that of the second insulating material.

[0112] In some embodiments of this disclosure, a method for forming a semiconductor structure is described. A first wafer is provided having a plurality of first dies, each first die having a first device region and a first peripheral region adjacent to the first device region. The first die includes a plurality of first metallization structures embedded in a first insulating material, wherein the plurality of first metallization structures include a resistor structure located in the first peripheral region and a first thermal trace located in the first device region, the resistor structure and the first thermal trace being located at the same level in the plurality of first metallization structures, the resistor structure and the first thermal trace being made of a first metallic material, the first metallic material being different from the material of the plurality of first metallization structures, and the thermal conductivity of the first thermal trace being higher than the thermal conductivity of the first insulating material. A second wafer is provided having a plurality of second dies, each second die having a second device region and a second peripheral region adjacent to the second device region. The second die includes a plurality of second metallization structures embedded in a second insulating material. Each second metallization structure includes a capacitor structure located in a second peripheral region and a plurality of second thermal traces located in a second device region. The capacitor structure and the plurality of second thermal traces are located at the same level within the plurality of second metallization structures. The capacitor structure and the plurality of second thermal traces are made of a second metal material, which is different from the material of the plurality of second metallization structures. The thermal conductivity of the plurality of second thermal traces is higher than that of the second insulating material. The first wafer and the second wafer are joined via a first bonding structure and a second bonding structure to form a semiconductor structure.

[0113] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor die having a first region and a second region located adjacent to the first region, wherein the semiconductor die includes: The device layer is located in the second region; Insulating material, located above the device layer and extending over the first and second regions; and Multiple metallized structures are embedded in the insulating material and electrically connected to the device layer, and The plurality of metallized structures include a plurality of passive device structures located in the first region and a plurality of thermal traces located in the second region. The plurality of passive device structures and the plurality of thermal traces are made of the same material and are located at the same level as the plurality of metallized structures. The plurality of passive device structures are electrically connected to the device layer, and the plurality of thermal traces are electrically floating.

2. The semiconductor structure according to claim 1, characterized in that, The thermal conductivity of the multiple thermal traces is higher than that of the insulating material.

3. The semiconductor structure according to claim 2, characterized in that, The plurality of passive device structures include resistors and capacitors, and the plurality of thermal traces include a first thermal trace flush with the resistors and a second thermal trace flush with the capacitors. The first thermal trace and the resistors are made of a first metal material, and the second thermal trace and the capacitors are made of a second metal material.

4. The semiconductor structure according to claim 3, characterized in that, The first and second metallic materials are different from the materials of the plurality of metallized structures.

5. The semiconductor structure according to claim 1, characterized in that, It also includes multiple heat pipes located in the second region and connected to the multiple heat traces.

6. A semiconductor structure, characterized in that, include: A first die has a first device region and a first peripheral region located adjacent to the first device region, wherein the first die includes: A first insulating material is located above and extends over the first device area and the first peripheral area; and Multiple first metallization structures are embedded in the first insulating material, and The plurality of first metallized structures include a resistor structure located in the first peripheral region and a first thermal trace located in the first device region. The resistor structure and the first thermal trace are located at the same level in the plurality of first metallized structures. The resistor structure and the first thermal trace are made of a first metallic material, which is different from the material of the plurality of first metallized structures. The thermal conductivity of the first thermal trace is higher than that of the first insulating material. A second die, stacked on and engaged with the first die, wherein the second die has a second device region and a second peripheral region adjacent to the second device region, the second die comprising: A second insulating material is located above and extends over the second device area and the second peripheral area; and Multiple second metallization structures are embedded in the second insulating material, and The plurality of second metallization structures include a capacitor structure located in the second peripheral region and a plurality of second thermal traces located in the second device region. The capacitor structure and the plurality of second thermal traces are located at the same level in the plurality of second metallization structures. The capacitor structure and the plurality of second thermal traces are made of a second metal material, which is different from the material of the plurality of second metallization structures. The thermal conductivity of the plurality of second thermal traces is higher than that of the second insulating material.

7. The semiconductor structure according to claim 6, characterized in that, The first thermal trace is electrically levitated, and the plurality of second thermal traces are electrically levitated.

8. The semiconductor structure according to claim 6, characterized in that, The resistivity of the first metallic material is higher than that of the materials of the plurality of first metallized structures.

9. The semiconductor structure according to claim 6, characterized in that, The first thermal trace is spaced apart from and separated from the resistor structure, and is electrically isolated from the resistor structure through the first insulating material, while the resistor structure is electrically connected to the plurality of first interconnect structures of the plurality of first metallized structures.

10. The semiconductor structure according to claim 6, characterized in that, The plurality of second thermal traces are spaced apart from and separated from the capacitor structure, and are electrically isolated from the capacitor structure through the second insulating material. The capacitor structure is electrically connected to the plurality of second interconnect structures of the plurality of second metallized structures.

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