Fan-out wafer level packaging structure

Abstract

The utility model provides a fan-out type wafer level packaging structure which comprises a reconstructed wafer, a second chip, a third chip and a fourth chip, the second chip, the third chip and the fourth chip are integrated on the reconstructed wafer, and the second chip is stacked on the top of the reconstructed wafer in the vertical direction. The active surface of the second chip is electrically connected with the first chip through the upper surfaces of the left conductive bump and the right conductive bump; the third chip is integrated on the left side of the reconstructed wafer, and the third chip is provided with a first conductive through hole; the fourth chip is integrated on the right side of the reconstructed wafer, and the fourth chip is provided with a second conductive through hole; the bottom of the reconstructed wafer is provided with a second rewiring metal layer, the surface of the second rewiring metal layer is provided with a plurality of solder balls, and the plurality of chips are electrically connected with an external circuit through the solder balls. According to the packaging structure, more chips and functional modules are integrated in a limited packaging space, the overall size of the packaging structure is obviously reduced, vertical interconnection among a plurality of integrated chips is also realized, and signal transmission is more stable and reliable.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor packaging technology, and specifically relates to a fan-out wafer-level packaging structure. Background Technology

[0002] Traditional packaging technologies have reached a bottleneck in miniaturization, making it difficult to meet the current market's urgent demand for thinner, lighter, and smaller products. This limits the further application and development of electronic products in wearable devices, mobile devices, and other fields.

[0003] Furthermore, in high-speed signal transmission, traditional packaging struggles to effectively handle the demands of high-frequency signal transmission, resulting in significant signal delay and loss, which negatively impacts the overall performance and user experience of the packaged product. This issue is particularly pronounced in applications such as 5G communication and high-speed data transmission.

[0004] In addition, in terms of system integration, traditional packaging technology is difficult to achieve effective integration and modular design of complex systems, which is not conducive to the development of electronic products towards multifunctionality and high integration.

[0005] Therefore, there is an urgent need for a fan-out wafer-level packaging structure that can solve the above problems. Summary of the Invention

[0006] The purpose of this invention is to provide a fan-out wafer-level packaging structure that can significantly reduce the overall size of the package, significantly reduce the signal transmission delay between chips, and integrate more chips within a limited package space.

[0007] To achieve the above objectives, this utility model provides a fan-out wafer-level packaging structure, comprising:

[0008] The reconstructed wafer has a first chip with its active side facing upwards and exposed, and the other sides of the first chip are provided with an insulating layer; the active side of the first chip is provided with a first redistribution metal layer, and the first redistribution metal layer has a left conductive bump on the left side and a right conductive bump on the right side; the end of the left conductive bump extends to the left end of the reconstructed wafer, and the end of the right conductive bump extends to the right end of the reconstructed wafer.

[0009] The second chip is stacked vertically on top of the reconstructed wafer. The active surface of the second chip is electrically connected to the first chip through the upper surfaces of the left and right conductive bumps.

[0010] The third chip is integrated on the left side of the reconstructed wafer. The third chip has a first conductive via, which has a first side interface and a first bottom interface. The first side interface is connected to the side surface of the left conductive bump.

[0011] The fourth chip is integrated on the right side of the reconstructed wafer. The fourth chip has a second conductive via, which has a second side interface and a second bottom interface. The second side interface is connected to the side surface of the right conductive bump.

[0012] The reconstructed wafer has a second redistribution metal layer at its bottom, and a plurality of solder balls on the surface of the second redistribution metal layer. The first bottom interface and the second bottom interface are respectively connected to the solder balls, and the plurality of chips are electrically connected to external circuits through the solder balls.

[0013] Preferably, the first chip is a single chip cut from an incoming wafer, and the insulating layer is an insulating film that is pressed onto the other sides of the first chip.

[0014] Preferably, a substrate wafer is provided at the bottom of the reconstruction wafer, and a second redistribution metal layer is provided on the surface of the substrate wafer.

[0015] Preferably, both the left conductive bump and the right conductive bump are rectangular.

[0016] Preferably, the third chip forms a first conductive via in the silicon wafer, and the fourth chip forms a second conductive via in the silicon wafer. The first and second conductive vias enable the shortest possible interconnection between the third and fourth chips and other chips, reducing interconnection length, lowering signal transmission delay between chips, and making signal transmission more stable and reliable.

[0017] Preferably, the first side interface is disposed on the side surface of the left conductive bump, and the second side interface is disposed on the side surface of the right conductive bump.

[0018] Preferably, the fan-out wafer-level packaging structure further includes a molding compound, which molding compounds the reconstructed wafer, the second chip, the third chip, and the fourth chip.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The packaging structure of this utility model enables the integration of more chips and functional modules within a limited packaging space, significantly reducing the overall size of the packaging structure.

[0021] 2. This utility model discloses that through TSV (Through Silicon Via) technology, vertical interconnection between multiple integrated chips is achieved, reducing the interconnection length and thus significantly reducing the signal transmission delay between chips, making signal transmission more stable and reliable. Attached Figure Description

[0022] Figure 1 A schematic diagram of the reconstructed wafer structure in this invention is shown;

[0023] Figure 2A schematic diagram of the structure of the first chip is shown;

[0024] Figure 3 A schematic diagram of a structure in which a first redistribution metal layer is disposed on a first chip is shown.

[0025] Figure 4 A schematic diagram of the reconstructed wafer integrating the third and fourth chips is shown;

[0026] Figure 5 A schematic diagram of the structure of the reconstructed wafer integrating the second chip is shown;

[0027] Figure 6 A schematic diagram of a fan-out wafer-level packaging structure is shown. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings.

[0029] This invention provides a fan-out wafer-level packaging structure, comprising a reconfigured wafer 1, a second chip 2, a third chip 3, and a fourth chip 4. This structure integrates more chips and functional modules within a limited packaging space, significantly reducing the overall size of the packaging structure. The fan-out wafer-level packaging structure is described in detail below.

[0030] The structural schematic diagram of reconstructed wafer 1 is shown below. Figure 1 As shown, it has a first chip 101. The active surface 1010 of the first chip 101 is exposed facing upwards, and the other surfaces of the first chip 101 are provided with an insulating layer 102; the active surface 1010 of the first chip 101 is provided with a first redistribution metal layer 103, the first redistribution metal layer 103 is provided with a left conductive bump 104 on the left side and a right conductive bump 105 on the right side; the end of the left conductive bump 104 extends to the left end of the reconstructed wafer 1, and the end of the right conductive bump 105 extends to the right end of the reconstructed wafer 1.

[0031] A schematic diagram of the structure of the first chip 101 is shown below. Figure 2 As shown, the first chip 101 is a single chip produced after the incoming wafer is diced. Generally, a diamond blade is used to physically dice the incoming wafer to form the first chip 101, while water is used to cool the blade and the wafer, reducing heat damage and removing debris generated during dicing. Figure 3As shown, the first chip 101 is then flip-chipped onto a carrier wafer 108 with a TBF temporary bonding film 107 attached using a DA flip-chip machine (the carrier wafer 108 and the TBF temporary bonding film 107 need to be removed in later processes). The insulating layer 102 in this application is an insulating film, pressed onto other surfaces of the first chip 101 (except for the active surface 1010 of the first chip 101). The insulating layer 102 can be an ABF insulating film. Specifically, the ABF insulating film is pressed onto the first chip 101 using a laminator, and then a substrate wafer 106 is bonded to the surface of the insulating layer 102 on the bottom surface of the first chip 101 (the active surface 1010 of the first chip 101 is the top surface). That is, the substrate wafer 106 is located at the bottom of the reconstructed wafer 1 to increase the overall rigidity of the reconstructed wafer 1 and enhance its reliability.

[0032] Finally, thermal bonding is performed to remove the carrier wafer 108 and the TBF temporary bonding film 107. After integrating multiple chips, a second redistribution metal layer 5 is formed on the surface of the substrate wafer 106, which increases the overall strength and reliability of the fan-out wafer-level packaging structure.

[0033] In the reconstructed wafer 1, the active surface 1010 of the first chip 101 is provided with a first redistribution metal layer 103. Specifically, photoresist is coated on the active surface 1010 of the first chip 101, and a pattern opening is made by photolithography or laser process using a mask to form a passivation layer; a photoresist layer is coated again, and a metal layer pattern opening is made by photolithography or laser process using a mask; electroplating is performed in the metal layer pattern opening to form the first redistribution metal layer 103.

[0034] Repeat the above steps to prepare a left conductive bump 104 on the left side of the first rewiring metal layer 103 and a right conductive bump 105 on the right side, forming a structure as shown above. Figure 1 The structure of the reconstructed wafer 1 is shown. In this application, both the left conductive bump 104 and the right conductive bump 105 are made into rectangles, with the end of the left conductive bump 104 extending to the left end of the reconstructed wafer 1 and the end of the right conductive bump 105 extending to the right end of the reconstructed wafer 1. Specifically, the positions of the left conductive bump 104 and the right conductive bump 105 are designed at the dicing track. During dicing, excess left conductive bump 104 and right conductive bump 105 are cut off, thereby forming Sn / SnAg and Cu exposed on the sidewall of the reconstructed wafer 1 (i.e., the side surface 1041 of the left conductive bump 104 and the side surface 1051 of the right conductive bump 105), thus achieving the effect of solder creep on the sidewall of the reconstructed wafer 1, facilitating subsequent connection with other integrated chips. The left conductive bump 104 also has an upper surface 1040, and the right conductive bump 105 also has an upper surface 1050, which are also used for connection with other chips.

[0035] Prepare a third chip 3 and a fourth chip 4 with through-silicon vias (TSVs), and integrate them on the left and right sides of the reconstructed wafer 1, respectively, to form a structure as shown below. Figure 4 The structure shown is as follows. The third chip 3 and the fourth chip 4 with through-silicon vias (TSVs) refer to the third chip 3 having a first conductive via 301 formed in the silicon wafer, and the fourth chip 4 having a second conductive via 401 formed in the silicon wafer. Through-silicon via technology is existing technology and will not be described in detail here.

[0036] The third chip 3 is integrated on the left side of the reconstructed wafer 1, and the fourth chip 4 is integrated on the right side of the reconstructed wafer 1. Unlike existing through-silicon vias (TSVs), the first conductive via 301 of the third chip 3 has a first side interface 302 and a first bottom interface 303. The first side interface 302 connects to the side surface 1041 of the left conductive bump 104. The second conductive via 401 of the fourth chip 4 has a second side interface 402 and a second bottom interface 403. The second side interface 402 connects to the side surface 1051 of the right conductive bump 105. During positioning, the first side interface 302 is correspondingly positioned on the side surface 1041 of the left conductive bump 104, and the second side interface 402 is correspondingly positioned on the side surface 1051 of the right conductive bump 105. Through the first conductive via 301 and the second conductive via 401, the shortest possible interconnection between the third chip 3, the fourth chip 4, and other chips can be achieved, reducing the interconnection length, lowering the signal transmission delay between chips, and making signal transmission more stable and reliable.

[0037] like Figure 5 As shown, a second chip 2 is bonded to the top of the reconstructed wafer 1, which integrates the third chip 3 and the fourth chip 4, using TCB (thermal pressure bonding) technology. This allows the second chip 2 to be stacked vertically on top of the reconstructed wafer 1. The active surface of the second chip 2 is electrically connected to the first chip 101, the third chip 3, and the fourth chip 4 through the upper surface 1040 of the left conductive bump 104 and the upper surface 1050 of the right conductive bump 105.

[0038] like Figure 6 As shown, the bottom of the reconstructed wafer 1 has a second redistribution metal layer 5, and the surface of the second redistribution metal layer 5 has multiple solder balls 6. The first bottom interface 303 and the second bottom interface 403 are respectively connected to the solder balls 6, and multiple chips are electrically connected to external circuits through the solder balls 6. Thus, three different chips are packaged on both sides and the front side of the reconstructed wafer 1. Combined with the first chip 101 in the reconstructed wafer 1, a multi-chip fan-out wafer-level packaging structure is formed. This integrates more chips and functional modules within a limited packaging space, significantly reducing the overall size of the packaging structure and demonstrating stronger performance.

[0039] The fan-out wafer-level packaging structure also includes a molding compound 7, which molds and reassembles the reconstructed wafer 1, the second chip 2, the third chip 3, and the fourth chip 4. Specifically, it uses a reheat molding compound, which changes the adhesive material from a solid to a liquid state. The liquid molding compound is injected into the mold under pressure from a liquid molding device, and begins to solidify under continuous high temperature. This protects the chips from external environmental damage and ensures reliable electrical connections between the chips in the package structure.

[0040] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A fan-out wafer level packaging structure, characterized in that, include: The reconstructed wafer has a first chip with its active side facing upwards and exposed, and the other sides of the first chip are provided with an insulating layer; the active side of the first chip is provided with a first redistribution metal layer, and the first redistribution metal layer has a left conductive bump on the left side and a right conductive bump on the right side; the end of the left conductive bump extends to the left end of the reconstructed wafer, and the end of the right conductive bump extends to the right end of the reconstructed wafer. The second chip is stacked vertically on top of the reconstructed wafer. The active surface of the second chip is electrically connected to the first chip through the upper surfaces of the left and right conductive bumps. The third chip is integrated on the left side of the reconstructed wafer. The third chip has a first conductive via, which has a first side interface and a first bottom interface. The first side interface is connected to the side surface of the left conductive bump. The fourth chip is integrated on the right side of the reconstructed wafer. The fourth chip has a second conductive via, which has a second side interface and a second bottom interface. The second side interface is connected to the side surface of the right conductive bump. The reconstructed wafer has a second redistribution metal layer at its bottom, and a plurality of solder balls on the surface of the second redistribution metal layer. The first bottom interface and the second bottom interface are respectively connected to the solder balls, and the plurality of chips are electrically connected to external circuits through the solder balls.

2. The fan-out wafer level package structure of claim 1, wherein, The first chip is a single chip cut from an incoming wafer, and the insulating layer is an insulating film that is pressed onto the other sides of the first chip.

3. The fan-out wafer level package structure of claim 2, wherein, The bottom of the reconstructed wafer is provided with a substrate wafer, and a second redistribution metal layer is disposed on the surface of the substrate wafer.

4. The fan-out wafer level package structure of claim 1, wherein, Both the left and right conductive bumps are rectangular.

5. The fan-out wafer level package structure of claim 1, wherein, The third chip forms a first conductive via in the silicon wafer, and the fourth chip forms a second conductive via in the silicon wafer.

6. The fan-out wafer level package structure of claim 5, wherein, The first side interface is disposed on the side surface of the left conductive bump, and the second side interface is disposed on the side surface of the right conductive bump.

7. The fan-out wafer level package structure of any one of claims 1-6, wherein, It also includes a molding compound, which molds and reconstructs the wafer, the second chip, the third chip, and the fourth chip.

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