Semiconductor package

Abstract

The utility model provides a packaging structure. The package structure includes an interposer substrate, a first semiconductor die, a second semiconductor die, an underfill, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are disposed on the interposer substrate. The underfill is disposed between the first semiconductor die and the interposer substrate. The insulating encapsulant is disposed on the interposer substrate. The insulating encapsulation includes a first portion and a second portion. The first portion laterally encapsulates the first semiconductor die and the second semiconductor die. The second portion is disposed between the second semiconductor die and the interposer substrate.

Description

Technical Field

[0001] The embodiments of this utility model relate to a semiconductor package. Background Technology

[0002] The electronics industry's demand for smaller, faster electronic components capable of supporting a greater number and increasingly complex and sophisticated functions is constantly growing. To meet these demands, there is an ongoing trend in the integrated circuit (IC) industry to improve the packing density of various semiconductor components and / or electronic components. This can be achieved by reducing IC size (for example, reducing the minimum feature size of the IC), allowing for the integration of various types of functional components into a given area. However, this scaling also increases the complexity of IC manufacturing processes. Therefore, semiconductor chips require more advanced packaging technologies to enable the continued advancement of IC components. Utility Model Content

[0003] According to some embodiments disclosed herein, a structure is provided including an intermediate substrate, a first semiconductor die, a second semiconductor die, an underfill, and an insulating encapsulator. The first and second semiconductor dies are disposed on the intermediate substrate. The underfill is disposed between the first semiconductor die and the intermediate substrate. The insulating encapsulator includes a first portion and a second portion, the first portion covering the second portion, the first portion laterally encapsulating the first and second semiconductor dies, and the second portion being disposed between the second semiconductor die and the intermediate substrate.

[0004] According to some embodiments disclosed herein, a structure is provided including an intermediate substrate, a first semiconductor die, a second semiconductor die, and an insulating encapsulator. The first and second semiconductor dies are disposed on the intermediate substrate. The first semiconductor die includes a first conductive terminal, and the second semiconductor die includes a second conductive terminal. The insulating encapsulator is disposed on the intermediate substrate, wherein the insulating encapsulator laterally covers the first semiconductor die, the second semiconductor die, and the second conductive terminal. Attached Figure Description

[0005] The aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various components may be arbitrarily increased or decreased.

[0006] Figures 1 to 5 , Figure 7 as well as Figures 9 to 10 The diagram illustrates a cross-sectional view of the structure produced at various stages of a semiconductor packaging manufacturing method according to some embodiments of this disclosure.

[0007] Figure 6A and Figure 6BA cross-sectional schematic diagram illustrating the process flow for manufacturing an insulating encapsulation according to some embodiments of this disclosure is shown.

[0008] Figure 8A and Figure 8B A cross-sectional schematic diagram of the process flow for manufacturing an insulating encapsulation according to some alternative embodiments of this disclosure is shown.

[0009] Figure 11 A schematic cross-sectional view of a semiconductor package connected to a packaging substrate is shown in some embodiments according to this disclosure.

[0010] Figure 12 An enlarged cross-sectional schematic diagram is shown, illustrating a plurality of openings disposed in the second region of the intermediate substrate and located on the insulating encapsulator according to the present disclosure. Detailed Implementation

[0011] This disclosure generally relates to a semiconductor package and a method for manufacturing semiconductors.

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein shall be interpreted accordingly.

[0014] In addition, for ease of description, terms such as "first," "second," "third," "fourth," and similar terms may be used in this article to describe similar or different components or features in the figure, and these terms may be used interchangeably, depending on the order of appearance or the context of the description.

[0015] In some embodiments, the manufacturing method is part of a wafer-level packaging process. It should be understood that additional processes may be provided before, during, and after the method, and only a few other processes are briefly described herein. In this disclosure, it should be understood that all components depicted in the figures are schematic and not drawn to scale. Components similar to or substantially similar to those previously described in the various views and illustrative embodiments of this disclosure will use the same reference numerals, and certain details of the same components described (e.g., materials, forming processes, positioning architectures, electrical connections, etc.) will not be repeated. For clarity of illustration, the figures are drawn using orthogonal axes (X-axis, Y-axis, and Z-axis) of a Cartesian coordinate system, with the figures oriented accordingly; however, this disclosure is not limited thereto.

[0016] To reduce warpage and prevent bridging of solder joints in semiconductor packages, various novel package structures and methods of manufacturing thereof are provided according to various embodiments. In the various views and exemplary embodiments, the same reference numerals are used to refer to the same components.

[0017] Figures 1 to 5 , Figure 7 as well as Figures 9 to 10 The diagram illustrates a cross-sectional view of the structure produced at various stages of a semiconductor packaging manufacturing method according to some embodiments of this disclosure.

[0018] refer to Figure 1An intermediate substrate 100 is provided. The intermediate substrate 100 includes a first region 100a and a second region 100b. At least one first semiconductor die 110 is provided and disposed on the first region 100a of the intermediate substrate 100. The first semiconductor die 110 is electrically connected to the intermediate substrate 100 via a first conductive terminal 120. The first conductive terminal 120 includes a first conductive bump 122 contacting the top surface 100s of the intermediate substrate 100, a second conductive bump 124 contacting the bottom surface of the first semiconductor die 110, and a solder region 126 located between the first conductive bump 122 and the second conductive bump 124. The intermediate substrate 100 further includes a first conductive post 102 and the first conductive post 102 is disposed on the second region 100b of the intermediate substrate 100. In some embodiments, the intermediate substrate 100 includes an organic intermediate substrate or an inorganic intermediate substrate. For example, the inorganic interposer substrate 100 described above may be or include a semiconductor interposer substrate (e.g., a silicon interposer substrate 100) or other suitable interposer substrates. Taking a semiconductor interposer substrate as an example, the interposer substrate 100 may include a semiconductor substrate 101, such as a silicon substrate in wafer form, wherein first conductive pillars 102 and first conductive bumps 122 are distributed on the top surface of the silicon substrate 101 (i.e., the top surface 100s of the interposer substrate 100). In some embodiments, the interposer substrate 100 further includes through-semiconductor vias (e.g., silicon vias) penetrating the semiconductor substrate 101. In some embodiments, the interposer substrate 100 is an active interposer substrate in which active components (e.g., transistors) and passive components (e.g., resistors, capacitors, and / or sensors) are integrated. In some embodiments, the interposer substrate 100 is an interposer substrate with vias, and no active components (e.g., transistors) and passive components (e.g., resistors, capacitors, and / or sensors) are formed in the interposer substrate 100.

[0019] In some embodiments, the first conductive bump 122, the second conductive bump 124, and the first conductive post 102 comprise copper, a copper alloy, or other conductive materials, and the first conductive bump 122, the second conductive bump 124, and the first conductive post 102 may be formed by deposition (e.g., electroplating) or other suitable techniques. In some embodiments, the solder region 126 comprises eutectic solder or non-eutectic solder, and the solder region 126 may be lead or lead-free, and may comprise Sn-Ag, Sn-Cu, Sn-Ag-Cu, or similar materials. In some embodiments, forming the first conductive bump 122, the second conductive bump 124, and the first conductive pillar 102 includes a seed layer deposition process, a photoresist layer formation on the seed layer, a patterning process (e.g., photolithography) to form an opening in the photoresist layer, a deposition process to form conductive material in the opening of the patterned photoresist layer, a removal process of the patterned photoresist layer (e.g., photoresist stripping process), and a removal process (e.g., etching process) to remove the portion of the seed layer not covered by conductive material. In some embodiments, the formed first conductive bump 122 and the first conductive pillar 102 have substantially the same height. The height h1 of the first conductive pillar 102 is the same as the height h2 of the first conductive bump 122, and the heights h1 and h2 can be in the range of about 10 micrometers to about 70 micrometers. In some embodiments, the formed first conductive pillar 102 and the first conductive terminal 120 can have different heights. The height h3 of the first conductive terminal 120 is higher than the height h1 of the first conductive pillar 102 and the height h2 of the first conductive bump 122. However, this disclosure is not limited to the first conductive post 102 with height h1, the first conductive bump 122 with height h2, and the first conductive terminal 120 with height h3. The heights h1, h2, and h3 can be adjusted according to design or production requirements.

[0020] In some embodiments, the intermediate substrate 100 further includes a redistribution circuit structure 104, wherein the redistribution circuit structure 104 is electrically connected to the first conductive bump 122 and the first conductive post 102 through a through-semiconductor via (not shown) embedded in the semiconductor substrate 101. Figure 1 As shown, the redistributed circuit structure 104 is distributed on the bottom surface of the intermediate substrate 100, and the bottom surface of the substrate 100 is opposite to the top surface 100s of the intermediate substrate 100. In some embodiments, an intermediate substrate 100 including a first conductive bump 122, a first conductive post 102, and the redistributed circuit structure 104 is provided. Then, a first semiconductor die 110 including a second conductive bump 124 and a solder region 126 is provided on the intermediate substrate 100. Through proper alignment, the solder region 126 can be aligned and contacted with the first conductive bump 122. Then, a reflow process can be performed so that the first conductive bump 122 is bonded to the second conductive bump 124 through the molten solder region 126.

[0021] like Figure 1 As shown, two first semiconductor dies 110 are illustrated to represent multiple dies, but the number of dies in a semiconductor package is not limited to this embodiment. Each first semiconductor die 110 may be a logic die, such as a central processing unit (CPU) die, a graphics processing unit (GPU) die, a microcontroller unit (MCU) die, an input / output (I / O) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, at least one of the first semiconductor dies 110 includes a memory die, such as a high-bandwidth-memory (HBM) die. In some embodiments, the first semiconductor dies 110 may be dies of the same type or performing the same function. In some embodiments, the first semiconductor dies 110 may be dies of different types or performing different functions. In some embodiments, the first semiconductor die 110 includes both logic dies and memory dies.

[0022] refer to Figure 2 After providing a first semiconductor die 110 over a first region 100a of the intermediate substrate 100 and electrically connecting the first semiconductor die 110 to the first region 100a of the intermediate substrate 100 via a first conductive terminal 120, an underfill 130 can be formed between the first semiconductor die 110 and the first region 100a of the intermediate substrate 100, and the underfill 130 laterally covers the first conductive terminal 120. The underfill 130 at least fills the gap between the first region 100a of the intermediate substrate 100 and the first semiconductor die 110, and the underfill 130 may cover the sidewalls of the first conductive terminal 120. The material of the underfill 130 includes molding compounds, resins, polymers, oxide materials, nitride materials, or combinations thereof. In some embodiments, the underfill 130 may be or include epoxy resin. The underfill 130 can be formed by underfill dispensing, a capillary flow process, or any other suitable method. In some embodiments, for example, an underfill 130 is dispensed into the gap between the first semiconductor die 110 and the first region 100a of the intermediate substrate 100 using a dispensing needle or other suitable dispensing tool, and then cured until hardened. The underfill 130 enhances the bonding strength between the first semiconductor die 110 and the intermediate substrate 100.

[0023] refer to Figure 3After the bottom filler 130 is formed, an insulating encapsulation 140 is formed on the intermediate substrate 100, such as... Figure 2 As shown. The insulating encapsulation 140 includes a first portion 140a and a second portion 140b. The first portion 140a of the insulating encapsulation 140 covers the second portion 140b of the insulating encapsulation 140 and the first conductive post 102. The first portion 140a of the insulating encapsulation 140 is in contact with the top surface of the first conductive post 102, and the second portion 140b of the insulating encapsulation 140 is in contact with the sidewall of the first conductive post 102. The first portion 140a laterally encapsulates the first semiconductor die 110. The second portion 140b of the insulating encapsulation 140 is disposed between the first portion 140a and the top surface 100s of the intermediate substrate 100, and laterally encapsulates the first conductive post 102. The insulating encapsulation 140 at least fills the gaps between the first semiconductor grains 110, the gaps between the underfill 130 below the first semiconductor grains 110, and the gap between the underfill 130 and the first conductive post 102, and the insulating encapsulation 140 may also surround and cover the first conductive post 102. In some embodiments, the insulating encapsulation 140 may be formed, for example, by molding, transfer molding, compression molding, liquid encapsulation molding, etc. In some embodiments, the insulating encapsulation 140 includes epoxy resin, phenolic resin, silicone resin, dielectric material, or other suitable material.

[0024] refer to Figure 4 In such Figure 3 After the insulating encapsulation 140 is formed on the intermediate substrate 100 shown, the insulating encapsulation 140 is partially removed or planarized, for example, by mechanical polishing, chemical mechanical polishing (CMP), etching, or a combination thereof. Planarization can also make the top surface 112 of the first semiconductor die 110 substantially flush with the top surface 142 of the insulating encapsulation 140. As shown in the figure Figure 4 The top surface 142 of the insulating encapsulant 140 is substantially flush with the top surface 112 of the first semiconductor die 110.

[0025] refer to Figure 5 In some embodiments, located as Figure 4A portion of the insulating encapsulation 140 at the second region 100b of the intermediate substrate 100 is partially removed or trimmed to form a remaining portion 146 of the insulating encapsulation 140, which covers the second region 100b of the intermediate substrate 100. For example, above the second region 100b of the intermediate substrate 100, a contact cutting process is used to partially remove or trim the insulating encapsulation 140 from its top surface 142. In some embodiments, the contact cutting process may be performed by a mechanical cutting process (e.g., blade cutting). The removal or trimming process may remove the insulating encapsulation 140 to create a new surface 144 that is below the top surface 142 of the insulating encapsulation 140 and above the first region 100a of the intermediate substrate 100. In some embodiments, the thickness h4 of the insulating encapsulation 140 remains constant at the second region 100b of the intermediate substrate 100.

[0026] refer to Figure 6A and Figure 6B In alternative embodiments, the insulating encapsulation 140 may be formed on the intermediate substrate 100 by an over-molding process followed by a planarization process. In some embodiments, the intermediate substrate 100 includes a first region 100a and a second region 100b. The intermediate substrate 100 includes a first conductive bump 122, a first conductive post 102, and a redistributed wiring structure 104. The molding process may be performed in a forming assembly (not shown) including a mold chase 160. Figure 6A As shown, a mold sleeve 160 is disposed above an intermediary substrate 100, a first semiconductor die 110 is disposed on a first region 100a of the intermediary substrate 100, and a first conductive post 102 is disposed on a second region 100b of the intermediary substrate 100. The mold sleeve 160 disposed above the top surface 100s of the intermediary substrate 100 may have a predetermined shape or structure to maintain the shape of the insulating encapsulation 140 during application. In some embodiments, the mold sleeve 160 disposed above the top surface 100s of the intermediary substrate 100 may have different heights. In some embodiments, the mold sleeve 160 includes a protrusion 160P projecting from the mold sleeve 160 into the second region 100b of the intermediary substrate 100. In some embodiments, the protrusion 160P is disposed above the first conductive post 102 or adjacent to the first semiconductor die 110. In some embodiments, the mold sleeve 160 comprises steel or the like.

[0027] like Figure 6AAs shown, an insulating encapsulation 140 is disposed between a mold sleeve 160 and an intermediate substrate 100. In some embodiments, the space defined by the mold sleeve 160, the first semiconductor die 110, and the first conductive post 102 is filled by the insulating encapsulation 140. In some embodiments, the insulating encapsulation 140 includes a molding compound, a molding underfill, epoxy resin, or the like. In some embodiments, a curing process may be performed to cure the insulating encapsulation 140. In some embodiments, the mold sleeve 160 is removed after the insulating encapsulation 140 is formed. In some embodiments, the first conductive post 102 formed on a second region 100b of the intermediate substrate 100 is surrounded by the insulating encapsulation 140. In some embodiments, the first semiconductor die 110 formed on a first region 100a of the intermediate substrate 100 is laterally covered by the insulating encapsulation 140.

[0028] like Figure 6B As shown, in some embodiments, the molding process includes forming a recess 180 over the second region 100b of the intermediate substrate 100. In some embodiments, the top surface 148 of the insulating package 140 located in the second region 100b of the intermediate substrate 100 is not coplanar with the top surface 142 of the insulating encapsulation 140 located in the first region 100a of the intermediate substrate 100. In some embodiments, the sidewalls 180s of the recess 180 are... Figure 6A The outer surface of the protrusion 160P of the mold sleeve 160 shown is conformal. In some embodiments, the recess 180 is adjacent to the first semiconductor die 110. In some embodiments, the insulating encapsulation 140 formed in the second region 100b of the intermediate substrate 100 and located above the first conductive pillar 102 has a thickness h5. In some embodiments, the thickness h4 of the insulating encapsulation 140 (shown in the figure) Figure 5 ) and thickness h5 (drawn in Figure 6B These are independent of each other, ranging from 10 to 30 micrometers, but this disclosure is not limited to this. Thickness h4 (illustrated on...) Figure 5 Thickness h5 (drawn in) Figure 6B The design or performance requirements can be adjusted. The encapsulated intermediate substrate 100 and insulating encapsulator 140 can undergo additional post-molding or patterning processes in subsequent process steps. Although only one package is shown, it should be understood that package arrays comprising multiple intermediate substrates 100 can be fabricated simultaneously in strip or array architectures, which are then separated or monolithized in subsequent steps.

[0029] refer to Figure 7 In some embodiments, according to such Figure 5 and Figure 6B The insulating encapsulation 140 formed in the second region 100b of the intermediate substrate 100, as illustrated in the process, can be further patterned to form a plurality of openings 200 at the second region 100b of the intermediate substrate 100 on the top surfaces 144, 148 of the insulating encapsulation 140, thereby exposing the top surface 102s of the underlying first conductive pillar 102. For example, the insulating encapsulation 140 can be patterned by etching, polishing, laser technology, or a combination thereof. In some embodiments, the insulating encapsulation 140 can be patterned using, for example, a laser drilling process. For example, those portions of the insulating encapsulation 140 to which the laser is directed will be removed to expose the top surface 102s of the underlying first conductive pillar 102. During the laser drilling process, the drill energy can range from 0.1 mJ / mm². 2 Up to approximately 1.0 mJ / mm 2 Within a certain range, the drill angle can be approximately 0 degrees (perpendicular to the top surfaces 144, 148 of the insulating encapsulation 140) perpendicular to the normals of the top surfaces 144, 148 of the insulating encapsulation 140. Patterning can be performed to form a plurality of openings 200 on the insulating encapsulation 140. The openings 200 can penetrate the insulating encapsulation 140 in the Z direction and extend toward the top surface 100s of the intermediate substrate 100.

[0030] refer to Figure 8A and Figure 8B In an alternative embodiment, the insulating encapsulation 140 may be formed on the intermediate substrate 100 by a molding process. The molding process is the same as described above. Figure 6A and Figure 6B The illustrated process is similar. According to this embodiment, the size and shape of the mold sleeve 160 can be designed such that when the mold sleeve 160 is filled with the insulating encapsulant 140, the space defined by the mold sleeve 160 allows the insulating encapsulant 140 to be formed therein with the aforementioned size and shape. In some embodiments, the mold sleeve 160 includes a plurality of protrusions 160P' projecting from the mold sleeve 160 into a second region 100b of the intermediate substrate 100. This disclosure does not limit the shape of the mold sleeve 160 or the number of protrusions 160P', which can be specified and selected according to requirements and design layout. In some embodiments, each protrusion 160P' has a tapered profile, and the molding process results in a plurality of openings 200 being formed on the top surface 149 of the insulating encapsulant 140 to expose the top surface 102s of the first conductive post 102. In some embodiments, the openings 200 are formed on the top surface 100s of the intermediate substrate 100 via a mold patterning process, without the need for additional patterning steps, such as laser drilling. In some embodiments, the height of the protrusion 160P' of the mold sleeve 160 is substantially equal to the depth of the opening 200. For example... Figure 8B As shown, the sidewalls 200s and 200s' of the opening 200 of the insulating encapsulation 140 conform to the outer surface of the protrusion 160P' of the mold sleeve 160. In some embodiments, each opening 200 has two tapered sidewalls 200s and 200' and a horizontal bottom recessed surface 220 connecting the sidewalls 200s and 200'. Each opening 200 corresponds to a region where the solder area (not shown) will be set in subsequent process steps (solder area attachment location).

[0031] refer to Figure 9 After the top surface 102s of the first conductive post 102 is exposed by the insulating encapsulant 140, through such Figures 5 to 8A and Figure 8B The multiple steps illustrated involve forming a solder region 240 on the top surface 102s of the first conductive post 102. In some embodiments, the solder region 240 is disposed within an opening 200 formed in the insulating encapsulation 140, such that the periphery of the solder region 240 contacts the sidewalls 200s, 200s' of the opening 200, and the topmost surface 240s of the solder region 240 is exposed by the opening 200. Through the opening 200 formed in the insulating encapsulation 140, the solder region 240 formed within the opening 200 can be easily exposed by the insulating encapsulation 140, thereby facilitating the placement of the semiconductor die in subsequent steps.

[0032] refer to Figure 10 A second semiconductor die 260 is disposed on a second region 100b of the intermediate substrate 100. The second semiconductor die 260 is electrically connected to the intermediate substrate 100 through a second conductive terminal 340 formed between the top surface 100s and the bottom surface of the second semiconductor die 260. The second conductive terminal 340 includes a first conductive post 102 contacting the top surface 100s of the intermediate substrate 100, a second conductive pad 280 contacting the bottom surface of the second conductive die 260, and a solder region 240 located between the first conductive post 102 and the second conductive pad 280. Since the die bonding process of the second semiconductor die 260 is performed after the fabrication of the insulating encapsulation 140, air gaps may occur between the second semiconductor die 260 and the insulating encapsulation 140 distributed on the second region 100b of the intermediate substrate 100. Figure 10 As shown, the second semiconductor die 260 can be configured such that no underfill 130 is formed between the second semiconductor die 260 and the portion of the insulating encapsulant 140 distributed on the second region 100b of the intermediate substrate 100, but this disclosure is not limited thereto. Figure 10As shown, the second semiconductor die 260 and the insulating encapsulant 140 can be separated by an air gap. In some embodiments, the air gap may be formed between a plurality of second conductive pads 280 attached to the bottom surface of the second semiconductor die 260. In some other embodiments, the air gap may be further filled by another underfill. In some embodiments, the underfill 130 is omitted, for example, at the second region 100b of the interposer substrate 100, in which case the insulating encapsulant 140 occupies all the space between the second semiconductor die 260 and the second region 100b of the interposer substrate 100, and laterally covers the first conductive post 102 located in the second region 100b of the interposer substrate 100. In other words, in the second region 100b of the interposer substrate 100, the second conductive pads 280 may protrude into the opening 200 (e.g., Figure 7 or Figure 8B As shown in the figure, the insulating encapsulation 140 is in direct contact with the second semiconductor die 260.

[0033] like Figure 10 As shown, the sidewall of the second semiconductor die 260 is in contact with the insulating encapsulation 140. In some other embodiments, the second semiconductor die 260 is not in contact with the insulating encapsulation 140. In other words, the second semiconductor die 260 may be laterally spaced from the insulating encapsulation 140 by an air gap. Furthermore, the air gap laterally separating the second semiconductor die 260 from the insulating encapsulation 140 may be provided by another underfill (not shown in the diagram). Figure 10 (fill in the middle)

[0034] Then, a reflow process is performed to connect the first conductive post 102 on the top surface 100s of the dielectric substrate 100 to the first conductive pad 280 of the second semiconductor die 260. The reflow temperature and processing time of the reflow process can be optimized according to the composition of the first conductive post 102, the first conductive pad 280, and the solder area 240. In some embodiments, joint shifting can be reduced, and the second semiconductor die 260 is precisely attached to the intended position on the dielectric substrate 100. When better placement conditions can be achieved, packages with fine pitch or smaller form factor can be formed.

[0035] refer to Figure 10 and Figure 11After the die bonding process of the second semiconductor die 260, conductive bumps 320 can be formed on the bottom surface of the dielectric substrate 100, for example, through a wafer-level bumping process. Conductive bumps 320 can be formed on the bottom surface of the redistribution circuitry 104 of the dielectric substrate 100. Conductive bumps 320 can be or include controlled-collapse chip connection bumps (C4bumps). After forming the conductive bumps 320, a monomerization process can be performed to cleave the dielectric substrate 100 and the resulting structure formed thereon, thereby obtaining multiple monomerized semiconductor components.

[0036] like Figure 10 and Figure 11 As shown, a packaging substrate 300 is provided, and at least one of the aforementioned monolithic semiconductor components is disposed and mounted on the packaging substrate 300, such that conductive bumps 320 are sandwiched between the intermediate substrate 100 and the packaging substrate 300 to electrically connect the intermediate substrate 100 and the packaging substrate 300. The packaging substrate 300 may be a printed circuit board or other suitable type of wiring substrate. Additionally, conductive terminals (not shown) may be formed on the bottom surface of the packaging substrate 300. In some embodiments, the conductive terminals formed on the bottom surface of the packaging substrate 300 include solder balls (e.g., ball grid array (BGA) balls).

[0037] refer to Figure 12 Enlarged schematic cross-sectional views of multiple openings 200 are provided, and the openings 200 are formed in Figure 7 On the insulating encapsulation 140 in the second region 100b of the intermediate substrate 100. In some embodiments, the opening 200 may penetrate the insulating encapsulation 140 in the Z direction, and the opening 200 may extend further in the X direction from the edge 140e of the insulating encapsulation 140. In some embodiments, each opening 200 has two tapered sidewalls 200s, 200s' and a horizontal bottom recessed surface 220 located between the tapered sidewalls 200s, 200s'. The vertical depth d of each opening, measured in the Z direction, may be in the range of approximately 10 micrometers to approximately 30 micrometers. Figure 12 As shown, the horizontal bottom recessed surface 220 of each opening 200 is at the edge surface 140e of the insulating encapsulation 140. Figure 7The openings extend between the top surfaces 100s of the intermediate substrate 100 (e.g., not flush with the edge surface 140e). Each opening has a bottom horizontal width w1 and a top horizontal width w2 measured in the X direction. The bottom horizontal width w1 may differ from the top horizontal width w2. In some embodiments, the top horizontal width w2 is greater than the bottom horizontal width w1, wherein the top horizontal width w2 may be in the range of approximately 25 micrometers to approximately 50 micrometers, and the bottom horizontal width w1 may be in the range of approximately 20 micrometers to approximately 30 micrometers. In some embodiments, the top horizontal width w2 is greater than the maximum diameter of the solder area (not shown) to achieve more optimized placement of the solder area within the opening of the insulating encapsulation 140.

[0038] According to some embodiments disclosed herein, a structure is provided including an intermediate substrate, a first semiconductor die, a second semiconductor die, an underfill, and an insulating encapsulator. The first and second semiconductor dies are disposed on the intermediate substrate. The underfill is disposed between the first semiconductor die and the intermediate substrate. The insulating encapsulator includes a first portion and a second portion, the first portion covering the second portion, the first portion laterally encapsulating the first and second semiconductor dies, and the second portion being disposed between the second semiconductor die and the intermediate substrate. In some embodiments, the first semiconductor die is electrically connected to the intermediate substrate through a first conductive terminal located between the top surface of the intermediate substrate and the bottom surface of the first semiconductor die, and the second semiconductor die is electrically connected to the intermediate substrate through a second conductive terminal located between the top surface of the intermediate substrate and the bottom surface of the second semiconductor die. In some embodiments, the underfill laterally encapsulates the first conductive terminal, and the second portion of the insulating encapsulator laterally encapsulates the second conductive terminal. In some embodiments, the first conductive terminal includes a first conductive bump contacting the top surface of the intermediate substrate, a second conductive bump contacting the bottom surface of the first semiconductor die, and a plurality of solder areas located between the first conductive bump and the second conductive bump. The second conductive terminal includes a first conductive post contacting the top surface of the intermediate substrate, a second conductive post contacting the bottom surface of the second semiconductor die, and a plurality of solder areas located between the first conductive post and the second conductive pad. In some embodiments, the first conductive terminal is higher than the first conductive post, and the top surface of the first conductive bump is substantially flush with the top surface of the first conductive post. In some embodiments, the top surface of a first portion of the insulating encapsulation is substantially flush with the top surface of the first semiconductor die.

[0039] According to some embodiments of this disclosure, a structure including an intermediate substrate, a first semiconductor die, a second semiconductor die, and an insulating encapsulator is provided. The first and second semiconductor dies are disposed on the intermediate substrate. The first semiconductor die includes a first conductive terminal, and the second semiconductor die includes a second conductive terminal. The insulating encapsulator is disposed on the intermediate substrate, wherein the insulating encapsulator laterally covers the first semiconductor die, the second semiconductor die, and the second conductive terminal. In some embodiments, the structure further includes an underfiller disposed between the first semiconductor die and the intermediate substrate, wherein the insulating encapsulator and the first conductive terminal are spaced apart through the underfiller. In some embodiments, the insulating encapsulator is in contact with the second conductive terminal and the underfiller. In some embodiments, the first conductive terminals are laterally spaced apart from each other through the underfiller, and the second conductive terminals are laterally spaced apart from each other through the underfiller. In some embodiments, the intermediate substrate includes a semiconductor substrate, a redistributed circuit structure, and conductive terminals. The redistributed circuit structure is electrically connected to the semiconductor substrate, and the conductive terminals are electrically connected to the redistributed circuit structure. In some embodiments, the conductive terminals and the semiconductor substrate are disposed on opposite sides of the redistributed circuit structure.

[0040] According to some other embodiments of this disclosure, a method for manufacturing a semiconductor package is provided. The manufacturing method includes the following steps: providing an interposer substrate having a first region and a second region; bonding a first semiconductor die to the first region of the interposer substrate; forming an underfill between the first region of the interposer substrate and the first semiconductor die; depositing an insulating encapsulant over the interposer substrate; performing a removal process to remove a portion of the insulating encapsulant to form a remaining portion of the insulating encapsulant, wherein the remaining portion of the insulating encapsulant covers the second region of the interposer substrate; performing a patterning process on the remaining portion of the insulating encapsulant to expose the top surface of a first conductive pillar of the interposer substrate; and bonding a second semiconductor die to the first conductive pillar of the second region of the interposer substrate. In some embodiments, the removal process includes a trimming process, and the patterning process includes a laser drilling process. In some embodiments, the insulating encapsulant is formed by a molding process. In some embodiments, the insulating encapsulant is formed by a molding process followed by a patterning process.

[0041] The foregoing summary of the features of several embodiments enables those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for achieving the same purposes and / or obtaining the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package, characterized by, include: Intermediate substrate; A first semiconductor die is disposed on the intermediate substrate; A second semiconductor die is disposed on the intermediate substrate; A bottom filler is disposed between the first semiconductor die and the intermediate substrate; as well as An insulating encapsulation is disposed on the intermediate substrate, wherein the insulating encapsulation includes a first portion and a second portion, the first portion covering the second portion, the first portion laterally encapsulating the first semiconductor die and the second semiconductor die, and the second portion being disposed between the second semiconductor die and the intermediate substrate.

2. The semiconductor package of claim 1, wherein, The first semiconductor die is electrically connected to the intermediate substrate through a plurality of first conductive terminals located between the top surface of the intermediate substrate and the bottom surface of the first semiconductor die.

3. The semiconductor package of claim 1, wherein, The second semiconductor die is electrically connected to the intermediate substrate through a plurality of second conductive terminals located between the top surface of the intermediate substrate and the bottom surface of the second semiconductor die.

4. The semiconductor package of claim 2, wherein, The plurality of first conductive terminals include a first conductive bump that contacts the top surface of the intermediate substrate, a second conductive bump that contacts the bottom surface of the first semiconductor die, and a plurality of solder areas located between the first conductive bump and the second conductive bump.

5. The semiconductor package of claim 1, wherein, The top surface of the first portion is substantially flush with the top surface of the first semiconductor die.

6. A semiconductor package, characterized by, include: Intermediate substrate; A first semiconductor die is disposed on the intermediate substrate, and the first semiconductor die includes a plurality of first conductive terminals; A second semiconductor die is disposed on the intermediate substrate, and the second semiconductor die includes a plurality of second conductive terminals; as well as An insulating encapsulation is disposed on the intermediate substrate, wherein the insulating encapsulation laterally encapsulates the first semiconductor die, the second semiconductor die, and the plurality of second conductive terminals.

7. The semiconductor package of claim 6, wherein, It further includes an underfiller disposed between the first semiconductor die and the intermediate substrate, wherein the insulating encapsulator is spaced apart from the plurality of first conductive terminals through the underfiller.

8. The semiconductor package of claim 7, wherein, The insulating encapsulation is in contact with the plurality of second conductive terminals and the underfill.

9. The semiconductor package of claim 7, wherein, The plurality of first conductive terminals are laterally spaced apart from each other through the underfill, and the plurality of second conductive terminals are laterally spaced apart from each other through the underfill.

10. The semiconductor package of claim 6, wherein, The intermediate substrate includes a semiconductor substrate, a redistributed circuit structure, and a plurality of conductive terminals. The redistributed circuit structure is electrically connected to the semiconductor substrate, and the plurality of conductive terminals are electrically connected to the redistributed circuit structure. The plurality of conductive terminals and the semiconductor substrate are disposed on opposite sides of the redistributed circuit structure.

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