Wafer fixing device and wafer etching device

Abstract

The embodiment of the utility model provides a wafer fixing device and a wafer etching device, and relates to the technical field of semiconductors. The wafer fixing device comprises a bearing disc and an edge ring. The bearing disc is used for placing wafers. The edge ring is arranged around the edge of the bearing disc and comprises a first surface and a second surface which are oppositely arranged, the first surface and the wafer are located on the same side of the bearing disc, and the first surface gradually gets close to the second surface in the direction away from the bearing disc. By performing simple structural deformation on the edge ring, the problem that polymer and reflected plasma are transmitted to the edge of the wafer to cause interference on etching of the edge of the wafer is avoided, and the overall etching uniformity of the wafer is further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a wafer fixing device and a wafer etching device. Background Technology

[0002] In the fabrication process of silicon carbide power chips, the silicon oxide film etching stage utilizes capacitively coupled plasma dry etching equipment. In this equipment, the protection of the outer ring of the electrostatic chuck relies on an edge ring. The edge ring serves two main functions: firstly, to prevent direct plasma bombardment of the edge area of ​​the electrostatic chuck; and secondly, to act as an electric field shield.

[0003] During the etching process, plasma bombardment of the edge ring generates polymers, which diffuse outwards. Simultaneously, some plasma is reflected back to the wafer edge by the edge ring. However, the central region of the wafer experiences less interference from these plasmas and polymers. This results in significant etching inhomogeneity between the wafer edge and the central region. Summary of the Invention

[0004] This application proposes a wafer fixing device and a wafer etching device, which aims to improve the overall etching uniformity of the wafer by making simple structural deformation of the edge ring to avoid the problem of polymer and reflected plasma being transmitted to the wafer edge and causing interference to the etching of the wafer edge.

[0005] On one hand, this application provides a wafer fixing device, including a carrier disk and an edge ring.

[0006] The carrier disk is used to place the wafer.

[0007] An edge ring is disposed around the edge of the carrier disk. The edge ring includes a first surface and a second surface disposed opposite to each other. The first surface is located on the same side of the carrier disk as the wafer. Along the direction away from the carrier disk, the first surface gradually approaches the second surface.

[0008] This application achieves this by creating an edge ring with a certain slope. When plasma bombards the first surface, the sloped structure of the edge ring alters the plasma's propagation direction, causing the plasma to be reflected away from the wafer and guiding the generated polymer to propagate away from the wafer. This significantly reduces the amount of plasma that would otherwise be directly reflected to the wafer edge and the amount of polymer that diffuses to the wafer edge. Specifically, after the plasma impacts the first surface, it is reflected, and the polymer's trajectory is guided further away from the wafer's location as it passes over the first surface, thus reducing the probability of plasma and polymer reaching the wafer edge.

[0009] By changing the reflection path and quantity of plasma, the additional etching effect on the wafer edge due to plasma reflection is effectively reduced, making the etching environment of the wafer edge and the central region more similar, improving the uniformity of the overall wafer etching, and thus improving the quality of the etching process.

[0010] This application reduces the amount of polymer diffused to the wafer edge during plasma etching by forming an edge ring with a certain slope, thus avoiding the problem of polymer accumulation at the wafer edge during dry etching. This avoids the situation where, during etching, the slower etching rate in the first direction (e.g., horizontal) leads to continuous polymer accumulation, while the faster etching rate in the second direction (e.g., vertical) prevents polymer accumulation. However, after a certain period, when the polymer accumulation in the first direction reaches a certain amount, the etched shape becomes an inverted trapezoid. The embodiments of this application reduce the amount of polymer transported to the wafer edge, making the etching conditions at the wafer edge and center regions more similar, reducing the etching difference between the wafer edge and center, and effectively improving the etching uniformity of the entire wafer.

[0011] In some embodiments, the first surface is a planar shape inclined toward the carrier disk.

[0012] In some embodiments, the second surface is parallel to the surface of the carrier disk on which the wafer is placed, and the angle between the plane containing the first surface and the plane containing the second surface is an acute angle with the opening facing the carrier disk.

[0013] In some embodiments, the first surface is curved and recessed toward the carrier disk.

[0014] In some embodiments, the maximum thickness of the portion of the edge ring extending beyond the carrier disk along the direction from the second surface to the first surface is greater than or equal to a preset thickness, where the preset thickness is the thickness of the wafer to be placed.

[0015] In some embodiments, the side of the edge ring near the carrier disk is perpendicular to the surface of the carrier disk used to place the wafer.

[0016] In some embodiments, the wafer fixing device further includes a receiving structure having a receiving groove, the receiving structure being located on the side of the edge ring away from the carrier disk, and closer to the second surface than the receiving groove on the first surface.

[0017] In some embodiments, the edge ring is made of alumina ceramic material.

[0018] In some embodiments, the carrier tray includes an electrostatic adsorption chuck, which is used to fix the wafer by electrostatic adsorption.

[0019] On the other hand, this application also provides a wafer etching apparatus, including the wafer fixing device and cavity structure described in any of the above embodiments, wherein the cavity structure has an etching cavity and the wafer fixing device is disposed in the etching cavity.

[0020] The wafer etching apparatus of this application includes a wafer fixing device as described in any of the above embodiments.

[0021] The technical effects of the wafer etching apparatus can be found in the aforementioned technical effects of the wafer fixing apparatus, and will not be repeated here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0023] Figure 1 This is a schematic diagram of a wafer fixing device provided in an embodiment of this application;

[0024] Figure 2 This is a schematic diagram of an etched shape provided in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of another wafer fixing device provided in an embodiment of this application;

[0026] Figure 4 This is a schematic diagram of another wafer fixing device provided in an embodiment of this application;

[0027] Figure 5 This is a schematic diagram of another wafer fixing device provided in an embodiment of this application;

[0028] Figure 6 This is a schematic diagram of a wafer etching apparatus provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0030] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0031] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0032] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0033] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0034] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0035] Firstly, such as Figure 1 As shown, this application provides a wafer fixing device 10, including a carrier disk 101 and an edge ring 102.

[0036] The carrier disk 101 is used to place the wafer 103.

[0037] The carrier tray 101 plays a fundamental and crucial role in the entire wafer holder 10, its primary function being to hold the wafer 103. The design of the carrier tray 101 must fully consider the size and shape of the wafer 103, as well as its compatibility with the wafer 103, to ensure that the wafer 103 can be placed stably and accurately on its surface, providing reliable support for subsequent process operations. When placing the wafer 103, the carrier tray 101 typically possesses a precise positioning structure to ensure the positional accuracy of the wafer 103, avoiding issues such as wafer 103 misalignment during the process, which could affect the quality and effectiveness of processes such as etching.

[0038] An edge ring 102 is arranged around the edge of the carrier disk 101. The edge ring 102 can prevent plasma from directly bombarding the edge area of ​​the electrostatic adsorption chuck and can also serve as an electric field shield.

[0039] The edge ring 102 includes a first surface P1 and a second surface P2 disposed opposite to each other. The first surface P1 is located on the same side of the carrier disk 101 as the wafer 103.

[0040] For example, with Figure 1 Taking the orientation as an example, the upper surface of the carrier disk 101 is used to carry the wafer 103, then the upper surface of the edge ring 102 is the first surface P1, and the lower surface is the second surface.

[0041] Along the direction away from the carrier disk 101, the first surface P1 gradually approaches the second surface P2, causing the edge ring 102 to form a structure with a certain slope, and along the direction away from the wafer 103, this slope gradually decreases (to... Figure 1 Taking the orientation as an example, "above" is defined as high, and "below" is defined as low.

[0042] This application creates an edge ring 102 with a certain slope. When plasma bombards the first surface P1, the sloped structure of the edge ring 102 alters the plasma's propagation direction, causing the plasma to be reflected away from the wafer 103 and guiding the generated polymer to propagate away from the wafer 103. This significantly reduces the amount of plasma that would otherwise be directly reflected to the edge of the wafer 103 and the amount of polymer that diffuses to the edge of the wafer 103. Specifically, after the plasma impacts the first surface P1, it is reflected, and when the polymer passes through the first surface P1, its trajectory is guided further away from the direction of the wafer 103, thereby reducing the probability of plasma and polymer reaching the edge of the wafer 103.

[0043] By changing the reflection path and quantity of plasma, the additional etching effect on the edge of wafer 103 due to plasma reflection is effectively reduced, making the etching environment of the edge and center regions of wafer 103 more similar, improving the overall etching uniformity of wafer 103, and thus improving the quality of the etching process.

[0044] This application reduces the amount of polymer diffused to the edge of the wafer 103 by forming an edge ring 102 with a certain slope, thus avoiding the problem of polymer accumulation at the edge of the wafer 103 during dry etching. This avoids the situation where, during etching, the slower etching rate in the first direction X leads to continuous polymer accumulation, while the faster etching rate in the second direction Y prevents polymer accumulation. However, this also prevents the situation where, after a certain period, the polymer accumulation in the first direction X reaches a certain amount, causing the etched shape to become an inverted trapezoid. By reducing the amount of polymer transported to the edge of the wafer 103, the etching conditions of the edge and center regions of the wafer 103 become more similar, reducing the etching difference between the edge and center of the wafer 103 and effectively improving the etching uniformity of the entire wafer 103.

[0045] In some embodiments, the first surface P1 is a planar shape inclined toward the carrier disk 101.

[0046] The first surface P1 of the edge ring 102 is a plane that is inclined toward the support plate 101. Specifically, from the cross-section of the edge ring 102, the first surface P1 is a straight line that forms a certain angle with the plane on which the support plate 101 is located, and the straight line is inclined toward the support plate 101.

[0047] When plasma bombards the tilted first surface P1, some of the plasma is reflected, while polymers are generated and diffuse outwards. Due to the tilt angle of the surface, the direction of plasma movement during reflection and polymer diffusion is guided and altered. The amount of plasma that would otherwise be directly reflected onto wafer 103 and the amount of polymer that would diffuse onto wafer 103 are significantly reduced. Specifically, the tilted surface causes the direction of plasma and polymer movement to deviate more from the direction of wafer 103, thus reducing the probability of plasma and polymer reaching the edge of wafer 103. Furthermore, the tilted surface may also prevent some plasma from colliding with or exchanging energy with other particles during reflection, reducing polymer generation and further weakening its impact on the edge of wafer 103.

[0048] This tilted first surface P1 design effectively reduces the impact of plasma reflection and polymer diffusion on the edge of wafer 103 by changing the movement path of plasma and polymer, making the etching environment of the edge and center regions of wafer 103 more similar, thereby improving the overall etching uniformity of wafer 103.

[0049] In some embodiments, the second surface P2 is parallel to the surface of the carrier disk 101 on which the wafer 103 is placed, and the angle between the plane where the first surface P1 is located and the plane where the second surface P2 is located is an acute angle with the opening facing the carrier disk 101.

[0050] The second surface P2 is parallel to the surface on which the wafer 103 is placed on the carrier disk 101. This design ensures the stability of the relative position of the edge ring 102 with the carrier disk 101 and the wafer 103 in the first direction X. The plane containing the first surface P1 and the plane containing the second surface P2 form an acute angle with an opening facing the carrier disk 101. This structural design not only changes the contour shape of the edge ring 102 but also affects the reflection path of plasma on the surface of the edge ring 102.

[0051] The angle between the plane containing the first surface P1 and the plane containing the second surface P2 is an acute angle with the opening facing the carrier disk 101, causing the first surface P1 to tilt. This changes the reflection path when the plasma bombards the edge ring 102, reducing the amount of plasma reflected onto the wafer 103. At the same time, it guides the diffusion direction of the polymer generated by the plasma bombardment of the edge ring 102, causing it to diffuse away from the wafer 103. This reduces the impact of plasma reflection and polymer diffusion on the edge of the wafer 103, improves the etching uniformity of the edge and center of the wafer 103, and reduces the problems of wafer 103 defects and yield reduction caused by uneven etching.

[0052] In some embodiments, such as Figure 3 As shown, the first surface P1 is curved and recessed toward the bearing disk 101.

[0053] For example, the first surface P1 of the edge ring 102 is designed to be curved and recessed towards the support disk 101. From a three-dimensional spatial perspective, this curved surface is not a simple planar bend, but has a specific radius of curvature and shape, with the entire recessed area transitioning smoothly without obvious edges or abrupt changes.

[0054] Viewed in cross-section from the edge ring 102, the first surface P1 appears as a curve curving towards the support disk 101. During etching, when plasma bombards the recessed curved first surface P1, the plasma's trajectory changes significantly. Due to the guiding effect of the curved surface, the plasma moves along a specific path away from the wafer 103 during reflection, rather than scattering randomly as on a planar surface. This reduces the problem of uneven etching of the entire wafer 103 caused by the difference in etching conditions between the edge and center of wafer 103 due to plasma reflection to the edge of wafer 103.

[0055] The concave first surface P1 can alter the diffusion direction of the polymer generated after plasma bombardment. Compared to a planar surface, the curved surface allows the polymer to move away from the wafer 103 during diffusion, reducing the amount of polymer diffusing onto the wafer 103 and mitigating the problem of uneven overall etching of the wafer 103 caused by different etching conditions between the wafer 103 edge and the wafer 103 center due to polymer diffusion to the wafer 103 edge.

[0056] In some embodiments, such as Figure 4 As shown, the maximum thickness D1 of the portion of the edge ring 102 extending beyond the carrier disk 101 along the direction from the second surface P2 to the first surface P1 is greater than or equal to the preset thickness D2, where the preset thickness D2 is the thickness of the wafer 103 to be placed.

[0057] For example, the second surface P2 is parallel to the surface on which the wafer 103 is placed on the carrier disk 101, providing a reference plane for the relative position of the edge ring 102 with respect to the carrier disk 101 and the wafer 103. The plane containing the first surface P1 forms a specific angular relationship with the plane containing the second surface P2, and the first surface P1 has a specific shape, such as a tilted plane or a concave curved surface as described in the above embodiments. Along the direction from the second surface P2 to the first surface P1, the portion of the edge ring 102 extending beyond the carrier disk 101 has a maximum thickness D1. During the etching process, when the plasma bombards the carrier disk 101 and the edge ring 102, on the one hand, the plasma itself carries high energy and bombards and etches the edge of the wafer 103; on the other hand, the plasma interacts with the material of the edge ring 102, generating byproducts such as polymers. When the plasma bombards the first surface P1 of the edge ring 102, some of the plasma is reflected, and the polymer generated from etching the edge ring 102 is also sputtered along with the movement of the plasma. The maximum thickness D1 of the edge ring 102 extending beyond the carrier disk 101 is greater than or equal to the thickness D2 of the wafer 103, which can further block the plasma reflected by the first surface P1 and the generated polymer from sputtering onto the surface of the wafer 103.

[0058] If these plasmas and polymers are directly sputtered onto the surface of wafer 103, it will cause a difference in the etching environment between the edge region and the center region of wafer 103. For example, after the polymer is sputtered onto the edge of wafer 103, it may adhere to the surface of wafer 103, hindering the etching reaction and resulting in insufficient etching at the edge of wafer 103.

[0059] However, the reasonable thickness design of the edge ring 102 extending beyond the carrier disk 101 effectively reduces the impact of these adverse factors. It prevents and disperses plasma and polymers before they reach the surface of wafer 103, ensuring a relatively uniform etching environment for the edges and center of wafer 103 during etching. This results in more uniform etching at the edges and center of wafer 103, improving the overall etching quality and consequently enhancing the performance and yield of semiconductor devices.

[0060] Meanwhile, in semiconductor manufacturing, wafers 103 of varying thicknesses may be used. The maximum thickness D1 of the portion of the edge ring 102 extending beyond the carrier pad 101 is greater than or equal to the common wafer 103 thickness D2, allowing this edge ring 102 design to accommodate wafers 103 of various thicknesses. When changing the wafer 103 thickness D2, there is no need for large-scale adjustments or replacements to the edge ring 102, improving the compatibility and flexibility of the etching equipment and reducing equipment operating costs and maintenance complexity.

[0061] In some embodiments, the side of the edge ring 102 near the carrier disk 101 is perpendicular to the surface of the carrier disk 101 used to place the wafer 103.

[0062] For example, a vertical side design can make the plasma more evenly distributed in the edge region of wafer 103. For instance, if the side of edge ring 102 facing the carrier disk 101 is tilted towards the carrier disk 101, it will cause some obstruction to the edge of wafer 103, preventing the plasma from etching the edge of wafer 103 and resulting in uneven etching of wafer 103 as a whole.

[0063] In another scenario, when the side of the edge ring 102 closest to the carrier disk 101 is tilted towards the side furthest from the carrier disk 101, i.e., the angle between the plane containing the first surface P1 of the edge ring 102 and the plane containing the carrier disk 101 is obtuse, when plasma bombards the first surface P1 of the edge ring 102, the plasma is reflected, and the polymer generated by the plasma bombardment of the edge ring 102 is more easily transported to the edge of the wafer 103 through the guidance of the tilted first surface P1, affecting the etching of the edge of the wafer 103. Simultaneously, this creates a difference in the etching environment between the edge and center of the wafer 103, resulting in uneven etching between the edge and center of the wafer 103.

[0064] The vertical side design reduces the risk of physical collision between the edge ring 102 and the wafer 103 during the etching process. During the placement, movement, and etching of the wafer 103, if the side of the edge ring 102 has a tilted or irregular shape, it may rub or collide with the edge of the wafer 103, causing damage to the edge of the wafer 103 or wear on the edge ring 102. The vertical side design ensures a relatively stable distance between the edge ring 102 and the wafer 103, reducing this physical interference and protecting the integrity of both the wafer 103 and the edge ring 102.

[0065] The vertical side design makes it easier to position the edge ring 102 when it is installed onto the carrier plate 101. Operators can quickly and accurately install the edge ring 102 into the designated position based on the relative position of the vertical side and the carrier plate 101, improving installation efficiency and accuracy.

[0066] The vertical side design also simplifies the operation when the edge ring 102 needs maintenance or replacement. Due to the regularity of the sides, jamming or misalignment is less likely to occur during disassembly and installation, reducing maintenance time and costs.

[0067] In some embodiments, such as Figure 5 As shown, the wafer 103 fixing device also includes a receiving structure with a receiving groove 104. The receiving structure is located on the side of the edge ring 102 away from the carrier disk 101, and the receiving groove 104 is closer to the second surface than the first surface P1.

[0068] The receiving groove 104 will receive some plasma and polymer to prevent the receiving plate 101 from adsorbing plasma and polymer through electrostatic adsorption, thereby affecting the etching of the wafer 103.

[0069] During the etching process, a series of complex physical and chemical reactions occur as the plasma interacts with components such as wafer 103 and edge ring 102. On one hand, the plasma undergoes reflection and scattering during bombardment; on the other hand, the plasma reacts with the material surface to generate byproducts such as polymers. These plasmas and polymers diffuse throughout the etching chamber.

[0070] Since the receiving structure is located on the side of the edge ring 102 away from the carrier disk 101, and the receiving groove 104 is closer to the second surface P2, when plasma and polymer move in the etching chamber, they will more easily enter the receiving groove 104, and the receiving groove 104 can receive most of the plasma and polymer.

[0071] Without a support structure, these plasmas and polymers may move randomly within the etching chamber, and some may adhere to the carrier pad 101 under electrostatic adsorption. As a key component for placing the wafer 103, the surface condition of the carrier pad 101 significantly impacts the etching effect. If plasmas and polymers adsorb onto the surface of the carrier pad 101, it may alter the charge distribution on its surface, thereby affecting the carrier pad 101's electrostatic adsorption capacity for the wafer 103. This could lead to positional displacement or weak adhesion of the wafer 103 during etching, affecting the etching accuracy and stability.

[0072] Plasma and polymer adsorbed on the surface of the carrier disk 101 may be released again during subsequent etching processes, interfering with the etching environment around the wafer 103.

[0073] In some embodiments, the edge ring 102 is made of alumina ceramic material.

[0074] In the prior art, the edge ring 102 is made of silicon or quartz. During the etching process, the plasma bombards the edge ring 102. In this process, the edge ring 102 made of silicon or quartz can be etched, resulting in a relatively low plasma concentration at the edge of the wafer 103 compared to the central region.

[0075] In this embodiment, alumina ceramic material is used as the edge ring 102. Alumina ceramic material has excellent physical and chemical stability, and its wear rate is relatively uniform and slow during etching. This makes the reaction between the etching gas and the surface of the edge ring 102 more stable. When plasma bombards the alumina ceramic edge ring 102, the difference in plasma concentration between the edge and center regions of the wafer 103 is reduced, making the etching conditions between the edge and center regions of the wafer 103 more similar. This reduces the etching difference between the edge and center of the wafer 103 and improves the etching uniformity of the entire wafer 103.

[0076] When plasma bombards the edge ring 102, it generates polymers that diffuse outwards. Some of these polymers diffuse to the edge of the wafer 103, which interferes with the etching environment at the edge of the wafer 103. This results in differences in etching conditions between the edge and center of the wafer 103, thus affecting the overall etching uniformity of the wafer 103.

[0077] During plasma bombardment of the alumina ceramic edge ring 102, the amount of polymer generated is relatively small, and the amount of polymer diffusing to the edge of wafer 103 is also reduced, greatly minimizing polymer interference with the edge of wafer 103. This makes the etching conditions at the edge and center of wafer 103 more similar, thereby effectively improving the etching uniformity of wafer 103.

[0078] In dry etching processes, such as Figure 2 As shown, etching primarily proceeds in the second direction Y, forming a vertical sidewall structure. Specifically, the etching rate is relatively slow in the first direction X, while it is faster in the second direction Y. As the etching process continues, plasma bombardment of the edge ring 102 generates polymers, which gradually accumulate at the edge of wafer 103. Especially in the first direction X, due to the slower etching rate, polymers continuously accumulate. The faster etching rate in the second direction Y prevents polymer accumulation. After a certain period, when the polymer accumulation in the first direction X reaches a certain amount, the etched shape becomes an inverted trapezoid. In contrast, the polymer distribution in the central region of wafer 103 is relatively uniform, and the etched shape is more normal. This difference in etched shape between the edge and center of wafer 103 is one of the key factors leading to uneven etching across the entire wafer 103.

[0079] In summary, alumina ceramic materials possess excellent physical and chemical stability. During etching, its wear rate is relatively uniform and slow. This makes the reaction between the etching gas and the surface of the edge ring 102 more stable and controllable. The interference generated by plasma bombardment of the edge ring 102 of the alumina ceramic material is also reduced. Ultimately, the etching conditions of the edge and center regions of wafer 103 are more similar, the etching difference between the edge and center of wafer 103 is reduced, and the etching uniformity of the entire wafer 103 is effectively improved.

[0080] In some embodiments, the carrier disk 101 includes an electrostatic adsorption chuck, which is used to fix the wafer 103 by electrostatic adsorption.

[0081] The electrostatic adsorption force of the electrostatic adsorption chuck is evenly distributed on the surface of wafer 103, which can accurately fix wafer 103 in the predetermined position of the chuck, ensuring the positional accuracy of wafer 103 during the etching process and meeting the high-precision processing requirements of semiconductor manufacturing.

[0082] Besides the electrostatic adsorption chuck, other methods can be used to fix the wafer 103 onto the carrier disk 101. This application is not limited to electrostatic adsorption as a fixing method.

[0083] This application also provides a wafer etching apparatus 11, such as Figure 6 As shown, the device includes a wafer holder 10 and a cavity structure as described in any of the above embodiments. The cavity structure has an etching cavity 105, within which the wafer holder 10 is disposed.

[0084] For example, the wafer etching apparatus 11 can be used for etching the silicon oxide film layer in the silicon carbide power chip fabrication process. The wafer etching apparatus 11 of this application includes the wafer fixing device 10 as described in any of the above embodiments. For example, by forming a slope structure for the edge ring 102 and using an edge ring 102 made of alumina material, the amount of plasma reflected to the edge of the wafer 103 and the amount of polymer generated when the plasma bombards the edge ring 102 can be reduced, making the etching conditions of the edge and center regions of the wafer 103 more similar, thereby reducing the etching difference between the edge and center of the wafer 103, effectively improving the etching uniformity of the entire wafer 103, and improving the quality and performance of the silicon carbide power chip.

[0085] The wafer etching apparatus 11 also includes other effects, which can be referred to in the description of the effects of the aforementioned wafer fixing apparatus 10, and will not be repeated here.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer fixing device, characterized in that, include: A tray for holding wafers; An edge ring is provided around the edge of the carrier disk; the edge ring includes a first surface and a second surface disposed opposite to each other, the first surface being located on the same side of the carrier disk as the wafer; the first surface gradually approaches the second surface along a direction away from the carrier disk.

2. The wafer fixing device according to claim 1, characterized in that, The first surface is a plane inclined toward the bearing plate.

3. The wafer fixing device according to claim 2, characterized in that, The second surface is parallel to the surface of the carrier disk on which the wafer is placed, and the angle between the plane containing the first surface and the plane containing the second surface is an acute angle with the opening facing the carrier disk.

4. The wafer fixing device according to claim 1, characterized in that, The first surface is curved and recessed toward the bearing plate.

5. The wafer fixing device according to claim 1, characterized in that, The maximum thickness of the portion of the edge ring extending beyond the carrier disk along the direction from the second surface to the first surface is greater than or equal to a preset thickness; the preset thickness is the thickness of the wafer to be placed.

6. The wafer fixing device according to claim 1, characterized in that, The side of the edge ring near the carrier disk is perpendicular to the surface of the carrier disk used to place the wafer.

7. The wafer fixing device according to claim 1, characterized in that, Also includes: The receiving structure has a receiving groove, and the receiving structure is located on the side of the edge ring away from the bearing plate, and the receiving groove is closer to the second surface than the first surface.

8. The wafer fixing device according to any one of claims 1 to 7, characterized in that, The edge ring is made of alumina ceramic material.

9. The wafer fixing device according to any one of claims 1 to 7, characterized in that, The carrier tray includes an electrostatic adsorption chuck, which is used to fix the wafer by electrostatic adsorption.

10. A wafer etching apparatus, characterized in that, include: The wafer fixing device as described in any one of claims 1 to 9; The cavity structure includes an etching cavity; The wafer fixing device is disposed inside the etching cavity.

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