Discrete device-based charger insertion detection circuit for BMS battery system

Abstract

The utility model discloses a discrete device-based charger insertion detection circuit for a BMS (battery management system). The discrete device-based charger insertion detection circuit comprises a diode D1, a capacitor C1, a resistor R1, an MOS (metal oxide semiconductor) tube Q1, a resistor R2, a resistor R3, a resistor R4, an MOS tube Q2, a resistor R5 and a resistor R6. According to the charger insertion detection circuit based on the discrete device for the BMS battery system, through the low-cost combination design of the discrete device (such as cascade amplification of an MOS tube Q1 / an MOS tube Q2 and an R-C dynamic threshold feedback network), on the premise that a complex chip or an isolation framework is not introduced, the reliability of the charger insertion detection circuit is improved, and the reliability of the charger insertion detection circuit is improved. The technical contradiction among high-voltage direct connection, noise resistance, low power consumption and quick response is synchronously solved, and a charger insertion detection solution with high cost performance and high reliability is provided for a multi-string battery pack BMS.

Description

Technical Field

[0001] This utility model relates to the field of battery management system (BMS) technology, and in particular to a charger insertion detection circuit for BMS battery systems with multi-cell battery packs (such as lithium-ion battery packs and lithium iron phosphate battery packs), which is used to sense the charger connection status in real time and trigger the charging management logic of the battery pack. Background Technology

[0002] Currently, existing charger insertion detection technologies in multi-cell battery pack BMS applications suffer from core problems such as poor high-voltage compatibility, weak anti-interference capability, high power consumption, and insufficient response speed. To address the specific needs of multi-cell battery pack BMS, a new charger insertion detection solution is urgently needed. Summary of the Invention

[0003] The main objective of this invention is to propose a charger insertion detection circuit based on discrete components for BMS battery systems. It aims to achieve low power consumption, high reliability, and no need for isolation devices by using a three-level architecture of signal level conversion, filtering, and logic output.

[0004] To achieve the above objectives, this utility model proposes a charger insertion detection circuit based on discrete components for a BMS battery system, comprising: diode D1, capacitor C1, resistor R1, MOSFET Q1, resistor R2, resistor R3, resistor R4, MOSFET Q2, resistor R5, and resistor R6.

[0005] The cathode of diode D1 is connected to the negative terminal of the charger. The anode of diode D1 is connected to one end of capacitor C1, one end of resistor R1, and the emitter of MOSFET Q1. The other end of capacitor C1 is connected to the other end of resistor R1, one end of resistor R2, and the base of MOSFET Q1. The collector of MOSFET Q1 is connected to one end of resistor R3. The other end of resistor R3 is connected to one end of resistor R4 and the emitter of MOSFET Q2. The other end of resistor R4 and the collector of MOSFET Q2 are connected to the VCC power supply. The base of MOSFET Q2 is connected to one end of resistor R5 and one end of resistor R6. The other end of resistor R5 is grounded, and the other end of resistor R6 is connected to CHARGER_IN.

[0006] A further technical solution of this utility model is that the negative terminal of the charger is isolated by the diode D1 to prevent reverse leakage of the battery pack.

[0007] A further technical solution of this utility model is that when the charger is plugged in and the voltage is higher than the battery pack voltage, the negative terminal potential of the charger is lower than the GND of the battery pack, forming a voltage difference. The anode voltage of the diode D1 is pulled down, triggering signal coupling.

[0008] A further technical solution of this utility model is that the capacitor C1 and the resistor R1 form an RC network, and the emitter of the MOS transistor Q1 is connected to the RC network to form a low-pass filter network.

[0009] A further technical solution of this utility model is that the resistors R1 and R2 form a voltage divider network, and the base of the MOS transistor Q1 is set with a conduction threshold through the voltage divider network. When the negative voltage of the charger is effectively pulled down, the base potential of the MOS transistor Q1 triggers the conduction condition.

[0010] A further technical solution of this utility model is that the resistance ratio of the resistor R4 and the resistor R3 forms a hysteresis window of 0.6V, which suppresses false triggering caused by voltage fluctuations.

[0011] A further technical solution of this utility model is that the resistor R6 limits the instantaneous current when the MOS transistor Q2 is turned on, and the resistor R5 provides a definite low level when the charger is not plugged in, so as to avoid the signal floating.

[0012] A further technical solution of this utility model is that the MOS transistor Q1 is an NPN type MOS transistor, and the MOS transistor Q2 is a PNP type MOS transistor.

[0013] The advantages of this utility model for a charger insertion detection circuit based on discrete components for BMS battery systems are:

[0014] I. Advantages of low cost and high integration:

[0015] 1. Discrete components replace dedicated chips: The high-voltage signal is directly converted to the logic level through the NPN-PNP transistor cascade structure (MOS transistor Q1-MOS transistor Q2). Compared with the traditional optocoupler or level conversion chip solution, the component cost is reduced by more than 90% (typical BOM cost < 0.5 RMB).

[0016] 2. Simplified circuit topology: Only 6 discrete components (2 transistors, 4 resistors, 1 capacitor, and 1 diode) are needed to complete the detection function, reducing the circuit area to 1 / 3 of the traditional solution, making it suitable for space-constrained BMS module designs.

[0017] II. Ultra-low static power consumption characteristics:

[0018] Near-zero leakage current design:

[0019] 1. In the static state, the base of MOSFET Q1 is pulled down to GND through resistor R2 (200kΩ), and the base of MOSFET Q2 is pulled up to 3.3V through resistor R4 (100kΩ). Both transistors are in the off state, and the total static current is 0.011uA.

[0020] 2. Actual total static power consumption: <1μA (including PCB leakage current), meeting the low power consumption requirements of IoT devices and energy storage systems.

[0021] III. Strong anti-interference capability:

[0022] Hardware-level noise suppression:

[0023] 1. RC low-pass filter design: High-frequency noise >0.31Hz (such as charger plugging and unplugging jitter, switching power supply ripple) is filtered out through the resistor R1 (510kΩ)-C1 (100nF) network to avoid false triggering.

[0024] 2. Enhanced hysteresis effect: The base pull-up resistor R4 (100kΩ) of MOSFET Q2 and the drive resistor R3 (510kΩ) form a 1:5 resistance ratio, generating a hysteresis window of about 0.5V, which can suppress voltage fluctuation interference within ±0.5V.

[0025] IV. Wide voltage compatibility:

[0026] Dynamic threshold adaptation: By using the dynamic voltage divider between the emitter and base of MOSFET Q1 (R1-R2 network), the threshold is detected and automatically matched to changes in battery pack voltage (such as 12-60V battery pack system), meeting the voltage boost requirements of various charging protocols, and has better compatibility than fixed threshold solutions.

[0027] V. Rapid Response and Reliability:

[0028] 1. Hardware-accelerated response:

[0029] (1) Charger insertion: After MOSFET Q1 is turned on, the base potential of MOSFET Q2 is quickly pulled down through R3 (510kΩ). The response time is 5ms to ensure that the BMS captures the charging event within 10ms.

[0030] (2) Charger removal: MOSFET Q2 is quickly pulled up and reset via R4 (100kΩ) to avoid misjudgment caused by delay.

[0031] 2. Reverse current blocking: The cathode of diode D1 is connected to C-, which completely blocks the reverse discharge path of the battery pack to the charging interface (leakage current <1nA), avoiding accidental battery damage.

[0032] VI. Environmental adaptability:

[0033] Wide temperature range stability: Through the negative temperature coefficient of the transistor base-emitter voltage (Vbe) and the temperature compensation design of the resistor network, the detection threshold drift is <±3% in the range of -40°C to 85°C, which meets the requirements of automotive-grade applications. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the circuit structure of a preferred embodiment of the charger insertion detection circuit based on discrete components for a BMS battery system according to this utility model.

[0036] Figure 2 This is a schematic diagram of the charging MOSFET circuit;

[0037] Figure 3 This is a diagram showing the charger connection;

[0038] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0039] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0040] This utility model proposes a charger insertion detection circuit based on discrete components for BMS battery systems. Please refer to [reference needed]. Figures 1 to 3 The preferred embodiment of the charger insertion detection circuit based on discrete components for BMS battery system of this utility model includes: diode D1, capacitor C1, resistor R1, MOSFET Q1, resistor R2, resistor R3, resistor R4, MOSFET Q2, resistor R5 and resistor R6.

[0041] The cathode of diode D1 is connected to the negative terminal of the charger. The anode of diode D1 is connected to one end of capacitor C1, one end of resistor R1, and the emitter of MOSFET Q1. The other end of capacitor C1 is connected to the other end of resistor R1, one end of resistor R2, and the base of MOSFET Q1. The collector of MOSFET Q1 is connected to one end of resistor R3. The other end of resistor R3 is connected to one end of resistor R4 and the emitter of MOSFET Q2. The other end of resistor R4 and the collector of MOSFET Q2 are connected to the VCC power supply. The base of MOSFET Q2 is connected to one end of resistor R5 and one end of resistor R6. The other end of resistor R5 is grounded, and the other end of resistor R6 is connected to CHARGER_IN. MOSFET Q1 is an NPN type MOSFET, and MOSFET Q2 is a PNP type MOSFET.

[0042] In this embodiment, the negative terminal of the charger is isolated by diode D1 to prevent reverse leakage of the battery pack.

[0043] In this embodiment, when the charger is plugged in and its voltage is higher than that of the battery pack, the negative terminal potential of the charger is lower than that of the battery pack GND, forming a voltage difference. The anode voltage of diode D1 is pulled down, triggering signal coupling.

[0044] In this embodiment, capacitor C1 and resistor R1 form an RC network, and the emitter of MOSFET Q1 is connected to the RC network to form a low-pass filter network.

[0045] In this embodiment, resistors R1 and R2 form a voltage divider network. The base of MOSFET Q1 is set with a conduction threshold through the voltage divider network. When the negative voltage of the charger is effectively pulled down, the base potential of MOSFET Q1 triggers the conduction condition.

[0046] In this embodiment, the resistance ratio of resistor R4 to resistor R3 forms a hysteresis window of 0.6V, which suppresses false triggering caused by voltage fluctuations.

[0047] In this embodiment, resistor R6 limits the instantaneous current when MOSFET Q2 is turned on, and resistor R5 provides a definite low level when the charger is not plugged in, thus preventing the signal from floating.

[0048] This utility model addresses the component selection and connection of a charger insertion detection circuit based on discrete components for a BMS battery system, as well as the design of key parameters, as follows:

[0049] I. Component Selection and Connection:

[0050] 1. Signal isolation and coupling:

[0051] (1) The diode D1 is a Schottky diode with low voltage drop and extremely low reverse leakage current (such as BAT54S). The cathode is connected to the negative terminal (C-) of the charger, and the anode is connected to the emitter of the NPNMOS transistor Q1 (model MMBT3904).

[0052] (2) RC filter network: The emitter of MOSFET Q1 is connected in parallel with resistor R1 (510kΩ, 1% accuracy) and capacitor C1 (100nF, X7R material). The other end of resistor R1 and the other end of capacitor C1 are connected to the base of MOSFET Q1 to form a low-pass filter network.

[0053] 2. Base pull-down and drive circuit:

[0054] (1) The base of MOS transistor Q1 is connected to GND via resistor R2 (200kΩ), and the collector is connected to the base of PNPMOS transistor Q2 (model MMBT3906) via resistor R3 (510kΩ).

[0055] (2) The base of MOSFET Q2 is pulled up to the 3.3V power supply through resistor R4 (100kΩ), the emitter is directly connected to the 3.3V power supply, and the collector outputs the interrupt signal CHARGER_IN through series resistor R6 (1kΩ) and is pulled down to GND through resistor R5 (510kΩ).

[0056] II. Key Parameter Design

[0057] 1. Turn-on condition of MOSFET Q1: MOSFET Q1 turns on when the C- potential exceeds 0.8V relative to the battery GND;

[0058] 2. Hysteresis window design: The resistance ratio of resistor R4 (100kΩ) to resistor R3 (510kΩ) forms a hysteresis voltage of approximately 0.5V to prevent signal jitter.

[0059] The following provides a more detailed explanation of the structure and working principle of the charger insertion detection circuit based on discrete components for BMS battery systems.

[0060] To address the specific requirements of existing multi-cell battery pack BMS technologies, a novel charger insertion detection solution is urgently needed, which must meet the following aspects:

[0061] 1. High-voltage direct connection capability: Supports direct high-voltage terminal detection without relying on isolation devices (such as 48V systems);

[0062] 2. Strong noise resistance: Maintains detection stability under dynamic balancing of multiple battery packs and sudden load changes;

[0063] 3. Ultra-low standby power consumption: The standby current of the detection circuit is less than 5μA to avoid accelerating the self-discharge of the battery pack;

[0064] 4. Fast response: Detection latency ≤ 5ms, meeting the fast switching requirements of fast charging protocols (such as CC-CV stage).

[0065] To address the core problems of existing charger insertion detection technologies in multi-cell battery management system (BMS) applications, such as poor high-voltage compatibility, weak anti-interference capability, high power consumption, and insufficient response speed, this invention proposes a charger insertion detection circuit based on discrete components for BMS battery systems, aiming to achieve the following technical objectives:

[0066] 1. Eliminate dependence on high-pressure isolation

[0067] By designing a discrete component cascade topology, it is directly compatible with the voltage input of the high-voltage side of multiple battery packs (such as a 48V system), avoiding the use of redundant modules such as optocouplers and isolated power supplies, thus reducing circuit complexity and cost (cost reduction of more than 80% compared to existing solutions).

[0068] 2. Improve dynamic noise immunity

[0069] By combining hardware RC filtering with logic level hysteresis comparison technology, transient interference inside the battery pack (such as active equalization PWM noise and load sudden changes) is effectively suppressed, ensuring that the charger insertion status can still be stably determined under ±5V common mode noise.

[0070] 3. Achieve ultra-low standby power consumption

[0071] By adopting a dynamic bias control strategy, the detection circuit is activated only when there is a voltage change at the charging interface, reducing the static current to below 3μA, which significantly extends the storage life and range of multi-cell battery packs.

[0072] 4. Optimize fast response performance

[0073] By simplifying the signal path and introducing a dynamic threshold adjustment mechanism, the detection delay is compressed to less than 5ms, meeting the real-time requirements of fast charging protocols (such as PD3.0) for charging handshake timing.

[0074] 5. Enhanced compatibility and reliability

[0075] It is compatible with a wide input voltage range (5-60V) and has no mechanical contacts, avoiding the risk of failure due to oxidation or arcing and improving the long-term stability of the system.

[0076] The technical solution adopted by this utility model for a charger insertion detection circuit based on discrete components for BMS battery systems mainly involves the low-cost combination design of discrete components (such as cascaded amplification of MOSFET Q1 / Q2 and RC dynamic threshold feedback network). Without introducing complex chips or isolation architecture, it simultaneously solves the technical contradictions between high voltage direct connection, noise immunity, low power consumption and fast response, providing a cost-effective and reliable charger insertion detection solution for multi-string battery pack BMS.

[0077] This invention relates to a charger insertion detection circuit for BMS battery systems based on discrete components. Through a three-stage architecture of signal level conversion, filtering, and logic output, it achieves low-power, high-reliability charger insertion status determination without the need for isolation devices. Its core modules are as follows:

[0078] I. Signal Coupling and Threshold Triggering Module:

[0079] 1. Diode isolation and level coupling:

[0080] (1) The negative terminal (C-) of the charger is isolated by diode D1 (cathode connected to C-) to prevent reverse leakage of the battery pack.

[0081] (2) When the charger is plugged in and its voltage is 1V higher than the battery pack voltage, the C- potential is lower than the battery pack GND (forming a 1V voltage difference), the voltage of the anode of diode D1 (emitter of MOS transistor Q1) is pulled down, triggering signal coupling.

[0082] 2. Dynamic bias and RC filter network:

[0083] (1) Emitter RC delay: The emitter of MOSFET Q1 is connected to an RC network (R1=510kΩ, C1=100nF) to form a low-pass filter with a cutoff frequency of fc=1 / 2piRC, which effectively filters out high-frequency noise (such as contact jitter) at the moment of plugging in the charger.

[0084] (2) Base voltage divider control: The base of MOSFET Q1 is set with a conduction threshold through the R1-R2 voltage divider network (R2=200kΩ grounded). When the C- voltage is effectively pulled down, the base potential of MOSFET Q1 triggers the conduction condition.

[0085] II. Amplification and Logic Conversion Module

[0086] 1. NPN-PNP cascaded drive:

[0087] (1) MOSFET Q1 turn-on control: When the charger is plugged in, the emitter voltage of MOSFET Q1 is pulled down, and its base-emitter voltage difference (Vbe) exceeds 0.6V → MOSFET Q1 turns on → the collector current pulls down the base potential of MOSFET Q2 through resistor R3 (510kΩ).

[0088] (2) Logic inversion of MOSFET Q2:

[0089] Charger not plugged in: MOSFET Q1 is off → MOSFET Q2 (PNP type) base is pulled up to 3.3V through resistor R4 (100kΩ) → MOSFET Q2 is off → CHARGER_IN signal is pulled down to low level by MOSFET R5 (510kΩ) (logic invalid).

[0090] Charger plugged in: MOSFET Q1 turns on → MOSFET Q2 base is pulled low to near GND → MOSFET Q2 turns on → CHARGER_IN signal is pulled up to 3.3V (logic valid) through MOSFET Q2 collector, triggering MCU interrupt.

[0091] 2. Anti-interference enhancement design

[0092] (1) Hysteresis effect: The resistance ratio of resistor R4 (100kΩ) to resistor R3 (510kΩ) (approximately 1:5) forms a hysteresis window of approximately 0.6V, which suppresses false triggering caused by voltage fluctuations.

[0093] (2) Output stability: Resistor R6 (1kΩ) limits the instantaneous current when MOSFET Q2 is turned on, and resistor R5 (510kΩ) provides a definite low level when not inserted to avoid signal floating.

[0094] III. Low Power Consumption and Reliability Design

[0095] 1. Near-zero quiescent current

[0096] In the static state, MOSFET Q1 is cut off, and the base of MOSFET Q2 is pulled up to 3.3V through R4 (100kΩ) → MOSFET Q2 is cut off, and only resistor R2 (200kΩ) generates a small leakage current. The total static power consumption is less than 1μA.

[0097] 2. Hardware anti-false triggering mechanism

[0098] (1) Delay filtering of capacitor C1: The 0.31Hz filtering bandwidth ensures that only valid charging signals lasting more than 1 second can trigger the response, avoiding short-term interference.

[0099] (2) Diode D1 reverse cutoff: completely blocks the reverse discharge path of the battery pack to the charging interface, avoiding unexpected power consumption.

[0100] The key workflow of the discrete component-based charger insertion detection circuit for BMS battery systems is as follows:

[0101] 1. Plug in the charger:

[0102] When the collector voltage (C-) is 1V lower than the battery GND, diode D1 turns on, the emitter voltage of MOSFET Q1 drops, MOSFET Q1 turns on after RC delay, the base of MOSFET Q2 is pulled down, MOSFET Q2 turns on, and CHARGER_IN outputs a high level of 3.3V.

[0103] 2. Charger removal:

[0104] C-voltage recovery → MOSFET Q1 is turned off → MOSFET Q2 base is pulled up to 3.3V → MOSFET Q2 is turned off → CHARGER_IN is pulled low to 0V by R5.

[0105] Specifically, the charger insertion triggering process is as follows:

[0106] 1. Step 1: After the charger is plugged in, the C- potential is raised by the external charger to about 1V higher than the battery GND → diode D1 is forward-biased;

[0107] 2. Step 2: The emitter voltage of MOSFET Q1 rises with C- → After a delay of about 3 seconds in the RC network (R1-C1), the base voltage of MOSFET Q1 exceeds the conduction threshold.

[0108] 3. Step 3: MOSFET Q1 turns on → The collector current pulls the base of MOSFET Q2 down to near GND through R3 (510kΩ) → MOSFET Q2 turns on;

[0109] 4. Step 4: The collector of MOSFET Q2 outputs a low-level signal (CHARGER_IN=0V) through resistor R6 (1kΩ) → The MCU detects the falling edge interrupt and determines that the charger has been inserted.

[0110] The charger removal and reset procedure is as follows:

[0111] 1. When the C- potential returns to the battery GND, diode D1 is cut off, the emitter voltage of MOSFET Q1 drops, the base of MOSFET Q1 is pulled down to GND by R2, and MOSFET Q1 is cut off.

[0112] 2. When the base of MOSFET Q2 rises back to 3.3V, MOSFET Q2 turns off, and CHARGER_IN returns to a high level (3.3V) through R5.

[0113] The following describes the experimental verification and test data of the charger insertion detection circuit based on discrete components for BMS battery systems according to this invention:

[0114] 1. Static power consumption test:

[0115] The total quiescent current measured using a high-precision multimeter without a charger inserted was actually less than 0.1 μA.

[0116] 2. Anti-interference test:

[0117] Injecting ±1V / 10kHz noise into the C- interface, CHARGER_IN shows no abnormal transition (RC filtering + hysteresis window dual suppression).

[0118] 3. Temperature adaptability:

[0119] High and low temperature cycling tests (-40°C~85°C) showed a detection threshold drift of <±2%, meeting reliability requirements.

[0120] The main innovations of this utility model regarding the charger insertion detection circuit based on discrete components for BMS battery systems are as follows:

[0121] 1. Discrete component logic direct drive architecture:

[0122] By utilizing the cascaded characteristics of MOSFET Q1 (NPN) and MOSFET Q2 (PNP), the conversion from high voltage signal (C-) to low voltage logic (3.3V) can be directly completed without the need for optocouplers or level conversion chips.

[0123] 2. Dynamic RC filtering and bias fusion:

[0124] The resistor R1-capacitor C1 network simultaneously achieves signal filtering and dynamic biasing of the base of MOSFET Q1, simplifying the independent filter and bias circuits in traditional solutions.

[0125] 3. Hardware hysteresis and latency coordination:

[0126] By employing a dual mechanism of proportional hysteresis between resistors R3 and R4 and delay filtering with capacitor C1, high anti-interference capability (compatible with ±1V noise) is achieved under the premise of low power consumption.

[0127] The advantages of this utility model for a charger insertion detection circuit based on discrete components for BMS battery systems are:

[0128] I. Advantages of low cost and high integration:

[0129] 1. Discrete components replace dedicated chips: The high-voltage signal is directly converted to the logic level through the NPN-PNP transistor cascade structure (MOS transistor Q1-MOS transistor Q2). Compared with the traditional optocoupler or level conversion chip solution, the component cost is reduced by more than 90% (typical BOM cost < 0.5 RMB).

[0130] 2. Simplified circuit topology: Only 6 discrete components (2 transistors, 4 resistors, 1 capacitor, and 1 diode) are needed to complete the detection function, reducing the circuit area to 1 / 3 of the traditional solution, making it suitable for space-constrained BMS module designs.

[0131] II. Ultra-low static power consumption characteristics:

[0132] Near-zero leakage current design:

[0133] 1. In the static state, the base of MOSFET Q1 is pulled down to GND through resistor R2 (200kΩ), and the base of MOSFET Q2 is pulled up to 3.3V through resistor R4 (100kΩ). Both transistors are in the off state, and the total static current is 0.011uA.

[0134] 2. Actual total static power consumption: <1μA (including PCB leakage current), meeting the low power consumption requirements of IoT devices and energy storage systems.

[0135] III. Strong anti-interference capability:

[0136] Hardware-level noise suppression:

[0137] 1. RC low-pass filter design: High-frequency noise >0.31Hz (such as charger plugging and unplugging jitter, switching power supply ripple) is filtered out through the resistor R1 (510kΩ)-C1 (100nF) network to avoid false triggering.

[0138] 2. Enhanced hysteresis effect: The base pull-up resistor R4 (100kΩ) of MOSFET Q2 and the drive resistor R3 (510kΩ) form a 1:5 resistance ratio, generating a hysteresis window of about 0.5V, which can suppress voltage fluctuation interference within ±0.5V.

[0139] IV. Wide voltage compatibility:

[0140] Dynamic threshold adaptation: By using the dynamic voltage divider between the emitter and base of MOSFET Q1 (R1-R2 network), the threshold is detected and automatically matched to changes in battery pack voltage (such as 12-60V battery pack system), meeting the voltage boost requirements of various charging protocols, and has better compatibility than fixed threshold solutions.

[0141] V. Rapid Response and Reliability:

[0142] 1. Hardware-accelerated response:

[0143] (1) Charger insertion: After MOSFET Q1 is turned on, the base potential of MOSFET Q2 is quickly pulled down through R3 (510kΩ). The response time is 5ms to ensure that the BMS captures the charging event within 10ms.

[0144] (2) Charger removal: MOSFET Q2 is quickly pulled up and reset via R4 (100kΩ) to avoid misjudgment caused by delay.

[0145] 2. Reverse current blocking: The cathode of diode D1 is connected to C-, which completely blocks the reverse discharge path of the battery pack to the charging interface (leakage current <1nA), avoiding accidental battery damage.

[0146] VI. Environmental adaptability:

[0147] Wide temperature range stability: Through the negative temperature coefficient of the transistor base-emitter voltage (Vbe) and the temperature compensation design of the resistor network, the detection threshold drift is <±3% in the range of -40°C to 85°C, which meets the requirements of automotive-grade applications.

[0148] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the concept of the present utility model and using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included in the patent protection scope of the present utility model.

Claims

1. A charger insertion detection circuit based on discrete components for a BMS battery system, characterized in that, include: Diode D1, capacitor C1, resistor R1, MOSFET Q1, resistor R2, resistor R3, resistor R4, MOSFET Q2, resistor R5, and resistor R6; The cathode of diode D1 is connected to the negative terminal of the charger. The anode of diode D1 is connected to one end of capacitor C1, one end of resistor R1, and the emitter of MOSFET Q1. The other end of capacitor C1 is connected to the other end of resistor R1, one end of resistor R2, and the base of MOSFET Q1. The collector of MOSFET Q1 is connected to one end of resistor R3. The other end of resistor R3 is connected to one end of resistor R4 and the emitter of MOSFET Q2. The other end of resistor R4 and the collector of MOSFET Q2 are connected to the VCC power supply. The base of MOSFET Q2 is connected to one end of resistor R5 and one end of resistor R6. The other end of resistor R5 is grounded, and the other end of resistor R6 is connected to CHARGER_IN.

2. The charger insertion detection circuit based on discrete components for BMS battery systems according to claim 1, characterized in that, The negative terminal of the charger is isolated by the diode D1 to prevent reverse leakage of the battery pack.

3. The charger insertion detection circuit based on discrete components for BMS battery systems according to claim 1, characterized in that, When the charger is plugged in and the voltage is higher than the battery pack voltage, the negative terminal potential of the charger is lower than the GND of the battery pack, forming a voltage difference. The anode voltage of the diode D1 is pulled down, triggering signal coupling.

4. The charger insertion detection circuit based on discrete components for BMS battery systems according to claim 1, characterized in that, The capacitor C1 and the resistor R1 form an RC network, and the emitter of the MOSFET Q1 is connected to the RC network to form a low-pass filter network.

5. The charger insertion detection circuit based on discrete components for a BMS battery system according to claim 1, characterized in that, The resistors R1 and R2 form a voltage divider network. The base of the MOSFET Q1 is set with a conduction threshold through the voltage divider network. When the negative voltage of the charger is effectively pulled down, the base potential of the MOSFET Q1 triggers the conduction condition.

6. The charger insertion detection circuit based on discrete components for a BMS battery system according to claim 1, characterized in that, The resistance ratio of resistor R4 to resistor R3 forms a hysteresis window of 0.6V, which suppresses false triggering caused by voltage fluctuations.

7. The charger insertion detection circuit based on discrete components for a BMS battery system according to claim 1, characterized in that, The resistor R6 limits the instantaneous current when the MOSFET Q2 is turned on, and the resistor R5 provides a definite low level when the charger is not plugged in, to prevent the signal from floating.

8. The discrete-component-based charger insertion detection circuit for a BMS battery system according to any one of claims 1 to 7, characterized in that, The MOSFET Q1 is an NPN type MOSFET, and the MOSFET Q2 is a PNP type MOSFET.

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