Circuit board structure
By setting a buffer layer in the circuit board structure, the problem of brittleness caused by the difference in thermal expansion coefficients between the glass substrate and the conductive pattern is solved, and a balance between structural stability and electrical performance is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- UNIMICRON TECH CORP
- Filing Date
- 2025-04-15
- Publication Date
- 2026-05-26
AI Technical Summary
In existing circuit board structures, the large difference in the coefficients of thermal expansion between the glass substrate and the conductive pattern leads to the problem of glass brittleness.
A buffer layer is provided at the corners or periphery of the conductive pattern to reduce the difference in the coefficient of thermal expansion between the glass substrate and the conductive pattern. By providing a buffer layer at the corners or periphery of the conductive pattern, the concentration of thermal stress is reduced, and glass brittleness is prevented.
It effectively mitigates glass cracking while reducing the impact of the buffer layer on electrical performance.
Smart Images
Figure CN224290143U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to circuit board structures, and more particularly to a circuit board structure with a buffer layer. Background Technology
[0002] With the widespread use of electronic products, these products are required to meet the trend of being thin, light, and small. Ultra-miniature thin chips (UMTCs), for example, can be used in various wearable devices, sensing devices, or high-density system-in-packages (SIPs) due to their extremely miniaturized size and thickness. In some applications, UMTCs use glass substrates as the primary carrier to support the circuit patterns mounted on them. However, the significant difference in the coefficients of thermal expansion between the glass substrate and the conductive patterns can lead to unintended problems. Therefore, while existing circuit board structures have gradually met their intended uses, they are not perfect in every aspect. Thus, further improvements to circuit board structures are still needed. Utility Model Content
[0003] According to some embodiments, a circuit board structure is provided. The circuit board structure includes a glass substrate, a first conductive pattern, and a first buffer layer. The first conductive pattern is disposed on one side of the glass substrate, wherein the first conductive pattern includes a first portion and a second portion, the first portion contacting the glass substrate, and the second portion surrounding the first portion. The first buffer layer is disposed between the second portion and the glass substrate and contacts the glass substrate.
[0004] In some embodiments, in a top view, a portion of the first buffer layer is covered by a first conductive pattern, and another portion of the first buffer layer extends in a direction away from the first conductive pattern.
[0005] In some embodiments, the second portion includes at least one corner, and the first buffer layer is disposed between the at least one corner and the glass substrate.
[0006] In some embodiments, the first buffer layer completely surrounds the first portion.
[0007] In some embodiments, the width of the first buffer layer is between 1 μm and 100 μm.
[0008] In some embodiments, the thickness of the first buffer layer is between 1 μm and 20 μm.
[0009] In some embodiments, the circuit board structure further includes vias and a second conductive pattern. The vias are disposed in the glass substrate and electrically connected to the first conductive pattern. The second conductive pattern is disposed on the other side of the glass substrate and electrically connected to the vias.
[0010] In some embodiments, the second conductive pattern includes a third portion and a fourth portion, the third portion contacting the glass substrate, the fourth portion surrounding the third portion, and the circuit board structure further includes a second buffer layer. The second buffer layer is disposed between the fourth portion and the glass substrate and contacts the glass substrate.
[0011] In some embodiments, in a top view, a portion of the second buffer layer is covered by the second conductive pattern, and another portion of the second buffer layer extends in a direction away from the second conductive pattern.
[0012] In some embodiments, the fourth portion includes at least one corner, and the second buffer layer is disposed between the at least one corner and the glass substrate.
[0013] The circuit board structure of this invention can be applied to various types of electronic devices. To make the components and advantages of this invention more apparent and understandable, various embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description
[0014] The present invention can be more fully understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.
[0015] Figure 1A , Figure 2A , Figure 3A and Figure 4A These are top views showing different stages of the manufacturing process of the circuit board structure according to some embodiments of the present invention.
[0016] Figure 1B , Figure 2B , Figure 3B and Figure 4B These are cross-sectional schematic diagrams showing different stages of the manufacturing process of the circuit board structure according to some embodiments of the present invention.
[0017] Figure 4C This is a cross-sectional schematic diagram of a circuit board structure according to some other embodiments of the present invention.
[0018] Figure 5 This is a top view schematic diagram of the circuit board structure according to some embodiments of the present invention.
[0019] Figure 6 This is a top view schematic diagram of the circuit board structure according to some embodiments of the present invention. Detailed Implementation
[0020] The following provides a detailed description of the apparatus according to various embodiments of the present invention. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of the present invention. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of the present invention. Of course, these are only examples and not limitations on the present invention. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of the present invention. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of the present invention and does not represent any association between the different embodiments and / or structures discussed.
[0021] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number representing the (or plurality of) elements, nor to represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; for example, a first element in the specification may be a second element in the claims.
[0022] In some embodiments of this utility model, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, with other structures disposed between them. Furthermore, these terms may include situations where both structures are movable or both are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.
[0023] In this text, the terms "approximately," "about," and "substantially" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The phrase "the range is between the first value and the second value" indicates that the range includes the first value, the second value, and other values in between. Furthermore, any two values or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error within approximately 10%, 5%, 3%, 2%, 1%, or 0.5% between the first and second values. If the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees. If the first direction is parallel to the second direction, then the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.
[0024] It should be understood that, without departing from the spirit of this utility model, the components in the various embodiments described below can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the utility model or conflict with it.
[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It is understood that such terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this invention.
[0026] Glass, with its low coefficient of thermal expansion (CTE), high insulation, and low loss, is frequently used in circuit board structures. However, a significant difference in the CTE between the glass substrate and the conductive pattern can lead to glass brittleness. For example, during the heating phase of the manufacturing process, the thermal stress caused by the difference in CTE often concentrates at the periphery of the conductive pattern, especially at sharp corners, making these locations particularly prone to glass brittleness.
[0027] To address this issue, the present invention provides a circuit board structure that effectively mitigates glass cracking by providing a buffer layer beneath the corners or peripheries of the conductive pattern. Furthermore, since the buffer layer is only located at the corners or peripheries of the conductive pattern, its impact on electrical performance is effectively reduced.
[0028] Reference Figure 1A , Figure 2A , Figure 3A and Figure 4A These are top views illustrating different stages of the manufacturing process of the circuit board structure according to some embodiments of the present invention. Additionally, see also... Figure 1B , Figure 2B , Figure 3B and Figure 4B These are cross-sectional schematic diagrams showing different stages of the manufacturing process of a circuit board structure according to some embodiments of the present invention. In some embodiments, Figure 1B , Figure 2B , Figure 3B and Figure 4B They are along Figure 1A , Figure 2A , Figure 3A and Figure 4A The figures show cross-sectional views of line segments A-A', B-B', C-C', and D-D'. It is worth noting that, for simplicity and ease of understanding, the dimensions of components and their proportions may be exaggerated in the accompanying drawings. Furthermore, some components in the circuit board structure may be omitted from the figures, but those skilled in the art will understand that the circuit board structure may also include other common components. For example, the circuit board structure of this invention may also include various active components, passive components, heat dissipation components, connectors, and / or protective layers not shown in the figures.
[0029] like Figure 1A and Figure 1B As shown, a glass substrate 10 is provided. In some embodiments, the glass substrate 10 may have two sides opposite to each other (e.g., a first side S1 and a second side S2), and the conductive pattern subsequently formed may be disposed on any one or both sides of the glass substrate 10. In some embodiments, the glass substrate 10 may be or may include borosilicate glass (BSG), quartz glass, alkali-free glass, other suitable materials or combinations thereof, but the present invention is not limited thereto.
[0030] like Figure 2A and Figure 2BAs shown, following the above steps, a through-hole 11 is formed in the glass substrate 10. The through-hole 11 penetrates the glass substrate 10 and connects the first side S1 and the second side S2 of the glass substrate 10. In some embodiments, the through-hole 11 can be formed by laser drilling, dry etching, wet etching, other suitable processes, or combinations thereof, but the present invention is not limited thereto.
[0031] like Figure 3A and Figure 3B As shown, following the above steps, a first buffer layer 12 and a second buffer layer 13 are formed on the glass substrate 10. The first buffer layer 12 is positioned to correspond to a subsequently formed conductive pattern (e.g., a first conductive pattern 14), and the second buffer layer 13 is positioned to correspond to a subsequently formed conductive pattern (e.g., a second conductive pattern 15). Specifically, the first buffer layer 12 is used to mitigate the difference in physical properties (e.g., coefficient of thermal expansion) between the periphery or corner of the first conductive pattern 14 and the glass substrate 10, and the second buffer layer 13 is used to mitigate the difference in physical properties (e.g., coefficient of thermal expansion) between the periphery or corner of the second conductive pattern 15 and the glass substrate 10. In other words, the physical properties (e.g., coefficient of thermal expansion) of the first buffer layer 12 are between those of the first conductive pattern 14 and the glass substrate 10, and the physical properties (e.g., coefficient of thermal expansion) of the second buffer layer 13 are between those of the second conductive pattern 15 and the glass substrate 10.
[0032] It is worth noting that although the coefficient of thermal expansion is used as an example above, the present invention is not limited thereto. In other embodiments, tensile strength, thermal conductivity coefficient, other suitable physical properties, or combinations thereof may be used as selection criteria. In some embodiments, the first buffer layer 12 and / or the second buffer layer 13 may be or may include epoxy resin, polyimide (PI), Ajinomoto build-up film (ABF), other suitable dielectric materials, or combinations thereof, but the present invention is not limited thereto.
[0033] In some embodiments, the width W1 of the first buffer layer 12 and / or the width W2 of the second buffer layer 13 are between 1 μm and 100 μm, but the present invention is not limited thereto. For example, the width W1 of the first buffer layer 12 and / or the width W2 of the second buffer layer 13 can be 1 μm, 10 μm, 20 μm, 30 μm, 50 μm, 75 μm, 100 μm, or any value or range between the above values. When the width W1 of the first buffer layer 12 and / or the width W2 of the second buffer layer 13 is less than 1 μm, the size of the buffer layer may be too small, which is not conducive to buffering the conductive pattern and the glass substrate. Conversely, when the width W1 of the first buffer layer 12 and / or the width W2 of the second buffer layer 13 is greater than 100 μm, the size of the buffer layer may be too large, which is not conducive to the overall electrical properties or subsequent processing. In some embodiments, the width W1 of the first buffer layer 12 and / or the width W2 of the second buffer layer 13 can be a range. For example, the first buffer layer 12 and / or the second buffer layer 13 may have a first width at a first position and a second width at a second position to more precisely buffer different positions of the conductive pattern.
[0034] In some embodiments, the thickness T1 of the first buffer layer and / or the thickness T2 of the second buffer layer 13 are between 1 μm and 20 μm, but the present invention is not limited thereto. For example, the thickness T1 of the first buffer layer 12 and / or the thickness T2 of the second buffer layer 13 can be 1 μm, 2 μm, 5 μm, 10 μm, 12.5 μm, 15 μm, 20 μm, or any value or range between the above values. When the thickness T1 of the first buffer layer 12 and / or the thickness T2 of the second buffer layer 13 is less than 1 μm, the size of the buffer layer may be too small, which is not conducive to serving as a buffer between the conductive pattern and the glass substrate. Conversely, when the thickness T1 of the first buffer layer 12 and / or the thickness T2 of the second buffer layer 13 is greater than 20 μm, the size of the buffer layer may be too large, which may cause the subsequently applied conductive pattern to protrude or become uneven. In some embodiments, the thickness T1 of the first buffer layer 12 and / or the thickness T2 of the second buffer layer 13 can be a range. For example, the first buffer layer 12 and / or the second buffer layer 13 may have a first thickness at a first location and a second thickness at a second location to more precisely buffer different locations of the conductive pattern. In some embodiments, in a cross-sectional view, the buffer layer may also be stepped and have a thickness that gradually increases or decreases from the inside to the outside.
[0035] In some embodiments, in a top view, the first buffer layer 12 and / or the second buffer layer 13 may be a continuous annular pattern to buffer the entire periphery of the conductive pattern. However, the present invention is not limited thereto. In other embodiments, in a top view, the first buffer layer 12 and / or the second buffer layer 13 may also have any shape to buffer the corners or specific locations of the conductive pattern. For example, the first buffer layer 12 and / or the second buffer layer 13 may also be a discontinuous plurality of line segments, or have a triangular shape, a rectangular shape, a polygonal shape, a circular shape, or other suitable shape.
[0036] In some embodiments, the specific patterns of the first buffer layer 12 and the second buffer layer 13 can be designed using Boolean operations, and the first buffer layer 12 and / or the second buffer layer 13 can be formed on the glass substrate 10 through a combination of deposition, photolithography, and etching processes. The deposition process is used to deposit dielectric material (i.e., the material of the buffer layer) and masking material on the glass substrate 10, while the photolithography and etching processes are used to pattern the dielectric material and masking material.
[0037] In some embodiments, the dielectric material may be epoxy resin, polyimide (PI), build-up material (ABF), other suitable dielectric materials, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the masking material may be or may include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, photoresist, other suitable materials, or combinations thereof, but the present invention is not limited thereto.
[0038] In some embodiments, the deposition process may include electroplating, chemical plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), other suitable processes, or combinations thereof, but the present invention is not limited thereto. In some embodiments, the photolithography process may include photoresist application (e.g., spin-on coating, lamination), soft baking, mask alignment, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof, but the present invention is not limited thereto. In some embodiments, the etching process may include dry etching, wet etching, other suitable etching, or combinations thereof, but the present invention is not limited thereto.
[0039] like Figure 4A and Figure 4B As shown, following the above steps, a conductive material is disposed in the through-hole 11 to form a via 16. For example, the conductive material may be aluminum (Al), copper (Cu), their alloys, or compounds, but the present invention is not limited thereto. In some embodiments, a seed layer may be first disposed in the through-hole 11 by physical vapor deposition (PVD), chemical vapor deposition (CVD), other suitable processes, or combinations thereof, and then the conductive material may be filled into the through-hole 11 by electroplating, chemical plating, other suitable processes, or combinations thereof, but the present invention is not limited thereto.
[0040] Following the steps described above, a first conductive pattern 14 is formed on one side (e.g., the first side S1) of the glass substrate 10. Specifically, the first conductive pattern 14 has a first portion 14A and a second portion 14B. The first portion 14A is the inner region of the first conductive pattern 14 and contacts the glass substrate 10. The second portion 14B is the peripheral region or corner of the first conductive pattern 14, and the first buffer layer 12 is located between the second portion 14B and the glass substrate 10. In this way, the problem of brittleness caused by stress (e.g., thermal stress) concentration at the periphery or corner of the first conductive pattern 14 can be avoided.
[0041] In some embodiments, the first conductive pattern 14 may be aluminum (Al), copper (Cu), their alloys, or compounds thereof, but the present invention is not limited thereto. In some embodiments, the first conductive pattern 14 may be formed on the first side S1 of the glass substrate 10 by a combination of deposition, photolithography, and etching processes. Descriptions and examples of each process can be found above and will not be repeated here.
[0042] In some embodiments, in a top view, a portion of the first buffer layer 12 is covered by the first conductive pattern 14, and another portion of the first buffer layer 12 extends away from the first conductive pattern 14. In some embodiments, in a cross-sectional view, the outer side of the first buffer layer 12 is not coplanar with the outer side of the first conductive pattern 14. In other words, the first buffer layer 12 is not completely covered by the first conductive pattern 14, but a portion is exposed from the periphery of the first conductive pattern 14. This configuration improves the buffering effect of the first buffer layer 12. In some cases, it also reduces the alignment accuracy requirement between the first conductive pattern 14 and the first buffer layer 12, thereby further improving the process margin. Of course, the present invention is not limited to this. In other embodiments, in a top view, the first buffer layer 12 may be completely covered by the first conductive pattern 14. In this case, in a cross-sectional view, the outer side of the first buffer layer 12 is coplanar with the outer side of the first conductive pattern 14.
[0043] Following the steps described above, a second conductive pattern 15 is formed on the other side (e.g., the second side S2) of the glass substrate 10. Specifically, the second conductive pattern 15 has a third portion 15A and a fourth portion 15B. The third portion 15A is the inner region of the second conductive pattern 15 and contacts the glass substrate 10. The fourth portion 15B is the peripheral region or corner of the second conductive pattern 15, and the second buffer layer 13 is located between the fourth portion 15B and the glass substrate 10. In this way, the problem of brittleness caused by stress (e.g., thermal stress) concentration at the periphery or corner of the second conductive pattern 15 can be avoided.
[0044] In some embodiments, in a top view, a portion of the second buffer layer 13 is covered by the second conductive pattern 15, and another portion of the second buffer layer 13 extends in a direction away from the second conductive pattern 15. In some embodiments, in a cross-sectional view, the outer side of the second buffer layer 13 is not coplanar with the outer side of the second conductive pattern 15. In a top view, the second buffer layer 13 may also be completely covered by the second conductive pattern 15. In this case, in a cross-sectional view, the outer side of the second buffer layer 13 is coplanar with the outer side of the second conductive pattern 15.
[0045] In some embodiments, the second conductive pattern 15 may be aluminum (Al), copper (Cu), their alloys, or compounds thereof, but the present invention is not limited thereto. In some embodiments, the second conductive pattern 15 may be formed on the second side S2 of the glass substrate 10 by a combination of deposition, photolithography, and etching processes. Descriptions and examples of the various processes can be found above and will not be repeated here.
[0046] As described above, a circuit board structure is obtained, which includes a glass substrate 10, a first conductive pattern 14, a first buffer layer 12, a second conductive pattern 15, a second buffer layer 13, and vias 16. The first conductive pattern 14 is disposed on one side of the glass substrate 10 (e.g., the first side S1), wherein the first conductive pattern 14 includes a first portion 14A and a second portion 14B, the first portion 14A contacting the glass substrate 10, and the second portion 14B surrounding the first portion 14A. The first buffer layer 12 is disposed between the second portion 14B and the glass substrate 10 and contacts the glass substrate 10. The second conductive pattern 15 is disposed on one side of the glass substrate 10 (e.g., the first side S1), wherein the second conductive pattern 15 includes a third portion 15A and a fourth portion 15B, the third portion 15A contacting the glass substrate 10, and the fourth portion 15B surrounding the third portion 15A. The second buffer layer 13 is disposed between the fourth portion 15B and the glass substrate 10 and contacts the glass substrate 10. The guide hole 16 is disposed in the glass substrate 10 and electrically connects the first conductive pattern 14 and the second conductive pattern 15.
[0047] It is worth noting that although some steps and the resulting structure have been described in detail above, they are only for the purpose of making the present invention clearer and easier to understand, and are not intended to limit the present invention. Other possible forms of the present invention will be further described below.
[0048] Reference Figure 4C This is a cross-sectional schematic diagram showing the circuit board structure at different stages of the manufacturing process, according to some embodiments of the present invention. In some embodiments, Figure 4C It can be along Figure 4AThe figure shows a cross-sectional view of line segment D-D'. As shown, when the size of the through hole 11 is large, two or more materials can be used to fill the through hole 11 to form a via 16 containing both conductive and dielectric materials. For example, the through hole 11 can be filled with dielectric material 17, and the dielectric material 17 can be or may include epoxy resin, polyimide (PI), build-up material (ABF), other suitable polymer materials, or combinations thereof, but the present invention is not limited thereto.
[0049] Reference Figure 5 and Figure 6 These are top views illustrating different stages of the manufacturing process of the circuit board structure, according to further embodiments of the present invention. Figure 5 As shown, the first buffer layer 12 can completely surround the first portion 14A of the first conductive pattern 14 to buffer the periphery of the entire first conductive pattern 14. However, the present invention is not limited thereto. Figure 6 As shown, the first buffer layer 12 may partially surround the first portion 14A of the first conductive pattern 14 to buffer a specific area of the entire first conductive pattern 14. For example, the second portion 14B of the first conductive pattern 14 includes at least one corner 14C, and the first buffer layer 12 is disposed between at least one corner 14C and the glass substrate 10. In this way, the total area (or total volume) of the first buffer layer 12 can be reduced to reduce the impact of the first buffer layer 12 on electrical properties or subsequent processes. Similarly, the second buffer layer 13 may completely surround the third portion 15A of the second conductive pattern 15. Alternatively, the fourth portion 15B of the second conductive pattern 15 includes at least one corner (not shown), and the second buffer layer 13 is disposed between at least one corner and the glass substrate 10. In other words, the buffer layer of this invention can be disposed below any position of the conductive pattern as needed.
[0050] In summary, this utility model provides a circuit board structure that effectively mitigates glass cracking by providing a buffer layer below the corners or peripheries of the conductive pattern. Furthermore, since the buffer layer is only located at the corners or peripheries of the conductive pattern, its impact on electrical performance is effectively reduced.
[0051] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the present invention. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.
[0052] [Symbol Explanation]
[0053] 10: Glass substrate
[0054] 11: Through hole
[0055] 12: First Buffer Layer
[0056] 13: Second Buffer Layer
[0057] 14: First conductive pattern
[0058] 14A: Part 1
[0059] 14B: Part Two
[0060] 14C: Corner
[0061] 15: Second conductive pattern
[0062] 15A: Part Three
[0063] 15B: Part Four
[0064] 16: Guide hole
[0065] 17: Dielectric Materials
[0066] A-A': Line segment
[0067] B-B': line segment
[0068] C-C': line segment
[0069] D-D': line segment
[0070] S1: First side
[0071] S2: Second side
[0072] T1: Thickness
[0073] T2: Thickness
[0074] W1: Width
[0075] W2: Width.
Claims
1. A circuit board structure, characterized by, include: Glass substrate; A first conductive pattern is disposed on one side of the glass substrate, wherein the first conductive pattern includes a first portion and a second portion, the first portion contacting the glass substrate, and the second portion surrounding the first portion; and A first buffer layer is disposed between the second portion and the glass substrate, and contacts the glass substrate.
2. The circuit board structure according to claim 1, characterized in that, In the top view, a portion of the first buffer layer is covered by the first conductive pattern, and another portion of the first buffer layer extends in a direction away from the first conductive pattern.
3. The circuit board structure according to claim 1, characterized in that, The second portion includes at least one corner, and the first buffer layer is disposed between the at least one corner and the glass substrate.
4. The circuit board structure according to claim 1, characterized in that, The first buffer layer completely surrounds the first portion.
5. The circuit board structure according to claim 1, characterized in that, The width of the first buffer layer is between 1 μm and 100 μm.
6. The circuit board structure according to claim 1, characterized in that, The thickness of the first buffer layer is between 1 μm and 20 μm.
7. The circuit board structure according to claim 1, characterized in that, Also includes: A guide hole is inserted into the glass substrate and electrically connected to the first conductive pattern; as well as A second conductive pattern is disposed on the other side of the glass substrate and electrically connected to the via.
8. The circuit board structure according to claim 7, characterized in that, The second conductive pattern includes a third portion and a fourth portion, the third portion contacting the glass substrate, the fourth portion surrounding the third portion, and the circuit board structure further includes: The second buffer layer is disposed between the fourth part and the glass substrate and contacts the glass substrate.
9. The circuit board structure according to claim 8, characterized in that, In the top view, a portion of the second buffer layer is covered by the second conductive pattern, and another portion of the second buffer layer extends in a direction away from the second conductive pattern.
10. The circuit board structure according to claim 8, characterized in that, The fourth part includes at least one corner, and the second buffer layer is disposed between the at least one corner and the glass substrate.