Back contact battery grid line structure
By adopting a single-poly multi-sub-grid line and a through-type sub-grid line structure design in the BC battery, and optimizing the sub-grid line shape, the problems of long carrier transport path and high cost are solved, thereby improving battery contact performance and reducing cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HENGDIAN GRP DMEGC MAGNETICS CO LTD
- Filing Date
- 2025-05-09
- Publication Date
- 2026-05-26
Smart Images
Figure CN224290518U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the photovoltaic field, and in particular to a back contact battery grid structure. Background Technology
[0002] Among the many types of photovoltaic cells, BC cells are the most promising next-generation cells after TOPCon cells due to their higher efficiency. Compared with the one-dimensional vertical carrier transport mode of conventional TOPCon cells, the carrier transport mode of BC cells is a combination of horizontal and vertical transport, resulting in a longer carrier transport path and a lower carrier collection probability.
[0003] To improve the carrier collection probability on the back side of BC cells, the current conventional solution is to increase the wet weight of the grid line paste printing, thereby increasing the width and height of the grid lines (CN119486305A). However, this approach undoubtedly not only significantly increases investment costs but also increases the gold / semiconductor contact composite area, reducing the open-circuit voltage of the cell.
[0004] Furthermore, for fully passivated contact batteries (such as TBC batteries), the screen printing process often prints only one grid line in a single poly area (e.g., Figure 1 As shown in (a), this results in a longer path for charge carriers to travel from the poly region to the electrode, which is not conducive to charge carrier collection.
[0005] In summary, how to further shorten the carrier transport path in TBC cells without increasing the wet weight of the grid line paste is crucial for reducing cell costs and improving efficiency. Utility Model Content
[0006] To address the aforementioned technical problems, this invention provides a back-contact battery grid line structure. Through a single-poly multi-sub-grid line and through-type sub-grid line design, this invention can further shorten the carrier transport distance and improve battery contact performance without increasing the overall wet weight of the grid line printing paste.
[0007] The specific technical solution of this utility model includes: a back-contact battery grid line structure, comprising: a main grid p-poly layer and a main grid n-poly layer isolated from each other; at least one secondary grid p-poly layer connected to the main grid p-poly layer; at least one secondary grid n-poly layer connected to the main grid n-poly layer; and p-region main grid lines, n-region main grid lines, p-region secondary grid lines, and n-region secondary grid lines respectively printed on the surfaces of the main grid p-poly layer, the main grid n-poly layer, the secondary grid p-poly layer, and the secondary grid n-poly layer. The p-region secondary grid lines and n-region secondary grid lines are each connected to the p-region main grid lines and the n-region main grid lines, respectively; the number of p-region secondary grid lines and n-region secondary grid lines is at least one.
[0008] As one implementation, the number of p-region subgate lines and n-region subgate lines can be selected from the following:
[0009] (a) The number of sub-gate lines in the p region is 1, and the number of sub-gate lines in the n region is at least 2. More preferably, at least one through-type sub-gate line is provided between the sub-gate lines in the n region, connecting each sub-gate line in the n region.
[0010] (b) The number of sub-gate lines in the p-region is at least 2, and the number of sub-gate lines in the n-region is 1. More preferably, at least one through-type sub-gate line is provided between the sub-gate lines in the p-region, connecting all the sub-gate lines in the p-region.
[0011] (c) The number of sub-gate lines in the p-region is at least 2, and the number of sub-gate lines in the n-region is at least 2. More preferably, at least one through-type sub-gate line is provided between the sub-gate lines in the p-region, and at least one through-type sub-gate line is provided between the sub-gate lines in the n-region, connecting all the sub-gate lines in the n-region.
[0012] Based on the structure of a single poly with multiple sub-gate lines, this invention reprints through-type sub-gate lines, which can balance the potential of multiple sub-gate lines and reduce the brightness and darkness phenomenon in different poly module areas.
[0013] Further preferably, one of the p-region through-type sub-gate lines or n-region through-type sub-gate lines is located at the free end of the p-region sub-gate line or n-region sub-gate line.
[0014] In one implementation, the subgate p-poly layer and the subgate n-poly layer are distributed in an interdigitated pattern.
[0015] In one implementation, when there are multiple n-region sub-gate lines, the gap between two adjacent n-region sub-gate lines increases along their free ends; when there are multiple p-region sub-gate lines, the gap between two adjacent p-region sub-gate lines increases along their free ends.
[0016] To improve carrier transport performance in the sub-grid, the shape of the sub-grid lines can be further optimized, transforming them into a "gradient" triangular sub-grid structure. The principle is as follows: the carrier transport process in a solar cell generally involves electrons or holes generated in the silicon substrate first being led out through the sub-grid (because the sub-grid forms a direct ohmic contact with the silicon substrate through sintering), then transported to the main grid, and finally from the main grid to the PAD point (this location is the contact point for the subsequent module solder ribbon and also the point where the current is ultimately drawn out of the cell). The thickness of the sub-grid lines directly determines the line resistance; thicker lines have lower resistance, and vice versa. Since the sub-grid region near the main grid collects more carriers than the region further away, increasing the width of the sub-grid lines near the main grid reduces the line resistance in this area, resulting in less overall carrier loss at that location, thus facilitating carrier collection across the entire sub-grid.
[0017] In one implementation, the area of the gate line is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which it is located.
[0018] Compared with the prior art, the beneficial effects of this utility model are: through the structural design of single poly multi-sub-grid lines and through-type sub-grid lines, this utility model can further shorten the carrier transmission distance and improve the battery contact performance without increasing the overall wet weight of grid line printing paste (by dividing the printing paste of a single sub-grid line into multiple parts). Attached Figure Description
[0019] Figure 1 The diagram shows the structure of different back contact battery grid lines, including: (a) a single p / n-poly grid line, (b) a single p-poly grid line and two n-poly grid lines, (c) two p-poly grid lines and a single n-poly grid line, and (d) two p-poly grid lines and two n-poly grid lines.
[0020] Figure 2 This is a schematic diagram of a single p / n-poly sub-gate with two through-type gate lines.
[0021] Figure 3 This is a schematic diagram of the structure when the width of the sub-gate line is gradually changing.
[0022] Figure 4 This is a schematic diagram of a structure where the width of the sub-gate line is gradually changing and a through-type sub-gate line is provided.
[0023] The reference numerals in the attached figures are as follows: 1. Main gate p-poly layer; 2. p-region main gate line; 3. Sub-gate p-poly layer; 4. p-region sub-gate line; 5. Main gate n-poly layer; 6. n-region main gate line; 7. Sub-gate n-poly layer; 8. n-region sub-gate line; 9. p-region through-type sub-gate line; 10. n-region through-type sub-gate line. Detailed Implementation
[0024] The present invention will be further described below with reference to the embodiments.
[0025] General Implementation Examples
[0026] A back-contact battery grid structure includes: a main grid p-poly layer and a main grid n-poly layer isolated from each other; at least one secondary grid p-poly layer connected to the main grid p-poly layer; at least one secondary grid n-poly layer connected to the main grid n-poly layer; and p-region main grid lines, n-region main grid lines, p-region secondary grid lines, and n-region secondary grid lines respectively printed on the surfaces of the main grid p-poly layer, the main grid n-poly layer, the secondary grid p-poly layer, and the secondary grid n-poly layer. The p-region secondary grid lines and n-region secondary grid lines are each connected to the p-region main grid line and the n-region main grid line, respectively; the number of p-region secondary grid lines and n-region secondary grid lines is at least one.
[0027] In some preferred embodiments, the number of p-region subgate lines and n-region subgate lines includes the following four different options:
[0028] (a) The number of sub-gate lines in region p is 1, and the number of sub-gate lines in region n is at least 2. In some more preferred embodiments, at least one through-type sub-gate line is provided between the sub-gate lines in region n, connecting each sub-gate line in region n.
[0029] (b) The number of sub-gate lines in the p-region is at least 2, and the number of sub-gate lines in the n-region is 1. In some more preferred embodiments, at least one through-type sub-gate line is provided between the p-region sub-gate lines to connect each p-region sub-gate line.
[0030] (c) The number of sub-gate lines in the p-region is at least 2, and the number of sub-gate lines in the n-region is at least 2. In some more preferred embodiments, at least one through-type sub-gate line is provided between the p-region sub-gate lines to connect each p-region sub-gate line; and at least one through-type sub-gate line is provided between the n-region sub-gate lines to connect each n-region sub-gate line.
[0031] In some more preferred embodiments, one of the p-region through-type sub-gate lines or n-region through-type sub-gate lines is located at the free end of the p-region sub-gate line or n-region sub-gate line.
[0032] In some preferred embodiments, the subgate p-poly layer and the subgate n-poly layer are distributed in an interdigitated pattern.
[0033] In some preferred embodiments, when there are multiple n-region sub-gate lines, the gap between two adjacent n-region sub-gate lines increases along their free ends; when there are multiple p-region sub-gate lines, the gap between two adjacent p-region sub-gate lines increases along their free ends.
[0034] In some preferred embodiments, the area of the gate line is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which it is located. Specific Implementation
[0036] Example 1
[0037] A back-contact battery grid line structure, such as Figure 1 As shown in (b), it includes: a main gate p-poly layer 1 and a main gate n-poly layer 5 isolated from each other; two secondary gate p-poly layers 3 connected to the main gate p-poly layer; two secondary gate n-poly layers 7 connected to the main gate n-poly layer; and p-region main gate lines 2, n-region main gate lines 6, p-region secondary gate lines 4, and n-region secondary gate lines 8 respectively printed on the surfaces of the main gate p-poly layer, the main gate n-poly layer, the secondary gate p-poly layer, and the secondary gate n-poly layer. The p-region secondary gate lines and n-region secondary gate lines are each connected to the p-region main gate lines and the n-region main gate lines, respectively.
[0038] The sub-gate p-poly layer and the sub-gate n-poly layer are distributed in an interdigitated pattern. The area of all gate lines is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which they are located.
[0039] In this embodiment, there is one sub-gate line in the p region and two sub-gate lines in the n region (arranged in parallel, with each n region sub-gate line having the same width).
[0040] Example 2
[0041] A back-contact battery grid line structure, such as Figure 1 As shown in (c), it includes: a main gate p-poly layer 1 and a main gate n-poly layer 5 isolated from each other; two secondary gate p-poly layers 3 connected to the main gate p-poly layer; two secondary gate n-poly layers 7 connected to the main gate n-poly layer; and p-region main gate lines 2, n-region main gate lines 6, p-region secondary gate lines 4, and n-region secondary gate lines 8 respectively printed on the surfaces of the main gate p-poly layer, the main gate n-poly layer, the secondary gate p-poly layer, and the secondary gate n-poly layer. The p-region secondary gate lines and n-region secondary gate lines are each connected to the p-region main gate lines and the n-region main gate lines, respectively.
[0042] The sub-gate p-poly layer and the sub-gate n-poly layer are distributed in an interdigitated pattern. The area of all gate lines is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which they are located.
[0043] In this embodiment, the number of sub-gate lines in the p region is 2 (arranged in parallel, with each p region sub-gate line having the same width), and the number of sub-gate lines in the n region is 1.
[0044] Example 3
[0045] A back-contact battery grid line structure, such as Figure 1 As shown in (d), it includes: a main gate p-poly layer 1 and a main gate n-poly layer 5 isolated from each other; two secondary gate p-poly layers 3 connected to the main gate p-poly layer; two secondary gate n-poly layers 7 connected to the main gate n-poly layer; and p-region main gate lines 2, n-region main gate lines 6, p-region secondary gate lines 4, and n-region secondary gate lines 8 respectively printed on the surfaces of the main gate p-poly layer, the main gate n-poly layer, the secondary gate p-poly layer, and the secondary gate n-poly layer. The p-region secondary gate lines and n-region secondary gate lines are each connected to the p-region main gate lines and the n-region main gate lines, respectively.
[0046] The sub-gate p-poly layer and the sub-gate n-poly layer are distributed in an interdigitated pattern. The area of all gate lines is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which they are located.
[0047] In this embodiment, the number of sub-gate lines in the p region is 2 (arranged in parallel, with each p region sub-gate line having the same width), and the number of sub-gate lines in the n region is 2 (arranged in parallel, with each n region sub-gate line having the same width).
[0048] Example 4
[0049] A back-contact battery grid line structure, such as Figure 2 As shown, it includes: a main gate p-poly layer 1 and a main gate n-poly layer 5 isolated from each other; two secondary gate p-poly layers 3 connected to the main gate p-poly layer; two secondary gate n-poly layers 7 connected to the main gate n-poly layer; and p-region main gate lines 2, n-region main gate lines 6, p-region secondary gate lines 4, and n-region secondary gate lines 8 respectively printed on the surfaces of the main gate p-poly layer, the main gate n-poly layer, the secondary gate p-poly layer, and the secondary gate n-poly layer. The p-region secondary gate lines and n-region secondary gate lines are each connected to the p-region main gate lines and the n-region main gate lines, respectively.
[0050] The sub-gate p-poly layer and the sub-gate n-poly layer are distributed in an interdigitated pattern. The area of all gate lines is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which they are located.
[0051] In this embodiment, there are two p-region sub-gate lines (arranged in parallel, each with the same width), and two n-region sub-gate lines (arranged in parallel, each with the same width). Furthermore, two through-type p-region sub-gate lines 9 connect the p-region sub-gate lines; and two through-type n-region sub-gate lines 10 connect the n-region sub-gate lines. One through-type p-region sub-gate line and one through-type n-region sub-gate line are located at their free ends.
[0052] Example 5
[0053] The difference between this embodiment and Embodiment 1 is that it includes an n-region through-type sub-gate line, as detailed below:
[0054] A back-contact battery grid structure includes: a phase-isolated main grid p-poly layer 1, a main grid n-poly layer 5, two sub-grid p-poly layers 3 connected to the main grid p-poly layer, two sub-grid n-poly layers 7 connected to the main grid n-poly layer, and p-region main grid lines 2, n-region main grid lines 6, p-region sub-grid lines 4, and n-region sub-grid lines 8 respectively printed on the surfaces of the main grid p-poly layer, the main grid n-poly layer, the sub-grid p-poly layer, and the sub-grid n-poly layer. The p-region sub-grid lines and n-region sub-grid lines are each connected to the p-region main grid lines and the n-region main grid lines, respectively.
[0055] The sub-gate p-poly layer and the sub-gate n-poly layer are distributed in an interdigitated pattern. The area of all gate lines is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which they are located.
[0056] In this embodiment, there is one sub-gate line in region p and two sub-gate lines in region n (arranged in parallel, with each sub-gate line having the same width). Furthermore, two through-type sub-gate lines 10 are provided between the sub-gate lines in region n, connecting each sub-gate line. One of these through-type sub-gate lines is located at the free end of the sub-gate line in region n.
[0057] Example 6
[0058] The difference between this embodiment and Embodiment 2 is that a p-region through-type sub-gate line is provided, as detailed below:
[0059] A back-contact battery grid structure includes: a phase-isolated main grid p-poly layer 1, a main grid n-poly layer 5, two sub-grid p-poly layers 3 connected to the main grid p-poly layer, two sub-grid n-poly layers 7 connected to the main grid n-poly layer, and p-region main grid lines 2, n-region main grid lines 6, p-region sub-grid lines 4, and n-region sub-grid lines 8 respectively printed on the surfaces of the main grid p-poly layer, the main grid n-poly layer, the sub-grid p-poly layer, and the sub-grid n-poly layer. The p-region sub-grid lines and n-region sub-grid lines are each connected to the p-region main grid lines and the n-region main grid lines, respectively.
[0060] The sub-gate p-poly layer and the sub-gate n-poly layer are distributed in an interdigitated pattern. The area of all gate lines is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which they are located.
[0061] In this embodiment, there are two p-region sub-gate lines (arranged in parallel, each with the same width), and one n-region sub-gate line. Furthermore, two through-type p-region sub-gate lines 9 are provided between the p-region sub-gate lines, connecting each p-region sub-gate line. One of these through-type p-region sub-gate lines is located at the free end of the p-region sub-gate line.
[0062] Example 7
[0063] The difference between this embodiment and embodiment 6 lies in the number of through-type sub-gate lines in the p-region, as detailed below:
[0064] A back-contact battery grid structure includes: a phase-isolated main grid p-poly layer 1, a main grid n-poly layer 5, two sub-grid p-poly layers 3 connected to the main grid p-poly layer, two sub-grid n-poly layers 7 connected to the main grid n-poly layer, and p-region main grid lines 2, n-region main grid lines 6, p-region sub-grid lines 4, and n-region sub-grid lines 8 respectively printed on the surfaces of the main grid p-poly layer, the main grid n-poly layer, the sub-grid p-poly layer, and the sub-grid n-poly layer. The p-region sub-grid lines and n-region sub-grid lines are each connected to the p-region main grid lines and the n-region main grid lines, respectively.
[0065] The sub-gate p-poly layer and the sub-gate n-poly layer are distributed in an interdigitated pattern. The area of all gate lines is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which they are located.
[0066] In this embodiment, there are two p-region sub-gate lines (arranged in parallel, each with the same width) and two n-region sub-gate lines (arranged in parallel, each with the same width). Furthermore, three through-type p-region sub-gate lines 9 connect the p-region sub-gate lines; and three through-type n-region sub-gate lines 10 connect the n-region sub-gate lines. One through-type p-region sub-gate line and one through-type n-region sub-gate line are located at their free ends, and all through-type p-region and through-type n-region sub-gate lines are equidistantly distributed.
[0067] Example 8
[0068] The difference between this embodiment and embodiment 7 lies in the number of subgate lines in region p and region n, as detailed below:
[0069] A back-contact battery grid structure includes: a phase-isolated main grid p-poly layer 1, a main grid n-poly layer 5, two sub-grid p-poly layers 3 connected to the main grid p-poly layer, two sub-grid n-poly layers 7 connected to the main grid n-poly layer, and p-region main grid lines 2, n-region main grid lines 6, p-region sub-grid lines 4, and n-region sub-grid lines 8 respectively printed on the surfaces of the main grid p-poly layer, the main grid n-poly layer, the sub-grid p-poly layer, and the sub-grid n-poly layer. The p-region sub-grid lines and n-region sub-grid lines are each connected to the p-region main grid lines and the n-region main grid lines, respectively.
[0070] The sub-gate p-poly layer and the sub-gate n-poly layer are distributed in an interdigitated pattern. The area of all gate lines is smaller than that of the main gate p-poly layer or the main gate n-poly layer in which they are located.
[0071] In this embodiment, there are 3 p-region sub-gate lines (arranged in parallel, each with the same width) and 3 n-region sub-gate lines (arranged in parallel, each with the same width). Furthermore, 3 p-region through-type sub-gate lines 9 are provided between the p-region sub-gate lines; and 3 n-region through-type sub-gate lines 10 are provided between the n-region sub-gate lines. One p-region through-type sub-gate line and one n-region through-type sub-gate line are located at their free ends, and all p-region through-type and n-region through-type sub-gate lines are equidistantly distributed.
[0072] Example 9
[0073] The difference between this embodiment and embodiment 4 is that the widths of the subgate lines in region n and region p are gradually changing, i.e., as shown in the figure. Figure 3As shown, the gap between two adjacent n-region subgate lines increases along their free ends, and the gap between two adjacent p-region subgate lines increases along their free ends.
[0074] Example 10
[0075] The difference between this embodiment and embodiment 9 is that: a through-type sub-grid line is provided, that is, as shown in the example below. Figure 4 As shown, an n-region through-type sub-gate line is provided between two adjacent n-region sub-gate lines, and a p-region through-type sub-gate line is connected between the middle positions of two adjacent p-region sub-gate lines.
[0076] In summary, this utility model provides various back contact battery grid line structures with different configurations. Through its single-poly multi-sub-grid line and through-type sub-grid line structural design, this utility model can further shorten the carrier transport distance and improve battery contact performance without increasing the overall wet weight of the grid line printing paste (by dividing the printing paste of a single sub-grid line into multiple portions).
[0077] Unless otherwise specified, the raw materials and equipment used in this utility model are all commonly used in the field; unless otherwise specified, the methods used in this utility model are all conventional methods in the field.
[0078] The above description is merely a preferred embodiment of the present utility model and does not constitute any limitation on the present utility model. Any simple modifications, alterations, or equivalent transformations made to the above embodiments based on the technical essence of the present utility model shall still fall within the protection scope of the present utility model.
Claims
1. A back-contact battery grid line structure, characterized in that: include: The main gate p-poly layer has p-region main gate lines printed on its surface; The secondary gate p-poly layer connected to the main gate p-poly layer has p-region secondary gate lines printed on its surface that are connected to the p-region main gate lines. The main gate n-poly layer has n-region main gate lines printed on its surface; The secondary gate n-poly layer connected to the main gate n-poly layer has n-region secondary gate lines printed on its surface, which are connected to the n-region main gate lines.
2. The back contact battery grid line structure according to claim 1, characterized in that: The p-region subgate line is a single line, while the n-region subgate line is multiple lines.
3. The back contact battery grid line structure according to claim 2, characterized in that: The n-region sub-grid lines are provided with n-region through sub-grid lines; the n-region through sub-grid lines are connected to each n-region sub-grid line in a through manner.
4. The back contact battery grid line structure according to claim 1, characterized in that: The p-region subgate line consists of multiple lines, while the n-region subgate line consists of a single line.
5. The back contact battery grid line structure according to claim 4, characterized in that: A through-type sub-grid line is provided between the sub-grid lines in the p-region; the through-type sub-grid line connects each sub-grid line in the p-region in a through manner.
6. The back contact battery grid line structure according to claim 1, characterized in that: The p-region has multiple sub-gate lines, and the n-region has multiple sub-gate lines.
7. The back contact battery grid line structure according to claim 6, characterized in that: A through-type sub-grid line is provided between the sub-grid lines of the p-region; the through-type sub-grid line connects each sub-grid line of the p-region in a through manner; The n-region sub-grid lines are provided with n-region through sub-grid lines; the n-region through sub-grid lines are connected to each n-region sub-grid line in a through manner.
8. The back contact battery grid line structure according to claim 3, 5, or 7, characterized in that: One of the p-region through-type sub-gate lines is located at the free end of the p-region sub-gate line; and / or One of the n-region through-type sub-gate lines is located at the free end of the n-region sub-gate line.
9. The back contact battery grid line structure according to claim 1, characterized in that: The subgate p-poly layer and the subgate n-poly layer are distributed in an interdigitated pattern.
10. The back contact battery grid line structure according to claim 1, characterized in that: The n-region sub-gate lines are multiple, and the gap width between adjacent n-region sub-gate lines increases along the free end direction of the n-region sub-gate lines; and / or The p-region sub-gate line consists of multiple lines, and the gap width between adjacent p-region sub-gate lines increases along the free end direction of the p-region sub-gate line.