Chip carriers and chips

Abstract

This application provides a wafer carrier and a wafer. The wafer carrier includes a carrier body; the carrier body has a bearing surface; wherein the bearing surface is used to place the wafer; wherein the bearing surface has a first region and a second region, and the roughness of the first region is greater than the roughness of the second region. The wafer provided by this application solves the technical problem in the prior art where wafers easily slide on their carriers, leading to deposition interruptions, equipment downtime, or wafer breakage.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and more specifically, relates to a wafer carrier and a wafer. Background Technology

[0002] During the production process of silicon carbide wafers, wafer slippage can easily occur at the beginning, middle, or end of the production process, which may lead to problems such as deposition interruption, machine downtime, or wafer breakage. Utility Model Content

[0003] The purpose of this application is to provide a wafer carrier and a wafer to solve the technical problem in the prior art where the wafer is prone to sliding on its carrier, leading to deposition interruption, machine downtime or wafer breakage.

[0004] To achieve the above objectives, the technical solution adopted in this application is: to provide a wafer carrier, including a carrier body; the carrier body is provided with a bearing surface; wherein the bearing surface is used to place a wafer; wherein the bearing surface has a first region and a second region, and the roughness of the first region is greater than the roughness of the second region.

[0005] In one alternative embodiment, the ratio of the area of ​​the first region to the area of ​​the second region ranges from 0.6 to 1.5.

[0006] In one alternative embodiment, the first region has one or more, and the second region has one or more; the first region and the second region are staggered on the bearing surface.

[0007] In one alternative embodiment, the second region and the first region are arranged alternately along the circumference of the bearing surface.

[0008] In one alternative embodiment, the second region and the first region are alternately arranged radially along the bearing surface.

[0009] In one optional embodiment, the first region and the second region form a plurality of circular regions along the radial direction of the bearing surface, each circular region including the first region and the second region alternately arranged along the circumferential direction, and the first region and the second region alternately arranged along the radial direction of the bearing surface.

[0010] In one alternative embodiment, the surface of the carrier body is recessed inward with a groove, the bottom surface of the groove forming a bearing surface, and the groove is used to position the periphery of the wafer.

[0011] Another objective of this application is to provide a wafer for use in a wafer carrier. The wafer includes a wafer body, which has a first region and a second region, wherein the roughness of the first region is greater than that of the second region.

[0012] In one alternative embodiment, the ratio of the area of ​​the second region to the area of ​​the first region ranges from 0.6 to 1.5.

[0013] In one alternative embodiment, a first region is provided with one or more, a second region is provided with one or more, and the first region and the second region are arranged alternately on the surface of the wafer body.

[0014] The beneficial effects of the wafer carrier and wafer provided in this application are as follows: Compared with the prior art, the wafer carrier in this application embodiment, by setting a first region and a second region on the bearing surface of the carrier body, and setting the roughness of the first region to be greater than that of the second region, increases the rough surface, increases the friction between the back of the wafer and the surface of the carrier body, ensures that the wafer can obtain sufficient friction support when placed, reduces the risk of wafer slippage, reduces defects caused by wafer displacement, reduces the probability of production interruption, reduces the probability of equipment downtime and product rework, increases the service life of the wafer carrier, and reduces the breakage caused by wafer slippage, so as to avoid contamination of the machine and product scrapping; at the same time, since the smooth surface is conducive to the effective transfer of heat, the smooth surface of the second region ensures sufficient contact area for efficient heat conduction, taking into account the heat conduction between the wafer and the carrier body. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the mating structure between the wafer carrier and the wafer provided in an embodiment of this application;

[0017] Figure 2 A schematic diagram of the bearing surface of the wafer carrier provided in the embodiments of this application. Figure 1 ;

[0018] Figure 3 A schematic diagram of the bearing surface of the wafer carrier provided in the embodiments of this application. Figure 2 ;

[0019] Figure 4 A schematic diagram of the bearing surface of the wafer carrier provided in the embodiments of this application. Figure 3 ;

[0020] Figure 5 A schematic diagram of the bearing surface of the wafer carrier provided in the embodiments of this application. Figure 4 ;

[0021] Figure 6 A schematic diagram of the bearing surface of the wafer carrier provided in the embodiments of this application. Figure 5 .

[0022] The following are the labeling elements in the figure:

[0023] 100 - wafer carrier; 11 - bearing surface; 111 - first region; 112 - second region; 12 - groove; 200 - wafer. Detailed Implementation

[0024] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0025] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0026] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0028] Silicon carbide wafers, with their smooth and hard surfaces, come into contact and rub against the equipment carrier during production. As the carrier becomes smoother, slippage can easily occur between the wafer's back surface and the carrier's surface. This slippage can happen at the beginning, middle, or end of the production process, potentially leading to deposition interruptions, equipment downtime, or wafer breakage. However, the smooth surface also facilitates heat conduction between the carrier and the wafer, maintaining the appropriate processing conditions.

[0029] Based on the above considerations, in order to improve the problem that wafers are prone to sliding on the wafer carrier, which can lead to deposition interruption, machine downtime or wafer breakage, this application provides a wafer carrier 100 and a wafer 200.

[0030] Please refer to the following: Figures 1 to 6 The wafer carrier 100 provided in the embodiments of this application will now be described. This application also provides a wafer carrier 100, including a carrier body (not shown in the figure); the carrier body is provided with a bearing surface 11; wherein, the bearing surface 11 is used to place a wafer; wherein, the bearing surface 11 has a first region 111 and a second region 112, and the roughness of the first region 111 is greater than the roughness of the second region 112.

[0031] The shape of the carrier surface 11 can be circular, rectangular, or hexagonal, etc. During production, the wafer is placed on the carrier surface 11 of the carrier body. The wafer can be a common silicon carbide wafer or a silicon wafer, or it can be a wafer 200 having a first region 111 and a second region 112 as described below; the shape of the wafer can be circular, rectangular, or hexagonal; the surface of the wafer has properties such as smoothness and hardness. The shape of the carrier surface 11 can be adapted to the shape of the wafer, or the area of ​​the carrier surface 11 can be set to be larger than the area of ​​the wafer, with the wafer placed in the middle region of the carrier surface 11.

[0032] By setting a first region 111 and a second region 112 on the carrier body, and setting the roughness of the first region 111 to be greater than that of the second region 112, the coefficient of friction between the bearing surface 11 and the back surface of the wafer can be increased. This ensures that the wafer receives sufficient frictional support during placement, reducing the risk of wafer slippage. Furthermore, the rough surface can be formed by sandblasting, grinding, or spraying.

[0033] The arrangement of the first region 111 and the second region 112 can be staggered, symmetrical, or alternating, forming different patterns on the bearing surface 11, such as radial, spiral, concentric circles, etc.

[0034] Meanwhile, since a smooth surface facilitates efficient heat transfer, while ensuring the temperature uniformity and stability of the wafer throughout the entire processing and meeting the requirements of the process conditions, only a portion of the bearing surface 11 on the carrier body is roughened, retaining some surface smoothness. This helps maintain good thermal conductivity and ensures the temperature uniformity of the wafer throughout the entire processing. In other words, while increasing the roughness of the first region 111, the smooth surface of the second region 112 still ensures sufficient contact area for efficient heat conduction, minimizing the impact on heat conduction while enhancing friction.

[0035] In some embodiments, setting the ratio of the roughness of the first region 111 to the roughness of the second region 112 to a range of 2 to 10 can significantly increase the coefficient of friction between the bearing surface 11 and the back surface of the wafer. Setting this appropriate roughness ratio range can enhance friction without affecting heat conduction, ensuring that heat can be effectively transferred from the carrier to the wafer and distributed uniformly. The carrier body is modified with a minimal surface processing design for the bearing surface 11 to increase the friction of the bearing surface 11, reducing the risk of wafer slippage during processing due to an overly smooth surface. In one embodiment, the roughness of the second region 112 is Ra2, and the roughness of the first region 111 is Ra12; in other embodiments, the roughness of the second region 112 is Ra5, and the roughness of the first region 111 is Ra15.

[0036] Having a stable position for the wafer on the carrier helps maintain the consistency and uniformity of deposition, etching and other process steps, reduces defects caused by wafer displacement, reduces production interruptions, reduces the probability of equipment downtime and product rework, increases the service life of the wafer carrier, reduces wafer breakage caused by wafer slippage, and avoids contamination of the machine and product scrapping.

[0037] When in use, since the design is carried out on the bearing surface 11 of the carrier body, only the carrier body needs to be used for different batches or types of wafers, which can reduce the risk of different types of wafers sliding.

[0038] Compared with the prior art, the wafer carrier 100 provided in this application provides a first region 111 and a second region 112 on the bearing surface 11 of the carrier body. The roughness of the first region 111 is greater than that of the second region 112, which increases the rough surface and the friction between the back of the wafer and the surface of the carrier body. This ensures that the wafer can obtain sufficient friction support when placed, reduces the risk of wafer slippage, reduces defects caused by wafer displacement, reduces the probability of production interruption, reduces the probability of equipment downtime and product rework, increases the service life of the wafer carrier 100, and reduces the breakage caused by wafer slippage, so as to avoid contamination of the machine and product scrapping. At the same time, since the smooth surface is conducive to the effective heat transfer, the smooth surface of the second region 112 ensures sufficient contact area for efficient heat conduction, taking into account the heat conduction between the wafer and the carrier body.

[0039] In another embodiment of this application, see [reference] Figures 2 to 5 The ratio of the area of ​​the first region 111 to the area of ​​the second region 112 ranges from 0.6 to 1.5.

[0040] By reasonably setting the area ratio of the first region 111 and the second region 112, and setting the area ratio of the first region 111 to the second region 112 between 0.6 and 1.5, the friction can be increased without significantly affecting the overall thermal conductivity. This design can provide the necessary friction to prevent slippage without excessively affecting the thermal conductivity. This design ensures that the wafer can be stably fixed on the carrier during the processing, reducing the probability of problems such as deposition interruption, machine downtime or wafer breakage caused by slippage.

[0041] The smooth second region 112 serves as the primary heat conduction path. The presence and area ratio of the second region 112 ensure sufficient contact area for efficient heat conduction. It provides the necessary friction to prevent slippage without unduly affecting heat conduction performance.

[0042] This layout not only reduces the impact of increased roughness on overall thermal conductivity, but also further improves thermal conductivity efficiency by optimizing the position and size of the first region 111, ensuring temperature uniformity and stability of the wafer throughout the entire processing.

[0043] In some embodiments, the ratio of the area of ​​the first region 111 to the area of ​​the second region 112 is 0.6, which helps to improve heat conduction efficiency and ensure the temperature uniformity and stability of the wafer throughout the entire processing.

[0044] In other embodiments, the ratio of the area of ​​the first region 111 to the area of ​​the second region 112 is 1, providing a balanced frictional and thermal conductivity performance, ensuring sufficient friction to prevent slippage while maintaining a good thermal conduction path, and offering high versatility.

[0045] In some other embodiments, the ratio of the area of ​​the first region 111 to the area of ​​the second region 112 is 1.5, providing more friction and helping to prevent the wafer from sliding.

[0046] The ratio of the first region 111 to the second region 112 can be flexibly adjusted according to different manufacturing requirements. For example, in process steps that require higher anti-slip performance, a higher ratio of the first region 111 can be selected; while in cases where higher thermal conductivity is required, the ratio of the second region 112 can be increased.

[0047] In some embodiments, the roughness range of the second region 112 is set to Ra1 to Ra7. All surface roughness units mentioned in this application are in nm (nanometer). Wafers are generally used in semiconductor manufacturing and have low surface roughness, such as Ra0.1 to Ra0.5, to ensure the success of subsequent process steps (such as photolithography, deposition, and etching). Therefore, on the bearing surface 11 of the carrier body, the roughness value of the second region 112 is set to Ra1 to Ra7 to provide good thermal conductivity balance. In one embodiment, the roughness of the second region 112 is set to Ra3, and the roughness of the first region 111 is set to Ra13; in another embodiment, the roughness of the second region 112 is set to Ra5, and the roughness of the first region 111 is set to Ra15; this is used to increase friction and prevent wafer slippage.

[0048] In another embodiment of this application, please refer to Figures 2 to 6 The first region 111 has one or more, and the second region 112 has one or more; the first region 111 and the second region 112 are staggered on the bearing surface 11.

[0049] In this application, "multiple" means two or more. The first region 111 can be set to one, two or three, etc., and the second region 112 can be set to one, two or three, etc.

[0050] The first region 111 and the second region 112 are staggered on the bearing surface 11. They can be one first region 111 and two second regions 112, two first regions 111 and one second region 112, or two first regions 111 and two second regions 112.

[0051] The staggered arrangement can be set to be staggered along the circumference, staggered along the radial direction, staggered in an array, or staggered in a gradient manner. The distribution of the first region 111 and the second region 112 presents a gradient characteristic, such as gradually transitioning from the center to the edge.

[0052] The first region 111 and the second region 112 can be set to the same area and alternate sequentially, or they can be set to different areas and staggered. By staggering the first region 111 and the second region 112, a uniformly distributed frictional force can be formed on the support surface 11. This ensures that regardless of the wafer's position on the support surface 11, it receives sufficient frictional support at different locations. No matter how the wafer is placed or moved, its back side always has sufficient contact surface to provide friction and prevent slippage, avoiding wafer slippage problems caused by insufficient local friction. This ensures that the wafer is stably fixed on the carrier under any circumstances, reducing the probability of deposition interruptions, machine downtime, or wafer breakage due to slippage.

[0053] If the bearing surface 11 is designed in a concentric circle shape, it can be divided into several concentric rings, which are alternately set as the first region 111 and the second region 112. Alternatively, the bearing surface 11 can be divided into multiple sector regions, such as dividing the entire bearing surface 11 into 8 sectors evenly, with 4 of them being the first region 111 and the other 4 being the second region 112, arranged alternately, which can effectively balance the anti-slip requirements and heat conduction performance.

[0054] Furthermore, the smooth second region 112 serves as a heat conduction path, and the staggered arrangement ensures sufficient contact area for efficient heat conduction without significantly reducing heat conduction efficiency due to the presence of the first region 111, thus helping to maintain the temperature uniformity and stability of the wafer throughout the entire processing.

[0055] In another embodiment of this application, please refer to Figures 2 to 5 The second region 112 and the first region 111 are arranged alternately along the circumference of the bearing surface 11.

[0056] By alternately setting the first region 111 and the second region 112 along the circumference of the bearing surface 11, a fan-shaped surrounding structure can be formed on the bearing surface 11. The evenly distributed rough and smooth areas can significantly reduce the possibility of wafer slippage during processing, better control the wafer position, and reduce process inconsistencies caused by wafer position changes.

[0057] Meanwhile, alternating the first region 111 and the second region 112 along the circumference can form a more uniform stress distribution pattern on the bearing surface 11 and ensure the temperature uniformity and stability of the wafer throughout the entire processing.

[0058] In some embodiments, such as Figures 2 to 4There are 12 sectors on the circular bearing surface 11. Each sector is a first region 111 and a second region 112 arranged alternately along the circumference. The first region 111 provides sufficient friction to prevent the wafer from sliding during processing, while the second region 112 maintains good thermal conductivity to ensure uniform temperature of the wafer during processing.

[0059] In other embodiments, such as Figure 3 Each sector has an arc-shaped curved side, and the complex multi-curved arc boundary increases the variation in surface texture, provides more friction contact points and paths, and enhances the overall friction.

[0060] In some other embodiments, such as Figure 4 Each sector has an arc-shaped side. The arc-shaped side design makes the transition between the rough and smooth areas smoother, reduces stress concentration points, and enhances the stability of the wafer during processing.

[0061] In another embodiment of this application, please refer to FIG. 5, the second region 112 and the first region 111 are alternately arranged in the radial direction along the bearing surface 11.

[0062] like Figure 5 Alternating arrangements along the radial direction of the bearing surface 11 can divide the bearing surface 11 into several concentric rings. In one embodiment, as shown... Figure 5 The bearing surface 11 is divided into 5 concentric rings; the first region 111 has 3 rings, and the second region 112 has 2 rings. By adopting the concentric circle design, the friction force on the bearing surface 11 can be evenly distributed, ensuring that the wafer can obtain sufficient friction support at different positions regardless of its position or rotation state, thus avoiding the sliding problem caused by insufficient local friction.

[0063] The concentric circle design is relatively simple and easy to implement. It can be achieved through simple machining, which reduces manufacturing difficulty and cost.

[0064] This design allows for adjustment of the friction distribution based on different wafer processing requirements. For example, in high-load areas (such as near the edge), the proportion of the first region (111) can be increased to enhance friction; while in other areas, the proportion of the smooth region is increased to improve heat conduction efficiency. This improves the stability of the wafer during processing, maintains temperature uniformity and stability throughout the entire process, increases production efficiency, and reduces manufacturing costs.

[0065] In another embodiment of this application, please refer to Figure 6The first region 111 and the second region 112 form a plurality of circular regions along the radial direction of the bearing surface 11. Each circular region includes the first region 111 and the second region 112 arranged alternately along the circumferential direction, and the first region 111 and the second region 112 are arranged alternately along the radial direction of the bearing surface 11.

[0066] like Figure 6 The bearing surface 11 is first divided into multiple circular regions, each containing a first region 111 and a second region 112, that is, a rough surface and a smooth surface. The number of first regions 111 and second regions 112 contained in each circular region can be set to one or more. This arrangement allows the friction distribution to be dynamically adjusted when the wafer moves. That is, in the processing process where the wafer needs to frequently adjust its position or angle, the bearing surface 11 can adaptively provide stable anti-slip performance, ensuring all-round friction support, thus reducing the process inconsistency problems caused by changes in wafer position.

[0067] Regardless of the wafer's position or rotation, the rough surface of each circular area increases the number of contact points, ensuring sufficient frictional support at different locations. This avoids wafer slippage caused by insufficient local friction, ensuring that the wafer can be stably placed on the carrier body and reducing problems such as deposition interruptions, machine downtime, or wafer breakage caused by wafer slippage.

[0068] At the same time, this layout allows for adjustment of the friction distribution according to different wafer process requirements. For example, in high-load areas (such as near the edge), the proportion of the first region can be increased to enhance friction; while in other areas, the proportion of the smooth area can be increased to improve heat conduction efficiency.

[0069] In another embodiment of this application, a groove 12 is recessed inward on the surface of the carrier body, and the bottom surface of the groove 12 forms a bearing surface 11. The groove 12 is used to position the periphery of the wafer.

[0070] By setting the groove 12, a clear positioning point is provided for the wafer, ensuring that the wafer can be positioned in the same location when placed. Operators can more easily and accurately place the wafer in place, which improves the positioning accuracy of the wafer during the processing, increases work efficiency, and reduces process inconsistency problems caused by wafer position deviation.

[0071] The groove 12 can be circular, rectangular or hexagonal; the shape of the groove 12 can be adapted to the shape of the wafer; the bottom surface of the groove 12 forms a support surface 11, which facilitates the placement of the wafer on the support surface 11.

[0072] The depth of the groove 12 is set to 50% to 80% of the wafer thickness. In some embodiments, the wafer thickness is 500 μm to 800 μm, and the depth of the groove 12 is set to 250 μm to 640 μm. μm is the Chinese equivalent of micrometer.

[0073] In addition, the design of the groove 12 can limit the movement range of the wafer to a certain extent, keep the wafer in the predetermined position, prevent the wafer from sliding or shifting during processing, and ensure processing quality and stability.

[0074] Please see Figure 1 This application also provides a wafer 200 for use in a wafer carrier. The wafer 200 includes a wafer body (not shown in the figure), the wafer body has a first region 111 (not shown in the figure) and a second region 112 (not shown in the figure), and the roughness of the first region 111 is greater than the roughness of the second region 112.

[0075] The wafer carrier used for wafer 200 can be wafer carrier 100 as described above, or a general carrier. The type of wafer 200 is a silicon carbide wafer or a silicon wafer, and the shape of wafer 200 can be circular, rectangular, or hexagonal. The surface of wafer 200 has characteristics such as smoothness and hardness.

[0076] By setting a first region 111 and a second region 112 on the wafer body, with the roughness of the first region 111 being greater than that of the second region 112, the coefficient of friction between the back surface of the wafer 200 and the carrier surface can be increased. This reduces the risk of the wafer 200 sliding during processing due to an overly smooth surface, reduces production interruptions, equipment downtime, and the probability of product rework, increases the service life of the wafer carrier 100, reduces wafer breakage caused by wafer 200 sliding, and avoids contamination of the machine and product scrap. The rough surface can be formed by sandblasting, grinding, or spraying.

[0077] The arrangement of the first region 111 and the second region 112 can be staggered, symmetrical, or alternating, forming different patterns on the wafer surface, such as radial, spiral, or concentric circles. Similarly, the shape design of the first region 111 and the second region 112 on the wafer surface can be referenced in the appendix. Figures 2 to 6 In the design of the shape of the first region 111 and the second region 112 on the bearing surface 11 of the vehicle body.

[0078] Meanwhile, since a smooth surface is conducive to the effective transfer of heat, when it is necessary to ensure the temperature uniformity and stability of the wafer 200 throughout the entire processing process and meet the requirements of the process conditions, only a part of the wafer body is roughened, while most of the surface smoothness is retained. This helps to maintain good thermal conductivity and ensure the temperature uniformity of the wafer 200 throughout the entire processing process.

[0079] In one embodiment, the roughness ratio of the first region 111 to the roughness of the second region 112 is set to 2 to 10. This can significantly increase the coefficient of friction between the back surface of the wafer 200 and the carrier surface, reduce defects caused by wafer 200 displacement, and, by setting an appropriate roughness ratio range, enhance friction without affecting heat conduction, ensuring that heat can be effectively transferred from the carrier to the wafer 200 and distributed uniformly. For example, the roughness of the second region 112 is Ra2, and the roughness of the first region 111 is Ra12; in other embodiments, the roughness of the second region 112 is Ra5, and the roughness of the first region 111 is Ra15.

[0080] In another embodiment of this application, the ratio of the area of ​​the second region 112 to the area of ​​the first region 111 ranges from 0.6 to 1.5.

[0081] By reasonably setting the area ratio of the first region 111 and the second region 112, and setting the area ratio of the first region 111 to the second region 112 between 0.6 and 1.5, the friction can be increased without significantly affecting the overall heat conduction performance. This design can provide the necessary friction to prevent slippage without excessively affecting the heat conduction performance. This design ensures that the wafer 200 can be stably fixed on the carrier during the processing, reducing the probability of problems such as deposition interruption, machine downtime, or wafer 200 breakage caused by slippage.

[0082] In some embodiments, the ratio of the area of ​​the first region 111 to the area of ​​the second region 112 is 0.6, which helps to improve heat conduction efficiency and ensure the temperature uniformity and stability of the wafer 200 throughout the entire processing.

[0083] In other embodiments, the ratio of the area of ​​the first region 111 to the area of ​​the second region 112 is 1, providing a balanced frictional and thermal conductivity performance, ensuring that the wafer 200 has sufficient friction to prevent it from sliding on the carrier, while maintaining a good thermal conduction path and high versatility.

[0084] The ratio of the first region 111 to the second region 112 can be flexibly adjusted according to different manufacturing requirements. For example, in process steps that require higher anti-slip performance, a higher ratio of the first region 111 can be selected; while in cases where higher thermal conductivity is required, the ratio of the second region 112 can be increased.

[0085] If the surface of the wafer body is designed in a concentric circle shape, the surface can be divided into several concentric rings, which are alternately set as the first region 111 and the second region 112. Alternatively, the surface of the wafer body can be divided into multiple sector-shaped regions. For example, the entire wafer body surface can be evenly divided into 8 sectors, with 4 being the first region 111 and the other 4 being the second region 112, arranged alternately. In this case, the area ratio of the first region 111 to the second region 112 is 1:1, which can effectively balance the anti-slip requirements and thermal conductivity.

[0086] The wafer 200 is generally used in semiconductor manufacturing and has a low surface roughness. In one embodiment, the roughness value of the second region 112 is set to Ra2, and the roughness of the first region 111 is set to Ra12; in another embodiment, the roughness value of the second region 112 is set to Ra5, and the roughness of the first region 111 is set to Ra15. This is used to increase friction and prevent the wafer 200 from sliding.

[0087] In another embodiment of this application, one or more first regions 111 are provided, and one or more second regions 112 are provided; the plurality of first regions 111 and the plurality of second regions 112 are arranged alternately on the surface of the wafer body.

[0088] In this application, "multiple" means two or more. On the surface of the wafer body, the first region 111 can be set to one, two or three, etc., and the second region 112 can be set to one, two or three, etc.

[0089] The first region 111 and the second region 112 are alternately arranged on the surface of the wafer body. They can be one first region 111 and two second regions 112, two first regions 111 and one second region 112, or two first regions 111 and two second regions 112.

[0090] The staggered arrangement can be set to be staggered along the circumference, staggered along the radial direction, staggered in an array, or staggered in a gradient manner. The distribution of the first region 111 and the second region 112 presents a gradient characteristic, such as gradually transitioning from the center to the edge.

[0091] By alternating the first region 111 and the second region 112, a uniformly distributed frictional force can be formed on the back side of the wafer 200. This ensures that regardless of how the wafer 200 is positioned or moved, its back side always has sufficient contact points to provide additional friction to prevent slippage.

[0092] In some embodiments, the first region 111 and the second region 112 are arranged alternately along the circumference of the wafer body. A fan-shaped, surrounding structure can be formed on the surface of the wafer body along the circumference, with uniformly distributed rough and smooth areas, which can significantly reduce the possibility of the wafer 200 slipping during processing. Through the fan-shaped design, it is ensured that no matter what position or rotation state the wafer 200 is in, the surface design of the wafer body provides sufficient frictional support on the carrier, avoiding the problem of wafer 200 slipping caused by insufficient local friction.

[0093] In other embodiments, the first region 111 and the second region 112 form multiple circular regions along the radial direction of the wafer body. Each circular region includes the first region 111 and the second region 112 alternately arranged circumferentially, and the first region 111 and the second region 112 alternately arranged radially along the wafer body. The surface of the wafer body is first divided into multiple circular regions, each circular region containing the first region 111 and the second region 112, that is, containing a rough surface and a smooth surface. The number of the first region 111 and the second region 112 contained in each circular region can be set to one or more. By alternately arranging smooth and rough regions, a "mesh" stress dispersion structure can be formed, which helps to evenly distribute stress on the surface of the wafer 200. Each circular region contains the first region 111 and the second region 112, that is, containing a rough surface and a smooth surface. The layered fan-shaped layout gives the wafer 200 stable anti-slip performance, ensuring all-round friction support, ensuring that the wafer 200 can be stably placed on the carrier, and reducing problems such as deposition interruption, machine downtime, or wafer 200 damage caused by wafer 200 sliding.

[0094] In some other embodiments, the first region 111 and the second region 112 are arranged alternately along the radial direction of the wafer body. For example... Figure 5 Multiple concentric circular regions are formed radially, which enables the wafer 200 to obtain sufficient frictional support and avoids insufficient local friction. The second region 112 serves as the main heat conduction path. The concentric circular layout ensures sufficient contact area for efficient heat conduction without reducing heat conduction efficiency due to the presence of the first region 111.

[0095] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A wafer carrier, characterized in that, Including the vehicle itself; The carrier body is provided with a bearing surface; wherein, the bearing surface is used to place the wafer; The bearing surface has a first region and a second region, wherein the roughness of the first region is greater than that of the second region.

2. The wafer carrier as claimed in claim 1, characterized in that, The ratio of the area of ​​the first region to the area of ​​the second region ranges from 0.6 to 1.

5.

3. The wafer carrier as described in any one of claims 1-2, characterized in that, The first region has one or more, and the second region has one or more; The first region and the second region are staggered on the bearing surface.

4. The wafer carrier as claimed in claim 3, characterized in that, The second region and the first region are arranged alternately along the circumference of the bearing surface.

5. The wafer carrier as claimed in claim 3, characterized in that, The second region and the first region are alternately arranged radially along the bearing surface.

6. The wafer carrier as claimed in claim 3, characterized in that, The first region and the second region form a plurality of circular regions along the radial direction of the bearing surface. Each circular region includes a first region and a second region that are alternately arranged in the circumferential direction, and the first region and the second region are alternately arranged in the radial direction of the bearing surface.

7. The wafer carrier as described in any one of claims 1 to 2, characterized in that, The surface of the carrier body is recessed inward with a groove, the bottom surface of which forms the bearing surface, and the groove is used to position the periphery of the wafer.

8. A wafer, applied to a wafer carrier, characterized in that, The wafer includes a wafer body, which has a first region and a second region, wherein the roughness of the first region is greater than that of the second region.

9. The wafer as claimed in claim 8, characterized in that, The ratio of the area of ​​the second region to the area of ​​the first region ranges from 0.6 to 1.

5.

10. The wafer as claimed in claim 8, characterized in that, The first region has one or more, and the second region has one or more; The first region and the second region are staggered on the surface of the wafer body.

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