Lead frame and packaging structure

Abstract

The utility model discloses a lead frame and a packaging structure, the lead frame comprises a plurality of pins, gaps are arranged between adjacent pins, and each pin comprises an inner pin area and an outer pin area; the base island is surrounded by the plurality of pins in a spaced mode, an inner pin area of the same pin is closer to the base island than an outer pin area, the front face of the base island comprises a chip area and a connecting area, the chip area is used for arranging a chip, the connecting area is separated from the chip area, at least the connecting area is provided with a silver coating, and the silver coating is coated on the inner pin area. The connecting area is used as a reference ground end to be connected with a plurality of bonding wires, the bonding wires comprise a plurality of first bonding wires and a plurality of second bonding wires, the two ends of the first bonding wires are connected to the chip and the connecting area respectively, the two ends of the second bonding wires are connected to the inner pin area and the connecting area respectively, and the first bonding wires and the second bonding wires are arranged in the connecting area. And the chip is coupled with the plurality of pins through the bonding wires. According to the utility model, the wiring complexity between the chip and the pins can be reduced, the stability of electrical connection is improved, the error rate of contact resistance and signal transmission is reduced, and the influence of ground bounce is reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a lead frame and packaging structure. Background Technology

[0002] With the rapid development of semiconductor technology, electronic products are placing increasingly stringent requirements on the performance, reliability, and heat dissipation of semiconductor chips.

[0003] In semiconductor packaging, the connection method between the chip and the package frame directly affects the overall quality of the product. Traditional die mounting and electrical connection methods have many drawbacks, such as complex wiring between the chip and pins, insufficient electrical connection stability leading to signal transmission interference, and severe ground bounce. Utility Model Content

[0004] The technical problem solved by this utility model is to provide a lead frame and packaging structure to reduce the wiring complexity between the chip and the pins, improve the stability of electrical connection, reduce contact resistance and signal transmission error rate, and reduce the impact of ground bounce.

[0005] To solve the above-mentioned technical problems, the present invention provides a lead frame, comprising: a plurality of pins with gaps between adjacent pins, each pin including an inner pin area and an outer pin area; a base island surrounded by the plurality of pins with gaps, the inner pin area of ​​the same pin being closer to the base island than the outer pin area, the front side of the base island including a chip area and a connection area, the chip area being used to mount a chip, the connection area being separated from the chip area, at least the connection area having a silver plating layer, the connection area being used as a reference ground terminal to connect a plurality of bonding wires, the plurality of bonding wires including a plurality of first bonding wires and a plurality of second bonding wires, the two ends of the first bonding wires being respectively connected to the chip and the connection area, the two ends of the second bonding wires being respectively connected to the inner pin area and the connection area, so that the chip and the plurality of pins are coupled through the bonding wires.

[0006] Optionally, the inner pin area has a silver plating layer.

[0007] Optionally, the chip region has a silver plating layer.

[0008] Optionally, the silver plating layer covers the front side of the base island.

[0009] Optionally, the connection area is a ring-shaped area surrounding the chip area.

[0010] Optionally, the annular region is located at the edge of the front of the base island.

[0011] Optionally, the thickness of the silver plating layer ranges from 70 micrometers to 250 micrometers.

[0012] Accordingly, the present invention also provides a packaging structure, comprising: a lead frame as described above; a chip disposed in the chip area; and a plurality of bonding wires, the plurality of bonding wires including a plurality of first bonding wires and a plurality of second bonding wires, wherein the two ends of the first bonding wires are respectively connected to the chip and the connection area, and the two ends of the second bonding wires are respectively connected to the inner pin area and the connection area.

[0013] Optionally, a conductive adhesive is provided between the chip and the lead frame, and the chip is bonded to the front side of the base island by the conductive adhesive.

[0014] Optionally, the conductive adhesive is a high-temperature resistant epoxy resin mixed with silver powder.

[0015] Optionally, the chip region has a silver plating layer, and the silver plating layer of the chip region is located between the front side of the base island and the conductive adhesive.

[0016] Optionally, the plurality of bonding wires includes at least one of copper wire, copper alloy wire, and gold wire.

[0017] Compared with the prior art, the technical solution of this utility model embodiment has the following beneficial effects:

[0018] In the lead frame and packaging structure provided by the technical solution of this utility model, on the one hand, the front side of the base island includes a chip area for setting the chip and a connection area, and the connection area is separated from the chip area. At least the connection area has a silver plating layer so that the connection area can be used as a reference ground terminal. On the other hand, the connection area is used as a ground terminal to connect several bonding wires so that the chip and the several pins are coupled through the bonding wires. That is to say, the two ends of the first bonding wire are respectively connected to the chip and the connection area, and the two ends of the second bonding wire are respectively connected to the inner pin area and the connection area. Therefore, firstly, for different chips and different interconnection scenarios, both the first and second bonding wires can achieve a nearby relay connection between the chip and the pin through the connection area (after the chip is connected to the reference ground, it is led out again from the reference ground to the pin). This greatly reduces the situation where bonding wires need to cross or avoid each other between the chips and pins that need to be coupled, making the wiring of the bonding wires less affected, more flexible, and occupying less area. Furthermore, the corresponding chip pads and pins can be staggered. Thus, for various interconnection scenarios of various chips, the wiring complexity between the chip and the pin is reduced, the wiring freedom is increased, the correspondence between the pads and the pins is reduced, and the integration density is improved. Secondly, by connecting both the first and second bonding wires to the silver plating layer of the connection area, the stability of the electrical connection can be enhanced, and the contact resistance and signal transmission error rate can be reduced. Especially in high-frequency application scenarios, combined with low-complexity wiring, the reliability of signal transmission can be greatly improved. Thirdly, the shorter bonding wire length from the chip's ground terminal to the nearest strong reference ground results in better signal strength, lower parasitic inductance of the bonding wire, more consistent voltage across the power section, and more uniform current distribution, thus reducing ground bounce. Furthermore, the smaller distance between the strong reference ground and the chip's substrate enhances the absorption of substrate current, thereby reducing interference from substrate current into high-power devices and mitigating latch-up effects. Attached Figure Description

[0019] Figure 1 This is a top view schematic diagram of the packaging structure according to an embodiment of the present invention;

[0020] Figure 2 This is a half-sectional schematic diagram of the packaging structure according to an embodiment of the present invention;

[0021] Figure 3 This is a top view of the lead frame according to an embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures:

[0023] 100 - Lead frame; 110 - Base island; 111 - Chip area; 112 - Connection area; 120 - Pin; 121 - Gap; 122 - Inner pin area; 123 - Outer pin area; 130 - Silver plating layer; 140 - Outer frame; 150 - Connecting rib; 200 - Chip; 310 - First bonding wire; 320 - Second bonding wire; 400 - Conductive adhesive. Detailed Implementation

[0024] As described in the background section, traditional chip mounting and electrical connection methods have many drawbacks, such as complex wiring between the chip and pins, insufficient electrical connection stability leading to signal transmission interference, and severe ground bounce.

[0025] To address the aforementioned technical problems, this utility model provides a lead frame and packaging structure. On one hand, the front side of the base island includes a chip area for mounting the chip and a connection area separated from the chip area. At least the connection area has a silver plating layer, allowing it to serve as a reference ground. On the other hand, the connection area serves as a ground terminal for connecting several bonding wires, coupling the chip and the inner pin area through these bonding wires. Specifically, the two ends of the first bonding wire are connected to the chip and the connection area, respectively, and the two ends of the second bonding wire are connected to the inner pin area and the connection area, respectively. Therefore, the routing complexity between the chip and pins is reduced, electrical connection stability is improved, contact resistance and signal transmission error rate are reduced, and ground bounce is minimized.

[0026] To make the above-mentioned objectives, features, and beneficial effects of this utility model more apparent and understandable, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0027] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.

[0028] Figure 1 This is a top view schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 2 This is a half-sectional schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 3 This is a top view of the lead frame according to an embodiment of the present invention.

[0029] Please refer to Figure 1 and Figure 2 The packaging structure includes: lead frame 100, chip 200, and several bonding wires.

[0030] Please Figure 1 and Figure 2 Based on, refer to Figure 3 The lead frame 100 in this embodiment includes a base island 110 and a plurality of pins 120.

[0031] There is a gap 121 between adjacent pins 120, and each pin 120 includes an inner pin area 122 and an outer pin area 123.

[0032] The base island 110 is surrounded by several pins 120 in the air, and the inner pin area 122 of the same pin 120 is closer to the base island 110 than the outer pin area 123.

[0033] The front side of the base island 110 includes a chip area 111 and a connection area 112.

[0034] Chip area 111 is used to set chip 200, and connection area 112 is separated from chip area 111.

[0035] In this embodiment, a silver plating layer 130 is provided in the connection area 112. The connection area 112 is used as a reference ground terminal GND to connect several bonding wires. The several bonding wires include several first bonding wires 310 and several second bonding wires 320. The two ends of the first bonding wires 310 are respectively connected to the chip 200 and the connection area 112, and the two ends of the second bonding wires 320 are respectively connected to the inner pin area 122 and the connection area 112, so that the chip 200 and several pins 120 are coupled through bonding wires.

[0036] In one embodiment, the inner pin area 122 also has a silver plating layer 130 to further reduce resistance.

[0037] In one embodiment, the chip region 111 also has a silver plating layer 130, which significantly improves the thermal conductivity between the chip 200 and the base island 110, reduces the operating temperature of the chip 200, and extends the service life of the chip 200.

[0038] Furthermore, the silver plating layer 130 can cover the front side of the base island 110 to further reduce resistance.

[0039] Specifically, the thickness of the silver plating layer 130 ranges from 70 micrometers to 250 micrometers. This ensures good conductivity and heat dissipation while avoiding excessive increases in the thickness of the packaging structure.

[0040] In one embodiment, the connection area 112 is a ring-shaped area surrounding the chip area 111. This further improves the ease of wire bonding routing.

[0041] Furthermore, the annular region is located at the edge of the front side of the base island 110. This maximizes the area of ​​the non-silver-plated region of the base island, thereby improving device reliability and reducing the risk of delamination between the silver plating layer and the molding compound.

[0042] In one embodiment, the lead frame 100 further includes an outer frame 140 and a connecting rib 150.

[0043] The outer frame 140 surrounds the base island 110. Several pins 120 are located between the outer frame 140 and the base island 110, and the outer pin area 123 of the pins 120 is connected to the outer frame 140.

[0044] The outer rib 150 is connected to the outer frame 140 and the base island 110 at both ends.

[0045] Please continue to refer to this. Figure 1 and Figure 2 Chip 200 is located in chip area 111.

[0046] Furthermore, conductive adhesive 400 is provided between chip 200 and lead frame 100. The conductive adhesive 400 serves at least for heat transfer between chip 200 and base island 110. On one hand, chip 200 is bonded to the front side of base island 110 via conductive adhesive 400; on the other hand, conductive adhesive 400 can also improve the heat conduction efficiency between chip 200 and base island 110, reduce the operating temperature of chip 200, and extend the lifespan of chip 200.

[0047] Furthermore, conductive adhesive 400 is a high-temperature resistant epoxy resin mixed with silver powder.

[0048] In one embodiment, when the chip region 111 also has a silver plating layer 130, the silver plating layer 130 of the chip region 111 is located between the front side of the base island 110 and the conductive adhesive 400. Therefore, the silver plating layer 130 of the chip region 111 significantly improves the thermal conductivity between the chip 200 and the base island 110, reduces the operating temperature of the chip 200, and extends the lifespan of the chip 200. In particular, by optimizing the synergistic effect of the silver plating layer 130 and the conductive adhesive 400, the thermal resistance can be greatly reduced.

[0049] Please continue to refer to this. Figure 1 and Figure 2 The plurality of bonding wires includes a plurality of first bonding wires 310 and a plurality of second bonding wires 320.

[0050] The two ends of the first bonding wire 310 are connected to the chip 200 and the connection area 112, respectively, and the two ends of the second bonding wire 320 are connected to the inner pin area 122 and the connection area 112, respectively.

[0051] In an embodiment of this utility model, on one hand, the front side of the base island 110 includes a chip area 111 for setting the chip 200 and a connection area 112 separated from the chip area 111, and at least the connection area 112 has a silver plating layer 130 so that the connection area 112 can serve as a reference ground terminal. On the other hand, the connection area 112 is used as a ground terminal to connect several bonding wires so that the chip 200 and several pins 120 are coupled through bonding wires. That is to say, the two ends of the first bonding wire 310 are respectively connected to the chip 200 and the connection area 112, and the two ends of the second bonding wire 320 are respectively connected to the inner pin area 122 and the connection area 112. Therefore, firstly, for different chips 200 and different interconnection scenarios, both the first bonding wire 310 and the second bonding wire 320 can achieve a nearby relay connection between the chip 200 and the pin 120 through the connection area 112 (after the chip 200 is connected to the reference ground, it is led out again from the reference ground to the pin 120). This greatly reduces the situation where the bonding wires between the chip 200 and the pin 120 need to be coupled and need to avoid each other, making the wiring of the bonding wires less affected, more flexible, and occupying less area. Thus, for various interconnection scenarios of various chips 200, the wiring complexity between the chip 200 and the pin 120 is reduced, and the integration is improved. Secondly, by connecting both the first bonding wire 310 and the second bonding wire 320 to the silver plating layer 130 of the connection area 112, the stability of the electrical connection can be enhanced, and the contact resistance and signal transmission bit error rate can be reduced. Especially in high-frequency application scenarios, the combination of low-complexity wiring can significantly improve the reliability of signal transmission. Thirdly, the length of the bonding wire from the ground terminal on chip 200 to the nearest strong reference ground (i.e., the connection area 112 of the reference ground terminal) is shortened. Therefore, not only is the signal better, but the parasitic inductance of the bonding wire is also smaller, the voltage of the power section is more consistent, and the current is more uniform, thereby reducing the impact of ground bounce. In addition, the smaller spacing between the strong reference ground and the chip substrate can also improve the absorption capacity of substrate current, thereby reducing the interference of substrate current on the internal components of high-power devices and weakening the latch-up effect.

[0052] Specifically, the bonding wires include at least one of copper wire, copper alloy wire, and gold wire.

[0053] Before forming the bonding wire, the connection area 112 can be plasma cleaned to remove any dust and organic matter that may be present, ensuring the cleanliness of the bonding wire contact interface.

[0054] It should be noted that, for ease of understanding, Figure 1 The boundary between the chip area and the connection area is indicated by a red line, and the position of the silver plating layer 130 is indicated by a red crosshair. Figure 2 and Figure 3The first solder line 310 is schematically represented by a green line segment, and the second solder line 320 is schematically represented by a blue line segment.

[0055] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A lead frame, characterized in that, include: A plurality of pins, with gaps between adjacent pins, each pin including an inner pin area and an outer pin area; The base island is surrounded by a plurality of pins with a gap. The inner pin area of ​​the same pin is closer to the base island than the outer pin area. The front of the base island includes a chip area and a connection area. The chip area is used to house the chip. The connection area is separated from the chip area and has at least a silver plating layer. The connection area is used as a reference ground terminal to connect a plurality of bonding wires. The plurality of bonding wires include a plurality of first bonding wires and a plurality of second bonding wires. The two ends of the first bonding wires are respectively connected to the chip and the connection area. The two ends of the second bonding wires are respectively connected to the inner pin area and the connection area, so that the chip and the plurality of pins are coupled through the bonding wires.

2. The lead frame according to claim 1, characterized in that, The inner pin area has a silver plating layer.

3. The lead frame according to claim 1, characterized in that, The chip area has a silver plating layer.

4. The lead frame according to claim 3, characterized in that, The silver plating layer covers the front side of the base island.

5. The lead frame according to claim 1, characterized in that, The connection area is a ring-shaped area surrounding the chip area.

6. The lead frame according to claim 5, characterized in that, The annular region is located at the edge of the front of the base island.

7. The lead frame according to any one of claims 1-6, characterized in that, The thickness of the silver plating layer ranges from 70 micrometers to 250 micrometers.

8. A packaging structure, characterized in that, include: The lead frame as described in any one of claims 1-7; A chip, wherein the chip is disposed in the chip area; A plurality of bonding wires, the plurality of bonding wires including a plurality of first bonding wires and a plurality of second bonding wires, wherein the two ends of the first bonding wires are respectively connected to the chip and the connection area, and the two ends of the second bonding wires are respectively connected to the inner pin area and the connection area.

9. The packaging structure according to claim 8, characterized in that, A conductive adhesive is provided between the chip and the lead frame, and the chip is bonded to the front side of the base island by the conductive adhesive.

10. The packaging structure according to claim 9, characterized in that, The conductive adhesive is a high-temperature resistant epoxy resin mixed with silver powder.

11. The packaging structure according to claim 9, characterized in that, The chip region has a silver plating layer, and the silver plating layer of the chip region is located between the front side of the base island and the conductive adhesive.

12. The packaging structure according to claim 8, characterized in that, The plurality of bonding wires includes at least one of copper wire, copper alloy wire, and gold wire.

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