Heterojunction cells and photovoltaic modules

Abstract

The application relates to a heterojunction cell and a photovoltaic module, which comprises a substrate, a first transparent conductive layer and a second transparent conductive layer. The first transparent conductive layer is located on one side of the substrate, the second transparent conductive layer is located on the surface of the first transparent layer and has a first opening, at least part of the first metal electrode is located in the first opening and is in contact with the first transparent conductive layer and the second transparent conductive layer. Since the second transparent conductive layer has the first opening and at least part of the first metal electrode is located in the first opening, the bottom of the first metal electrode is in contact with the first transparent conductive layer and at least part of the sidewall of the first metal electrode is in contact with the second transparent conductive layer, the contact area of the first metal electrode and the transparent conductive layer is increased, thus the contact resistance can be reduced and the conductive capacity of the first metal electrode and the transparent conductive layer is enhanced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a heterojunction cell and photovoltaic module. Background Technology

[0002] This section is intended to provide background or context for the embodiments of the present invention as set forth in the claims. The description herein does not constitute an admission that it is prior art simply because it is included in this section.

[0003] Heterojunction solar cells, with their advantages of fewer fabrication steps, higher efficiency, stronger stability, and bifacial power generation, are highly likely to become the mainstream technology for future photovoltaic cells. Using monocrystalline silicon as the substrate for light absorption, after texturing and cleaning, intrinsic amorphous or microcrystalline silicon thin films and doped layers are fabricated on both sides, forming a PN junction with the silicon substrate. Then, a transparent conductive film is deposited on each side based on the above thin films. Finally, double-sided metal electrodes are fabricated using screen printing technology to obtain a heterojunction solar cell with a symmetrical structure.

[0004] Since screen printing involves attaching metal electrodes to a transparent conductive film, the contact resistance between them affects the cell efficiency. Therefore, reducing the contact resistance between the metal electrodes and the transparent conductive film is a problem that needs to be solved. Utility Model Content

[0005] This application provides a heterojunction cell and photovoltaic module that reduces the contact resistance between the first metal electrode and the transparent conductive layer, thereby at least partially solving the above-mentioned technical problems.

[0006] This application provides a heterojunction battery, comprising: a substrate; a first transparent conductive layer located on one side of the substrate; a second transparent conductive layer located on the surface of the first transparent layer and having a first opening; and a first metal electrode, at least a portion of which is located within the first opening and in contact with the first and second transparent conductive layers.

[0007] In some embodiments, the second transparent conductive layer is located on the sidewall of the first metal electrode.

[0008] In some embodiments, the thickness of the first metal electrode along a first direction is greater than or equal to the thickness of the second transparent conductive layer along the first direction, and the first direction is perpendicular to the surface of the substrate.

[0009] In some embodiments, the system further includes a third transparent conductive layer located on the surface of the first transparent conductive layer away from the first metal electrode and disposed corresponding to the first metal electrode.

[0010] In some embodiments, the substrate includes: a substrate; and a first type semiconductor layer located between the substrate and the first transparent conductive layer.

[0011] In some embodiments, the first type of semiconductor layer has a second opening corresponding to the first metal electrode, and the third transparent conductive layer is embedded in the second opening.

[0012] In some embodiments, the thickness of the third transparent conductive layer along a first direction is equal to the thickness of the first semiconductor layer along the first direction, and the first direction is perpendicular to the surface of the substrate.

[0013] In some embodiments, the thickness of the second transparent conductive layer along the first direction is greater than or equal to the thickness of the first transparent conductive layer along the first direction, and the first direction is perpendicular to the surface of the substrate.

[0014] In some embodiments, the thickness of the first transparent conductive layer along the first direction is 10 nm to 50 nm.

[0015] In some embodiments, the thickness of the second transparent conductive layer along the first direction is 50 nm to 100 nm.

[0016] In some embodiments, the thickness of the second transparent conductive layer along the first direction is greater than or equal to the thickness of the third transparent conductive layer along the first direction, wherein the first direction is perpendicular to the surface of the substrate.

[0017] In some embodiments, the material of the first transparent conductive layer includes a first transparent oxide, the material of the second transparent conductive layer includes a second transparent oxide, and the indium content in the second transparent oxide is less than or equal to the indium content in the first transparent oxide.

[0018] In some embodiments, the first metal electrode includes a fine gate structure, the linewidth of which is less than or equal to 1 micrometer.

[0019] In some embodiments, the surface of the first transparent conductive layer away from the substrate has protrusions.

[0020] In some embodiments, the protruding sidewall is an inclined plane.

[0021] In some embodiments, the protruding sidewall is an arc surface.

[0022] In some embodiments, it further includes: an antireflection layer located on the surface of the second transparent conductive layer and on the sidewall of the first metal electrode.

[0023] In some embodiments, the thickness of the antireflection layer along a first direction is less than the thickness of the first metal electrode along the first direction, and the first direction is perpendicular to the surface of the substrate.

[0024] In some embodiments, the thickness of the antireflection layer along the first direction is 50 nm to 200 nm.

[0025] In some embodiments, the device further includes a second metal electrode located on the surface of the first metal electrode and the surface of the antireflection layer, wherein the second metal electrode is disposed intersecting with the first metal electrode.

[0026] In some embodiments, the substrate further includes: a first intrinsic semiconductor layer located between the first semiconductor layer and the substrate, and a third transparent conductive layer located between the third semiconductor layer and the substrate.

[0027] In some embodiments, the substrate further includes: a second intrinsic semiconductor layer located on the side of the substrate away from the first transparent conductive layer; a second type semiconductor layer located on the surface of the second intrinsic semiconductor layer, wherein the second type is the inverse of the first type; a fourth transparent conductive layer located on the surface of the second type semiconductor layer; and a third metal electrode located on the surface of the fourth transparent conductive layer.

[0028] In some embodiments, it further includes: a fifth transparent conductive layer located on the surface of the fourth transparent conductive layer and having a third opening, wherein at least a portion of the third metal electrode is located within the third opening.

[0029] In some embodiments, the device further includes a fourth metal electrode located on the surface of the third metal electrode and disposed intersecting with the third metal electrode.

[0030] This application also provides a photovoltaic module, including the heterojunction cell described in any of the above embodiments.

[0031] In the heterojunction battery of this application embodiment, since the second transparent conductive layer has a first opening and at least a portion of the first metal electrode is located in the first opening, the bottom of the first metal electrode is in contact with the first transparent conductive layer, and at least a portion of the sidewall of the first metal electrode is in contact with the second transparent conductive layer, thereby increasing the contact area between the first metal electrode and the transparent conductive layer. Therefore, the contact resistance can be reduced and the conductivity between the first metal electrode and the transparent conductive layer can be enhanced.

[0032] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0035] Figure 1 This is a cross-sectional structural schematic diagram of a heterojunction solar cell provided in some embodiments of this application;

[0036] Figure 2 This is a top view schematic diagram of the heterojunction solar cell provided in some embodiments of this application;

[0037] Figure 3 This is a cross-sectional structural schematic diagram of a heterojunction solar cell provided in some embodiments of this application;

[0038] Figures 4 to 11 This is a schematic diagram of the fabrication process of a heterojunction battery provided in some embodiments of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100. Heterojunction solar cell; 1. Substrate; 11. Substrate; 12. First type semiconductor layer; 121. Second opening; 13. First intrinsic semiconductor layer; 2. First transparent conductive layer; 3. Second transparent conductive layer; 31. First opening; 4. First metal electrode; 5. Third transparent conductive layer; 6. Antireflection layer; 7. Second metal electrode; 10. Second intrinsic semiconductor layer; 20. Second type semiconductor layer; 30. Fourth transparent conductive layer; 40. Third metal electrode; 50. Fifth transparent conductive layer; 51. Third opening; 60. Fourth metal electrode. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0042] In some heterojunction solar cells, the contact resistance between the metal electrodes (also known as grid lines) and the transparent conductive film, which are attached by screen printing, affects the cell efficiency. Increasing the width of the metal electrodes to increase the contact area with the transparent conductive layer and reduce the contact resistance will cause grid line shading, reducing light transmittance and worsening light absorption. If the grid lines are made thinner, the contact between the grid lines and the transparent conductive layer will be worse, the contact resistance will be higher, and the current collection ability will be reduced, adversely affecting the cell efficiency.

[0043] Some embodiments of this application provide a heterojunction battery, comprising: a substrate; a first transparent conductive layer located on one side of the substrate; a second transparent conductive layer located on the surface of the first transparent layer and having a first opening; and a first metal electrode, at least a portion of which is located within the first opening and in contact with the first and second transparent conductive layers.

[0044] Since the second transparent conductive layer has a first opening, and at least a portion of the first metal electrode is located within the first opening, the bottom of the first metal electrode is in contact with the first transparent conductive layer, and at least a portion of the sidewall of the first metal electrode is in contact with the second transparent conductive layer. This increases the contact area between the first metal electrode and the transparent conductive layer, thereby reducing the contact resistance and enhancing the conductivity between the first metal electrode and the transparent conductive layer.

[0045] Since the first metal electrode is embedded in the second transparent conductive layer, it can adhere firmly to the second transparent conductive layer, thus ensuring good contact between the first metal electrode and the transparent conductive layer.

[0046] The technical solution of this application can reduce contact resistance without increasing the width or thinning the metal electrode. Therefore, it reduces grid line obstruction, increases the light transmission area, and can promptly introduce charge carriers from the transparent conductive layer (including the first and second transparent conductive layers) to the first metal electrode, shortening the charge carrier transport path, reducing losses during charge carrier transport, improving current extraction, and further enhancing battery efficiency.

[0047] Compared to the case where the first metal electrode is in direct contact with the substrate (i.e., without the first transparent conductive layer), in this embodiment, the first transparent conductive layer is located between the first metal electrode and the substrate. This is beneficial for the first transparent conductive layer to collect current from the entire substrate and concentrate the current to the first metal electrode. Therefore, the first transparent conductive layer is beneficial for the transport of charge carriers and enhances conductivity.

[0048] Compared to the case where the second transparent conductive layer does not have a first opening and covers the sidewall and top of the first metal electrode, in this embodiment, the second transparent conductive layer only covers the sidewall of the first metal electrode. Therefore, the top of the first metal electrode can be exposed to facilitate subsequent contact with another metal electrode on its upper layer, thereby achieving a good conductivity effect.

[0049] The heterojunction solar cell provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0050] Please see Figure 1 , Figure 1 This is a cross-sectional structural diagram of a heterojunction battery provided in some embodiments of this application.

[0051] The heterojunction solar cell 100 includes a substrate 1, a first transparent conductive layer 2, a second transparent conductive layer 3, and a first metal electrode 4. The first transparent conductive layer 2 is located on one side of the substrate 1, and the second transparent conductive layer 3 is located on the surface of the first transparent layer and has a first opening 31. At least a portion of the first metal electrode 4 is located in the first opening 31 and is in contact with the first transparent conductive layer 2 and the second transparent conductive layer 3.

[0052] It is understood that the fact that at least part of the first opening 31 is located within and in contact with the first transparent conductive layer 2 indicates that the first metal electrode 4 is in contact with the first transparent conductive layer 2 through the first opening 31, i.e., the first opening 31 penetrates the first transparent conductive layer 2. In other words, the depth of the first opening 31 along the first direction Z is equal to the thickness of the first transparent conductive layer 2 along the first direction Z, where the first direction Z is the stacking direction of the film layers, i.e., perpendicular to the surface of the substrate 1. Here, the surface of the substrate 1 refers to the upper surface of the substrate 1.

[0053] In some embodiments, the second transparent conductive layer 3 is located on the sidewall of the first metal electrode 4, that is, in contact with the sidewall of the first metal electrode 4, so that charge carriers can be transported using the sidewall of the first metal electrode 4, thereby enhancing conductivity.

[0054] Specifically, the second transparent conductive layer 3 can be located on all sidewalls of the first metal electrode 4, or on a portion of the sidewalls of the first metal electrode 4. When the second transparent conductive layer 3 is located on all sidewalls of the first metal electrode 4, the thickness of the first metal electrode 4 along the first direction Z is equal to the thickness of the second transparent conductive layer 3 along the first direction Z.

[0055] In some embodiments, the thickness of the first metal electrode 4 along the first direction Z is greater than the thickness of the second transparent conductive layer 3 along the first direction Z. Therefore, only a portion of the first metal electrode 4 is embedded in the second transparent conductive layer 3, meaning the second transparent conductive layer 3 is located on a portion of the sidewall of the first metal electrode 4. In other words, the first metal electrode 4 protrudes from the second transparent conductive layer 3. This not only exposes the top surface of the first metal electrode 4 but also leaves space on the second transparent conductive layer 3 for fabricating the anti-reflection layer described below.

[0056] In some embodiments, the first metal electrode 4 has a uniform size along the second direction X, that is, the size of the first metal electrode 4 remains unchanged from top to bottom, and the second direction is perpendicular to the first direction.

[0057] In some embodiments, the thickness of the second transparent conductive layer 3 along the first direction Z is greater than or equal to the thickness of the first transparent conductive layer 2 along the first direction Z, which can increase the contact area between the second transparent conductive layer 3 and the first metal electrode 4 and improve conductivity.

[0058] For example, the thickness of the first transparent conductive layer 2 along the first direction Z is 10nm to 50nm, and the thickness of the second transparent conductive layer 3 along the first direction Z is 50nm to 100nm.

[0059] In some embodiments, the material of the first transparent conductive layer 2 may be the same as the material of the second transparent conductive layer 3. The material of the first transparent conductive layer 2 includes a first transparent oxide, and the material of the second transparent conductive layer 3 includes a second transparent oxide. For example, both the first transparent oxide and the second transparent oxide may include at least one of VTTO, HITO, IMO:H, AZO, FTO, SnOx, and AZO.

[0060] In some embodiments, the material of the first transparent conductive layer 2 may be the same as the material of the second transparent conductive layer 3, for example, both comprising transparent oxides. The material of the first transparent conductive layer 2 comprises a first transparent oxide, and the material of the second transparent conductive layer 3 comprises a second transparent oxide, wherein the indium content in the second transparent oxide is less than or equal to the indium content in the first transparent oxide.

[0061] In some embodiments, the first transparent oxide includes, but is not limited to, at least one of VTTO, HITO, IMO:H, AZO, and FTO.

[0062] In some embodiments, the second transparent oxide may contain less indium than the indium content in the first transparent oxide, and the second transparent oxide may also be indium-free. For example, the second transparent oxide may include at least one of SnOx and AZO.

[0063] Because this embodiment improves the conductivity of the first metal electrode 4 and the transparent conductive layer, the amount of indium material used in the transparent oxide can be reduced while maintaining the same conductivity. Compared to the first transparent conductive layer 2, the area of ​​the second transparent conductive layer 3 is smaller, so the indium content in the second transparent oxide of the second transparent conductive layer 3 can be reduced. Since indium material is expensive, the amount of indium used can be reduced and costs lowered while maintaining the same conductivity.

[0064] Compared to embodiments where all transparent conductive layers use indium-free materials, the combination of the first transparent conductive layer 2 using indium-containing materials and the second transparent conductive layer 3 using indium-free materials can relatively improve carrier mobility.

[0065] In addition, when the second transparent oxide is SnOx, it has strong corrosion resistance, which can improve the corrosion resistance of the second transparent conductive layer 3 and reduce the damage to the second transparent conductive layer 3 caused by the electroplating process.

[0066] In some embodiments, the material of the first metal electrode 4 may include at least one of copper, nickel, gold, and silver. Ultra-fine linewidth gate lines can be fabricated using processes such as patterning to serve as the first metal electrode 4. Other conductive materials with superior performance can also be used as the material of the first metal electrode 4, and this application does not impose any limitations on this.

[0067] In some embodiments, the first metal electrode 4 includes a fine gate structure, the linewidth of which is less than or equal to 1 micrometer. That is, the linewidth of the fine gate structure can reach the nanometer level, thereby reducing gate line shading, increasing the light transmission area, and improving the light absorption effect.

[0068] When the material of the first metal electrode 4 includes copper, a 190nm thick copper layer can be prepared by electroplating first, and then the copper layer can be etched by laser to form the first metal electrode 4; alternatively, a 190nm thick copper layer can be deposited by masking, wherein the size of the mask cutout area is the linewidth of the fine gate structure.

[0069] In some embodiments, the heterojunction cell 100 further includes a third transparent conductive layer 5, which is located on the surface of the first transparent conductive layer 2 away from the first metal electrode 4 and is disposed corresponding to the first metal electrode 4.

[0070] For example, the orthographic projection of the third transparent conductive layer 5 on the substrate 1 coincides with the orthographic projection of the first metal electrode 4 on the substrate 1.

[0071] like Figure 1As shown, since the third transparent conductive layer 5 and the second transparent conductive layer 3 are located on both sides of the first transparent conductive layer 2, and the third transparent conductive layer 5 is disposed corresponding to the first metal electrode 4, while the second transparent conductive layer 3 is located on the side wall of the first metal electrode 4, the provision of the third transparent conductive layer 5 can increase the thickness of the transparent conductive layer at the corresponding position of the first metal electrode 4, reduce the thickness difference of the transparent conductive layer at different positions, and facilitate the transport of charge carriers.

[0072] In some embodiments, the thickness of the second transparent conductive layer 3 along the first direction Z is greater than or equal to the thickness of the third transparent conductive layer 5 along the first direction Z, where the first direction Z is perpendicular to the surface of the substrate 1. When the thickness of the second transparent conductive layer 3 is equal to the thickness of the third transparent conductive layer 5, the thickness of the transparent conductive layer at different locations is equal, which is beneficial to improving the uniformity of the thickness of the transparent conductive layer.

[0073] The material of the third transparent conductive layer 5 may be the same as that of the first transparent conductive layer 2 and / or the second transparent conductive layer 3, for example, it may include at least one of VTTO, HITO, IMO:H, AZO, FTO, SnOx, and AZO.

[0074] The first transparent conductive layer 2, the second transparent conductive layer 3, and the third transparent conductive layer 5 can be made of a variety of high-performance materials stacked together to improve the light transmission effect and high conductivity of the transparent conductive layer.

[0075] The first transparent conductive layer 2, the second transparent conductive layer 3, and the third transparent conductive layer 5 can be formed using plasma reactive deposition (PRD) technology, which can reduce damage to the substrate 1 and ensure that the open-circuit voltage drop is not significant.

[0076] In some embodiments, the substrate 1 may include a substrate 11 and a first type semiconductor layer 12, the first type semiconductor layer 12 being located between the substrate 11 and the first transparent conductive layer 2, and the first type semiconductor layer 12 being used to form a PN junction with the substrate 11.

[0077] The substrate 11 can be a monocrystalline silicon wafer, which can be an N-type silicon wafer or a P-type silicon wafer. The monocrystalline silicon substrate 11 can also be subjected to getter treatment to purify it, effectively reducing the impurity content within the monocrystalline silicon wafer and thereby increasing the effective carrier concentration.

[0078] In some embodiments, the front (upper surface) and back (lower surface) of the substrate 11 are texturized to form protrusions. These protrusions form light-trapping microstructures that effectively reduce light reflection and increase the absorption of sunlight by the silicon wafer. The protrusions resemble a pyramid structure; for example, the front side of the substrate 11 has an upward pyramid structure, and the back side of the substrate 11 has a downward pyramid structure.

[0079] In some embodiments, the first transparent conductive layer 2, the second transparent conductive layer 3, and the first metal electrode 4 may be located on the front side of the substrate 11 or on the back side of the substrate 11.

[0080] In this embodiment, the first transparent conductive layer 2, the second transparent conductive layer 3, and the first metal electrode 4 are located on the front side of the substrate 11.

[0081] In some embodiments, the first type semiconductor layer 12 has a second opening 121 corresponding to the first metal electrode 4, and the third transparent conductive layer 5 is embedded in the second opening 121. That is, the third transparent conductive layer 5 replaces part of the original first type semiconductor layer 12, and the remaining part of the first type semiconductor layer 12 forms a local PN junction with the substrate 11, which can reduce parasitic absorption loss and does not affect electron transport.

[0082] In some embodiments, the thickness of the third transparent conductive layer 5 along the first direction Z is equal to the thickness of the first semiconductor layer 12 along the first direction Z. This elevates the first transparent conductive layer 2 below the first metal electrode 4, ensuring a smooth surface for the first transparent conductive layer 2.

[0083] In some embodiments, the surface of the first transparent conductive layer 2 away from the substrate 1 has protrusions to reduce light reflection.

[0084] In one embodiment, the sidewalls of the protrusion are inclined planes, meaning the protrusion is pyramid-shaped. The pyramid-shaped protrusion can be formed conformally from protrusions on the surface of the substrate 11.

[0085] In another embodiment, the sidewalls of the protrusion are curved. That is, when the surface of the first transparent conductive layer 2 has the same pyramid-shaped protrusion due to conformity with the protrusion on the surface of the substrate 11, the pyramid-shaped protrusion can be micro-processed to form a protrusion with curved sidewalls, which can increase the light trapping effect.

[0086] In some embodiments, the heterojunction solar cell 100 further includes an antireflection layer 6, which is located on the surface of the second transparent conductive layer 3 and on the sidewall of the first metal electrode 4. The antireflection layer 6 can further reduce light reflection and improve light utilization.

[0087] The material of the antireflection layer 6 may include at least one of silicon nitride and zirconium oxide.

[0088] In some embodiments, the thickness of the antireflective layer 6 along the first direction Z is less than the thickness of the first metal electrode 4 along the first direction Z. For example, the sum of the thickness of the antireflective layer 6 and the thickness of the second transparent conductive layer 3 is equal to the thickness of the first metal electrode 4, which can provide a flat surface for forming the second metal electrode described below.

[0089] In some embodiments, the thickness of the antireflection layer 6 can be 50 nm to 200 nm.

[0090] Please combine Figure 2 , Figure 2 This is a top view schematic diagram of the heterojunction battery provided in some embodiments of this application.

[0091] In some embodiments, the heterojunction solar cell 100 further includes a second metal electrode 7, which is located on the surface of the first metal electrode 4 and the surface of the antireflection layer 6, and is arranged intersectingly with the first metal electrode 4. The first metal electrode 4 serves as a fine grid, and the second metal electrode 7 serves as a main grid, for collecting the current collected by the first metal electrode 4.

[0092] Furthermore, the first metal electrode 4 is embedded in the second transparent conductive layer 3. Therefore, when the first metal electrode 4 is connected to the second metal electrode 7, it can withstand greater tensile force, providing a good foundation for subsequent component encapsulation. When the material of the first metal electrode 4 includes copper, the material of the second metal electrode 7 can also be copper. In this case, the first metal electrode 4 can serve as a seed layer, and the second metal electrode 7 with good adhesion to the first metal electrode 4 can be formed using an electroplating process. Therefore, it is compatible with the copper electroplating process.

[0093] In some embodiments, such as Figure 2 As shown, the second metal electrode 7 intersects the first metal electrode 4 perpendicularly, and the first metal electrode 4 and the second metal electrode 7 intersect in a square shape.

[0094] In some embodiments, the layout of the first metal electrode 4 is optimized such that the first metal electrode 4 and the second metal electrode 7 are arranged in a grid (and rhomboid) pattern to further reduce light shading and reflection.

[0095] In some embodiments, the substrate 1 may further include a first intrinsic semiconductor layer 13, which is located between the first type semiconductor layer 12 and the substrate 11, and between the third transparent conductive layer 5 and the substrate 11. The first intrinsic semiconductor layer 13 is used to passivate the substrate 11, and the third transparent conductive layer 5 can also passivate and protect the first intrinsic semiconductor layer 13.

[0096] The first intrinsic semiconductor layer 13 can be an intrinsic hydrogenated amorphous (or microcrystalline) silicon thin film.

[0097] The first intrinsic semiconductor layer 13 and the first type semiconductor layer 12 can be sequentially formed on one side surface of the substrate 11 using a deposition process. The deposition process may include at least one of plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0098] In some embodiments, the heterojunction solar cell 100 may further include a second intrinsic semiconductor layer 10, a second-type semiconductor layer 20, a fourth transparent conductive layer 30, and a third metal electrode 40. The second intrinsic semiconductor layer 10 is located on the side of the substrate 1 away from the first transparent conductive layer 2, and the second-type semiconductor layer 20 is located on the surface of the second intrinsic semiconductor layer 10, wherein the second type is the inverse of the first type. The fourth transparent conductive layer 30 is located on the surface of the second-type semiconductor layer 20, and the third metal electrode 40 is located on the surface of the fourth transparent conductive layer 30, thereby obtaining a structure that can collect current from both the front and back sides.

[0099] Specifically, the second intrinsic semiconductor layer 10, the second type semiconductor layer 20, the fourth transparent conductive layer 30, and the third metal electrode 40 are sequentially stacked from the lower surface of the substrate 11. When the first type semiconductor layer 12 is an N-type semiconductor layer, the second type semiconductor layer 20 is a P-type semiconductor layer; when the first type semiconductor layer 12 is a P-type semiconductor layer, the second type semiconductor layer 20 is an N-type semiconductor layer.

[0100] Please see Figure 3 , Figure 3This is a cross-sectional structural diagram of a heterojunction solar cell provided in some embodiments of this application. For ease of understanding and brief explanation, the same structures as those in the above embodiments will continue to use the same reference numerals, and the same structures will not be described in detail. This embodiment only provides detailed descriptions of different structures.

[0101] The heterojunction solar cell 200 and Figure 1 The difference in the heterojunction cell 100 lies in the structure of the back side of the substrate 11. In this heterojunction cell 200, the back side of the substrate 11 also adopts the same structure as the front side, in order to increase the contact area between the third metal electrode 40 and the transparent conductive layer, reduce the contact electrode between the third metal electrode 40 and the transparent conductive layer, and improve conductivity and cell efficiency.

[0102] like Figure 3 As shown, the heterojunction cell 200 may further include a fifth transparent conductive layer 50, which is located on the surface of the fourth transparent conductive layer and has a third opening 51, with at least a portion of the third metal electrode 40 located within the third opening 51.

[0103] In some embodiments, the heterojunction cell 200 may further include a fourth metal electrode 60, which is located on the surface of the third metal electrode 40 and is disposed intersecting with the third metal electrode 40.

[0104] In this embodiment, the specific structure of the back side of the substrate 11 can be referred to the structure of its front side, and will not be described again here.

[0105] In summary, the embodiments of this application can reduce battery costs while improving the utilization of sunlight and battery conversion efficiency.

[0106] Please combine Figures 4 to 11 , Figures 4 to 11 This is a structural schematic diagram of the fabrication process of a heterojunction battery provided in some embodiments of this application. The heterojunction battery can be fabricated using the following methods.

[0107] See Figure 4 Substrate 11 is provided.

[0108] See Figure 5 The first intrinsic semiconductor layer 13 and the second intrinsic semiconductor layer 10 are formed on the front and back sides respectively using a deposition process.

[0109] See Figure 6 The first type semiconductor layer 12 and the second type semiconductor layer 20 are formed on the front and back sides respectively using a deposition process.

[0110] See Figure 7The first semiconductor layer 12 is etched using photolithography or a mask, and the etched pattern is the location of the first metal electrode 4, without removing the photoresist or mask.

[0111] See Figure 8 A third transparent conductive layer 5 is deposited, with the same thickness as the first type semiconductor layer 12; the photoresist or mask and the third transparent conductive layer 5 on it are removed; and a first transparent conductive layer 2 with a thickness of 10 nm is deposited on this basis.

[0112] See Figure 9 An ultra-fine linewidth first metal electrode 4 with a thickness of 190 nm is fabricated on the first transparent conductive layer 2 using methods including but not limited to patterning.

[0113] See Figure 10 A second transparent conductive layer 3 with a thickness of 90 nm is deposited again by means of masking or etching, and the first metal electrode 4 is exposed. For example, the second transparent conductive layer 3 is deposited after the first metal electrode 4 is covered by a mask.

[0114] See Figure 11 Then, another antireflection layer 6 with a thickness of 100 nm is deposited; the mask and excess second transparent conductive layer 3 and antireflection layer 6 are removed to expose the first metal electrode 4.

[0115] See Figure 2 The second metal electrode 7 is prepared on the exposed first metal electrode 4 by means of electroplating or transfer printing.

[0116] See Figure 1 A fourth transparent conductive layer 30 is deposited on the surface of the second type semiconductor layer 20; a third metal electrode 40 and a fourth metal electrode 60 are sequentially screen-printed or electroplated on the surface of the fourth transparent conductive layer 30.

[0117] In some embodiments, prior to forming the third metal electrode 40, the above method further includes: see Figure 3 The fourth transparent conductive layer 30 is etched using photolithography or a mask, and the etched pattern is the location of the third metal electrode 40, without removing the photoresist or mask.

[0118] The method of forming the third metal electrode 40 may include: depositing a 50 nm thick third metal electrode 40 by means of a mask, wherein the size of the cutout area of ​​the mask is the linewidth of the fine gate in the third metal electrode 40; or first depositing a 50 nm thick copper layer, and then using laser etching to ensure the formation of a continuous third metal electrode 40.

[0119] In some embodiments, prior to forming the fourth metal electrode 60, the above method further includes: see Figure 3 The third metal electrode 40 is covered with a mask, and then a fifth transparent conductive layer 50 with a thickness of 50 nm is deposited. The material can be AZO, FTO, or other materials. Then the mask is removed to expose the third metal electrode 40.

[0120] In some embodiments, the deposition process may include at least one of plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0121] In some embodiments, the thickness of the first transparent conductive layer 2 can be 50 nm, the thickness of the first metal electrode 4 can be 150 nm, the thickness of the second transparent conductive layer 3 can be 50 nm, and the thickness of the antireflection layer 6 can be 100 nm.

[0122] In some embodiments, the thickness of the fourth transparent conductive layer 30 is 50 nm.

[0123] This application also provides a photovoltaic module, including the heterojunction cell in any of the above embodiments. This photovoltaic module has the same beneficial effects as the heterojunction cell, and will not be described again here.

[0124] The photovoltaic module can be applied to solar-powered cars or solar-assisted vehicles, etc., and this application does not make any specific limitations on it.

[0125] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0126] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0127] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0128] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A heterojunction battery, characterized in that, include: Matrix; A first transparent conductive layer is located on one side of the substrate; A second transparent conductive layer is located on the surface of the first transparent conductive layer and has a first opening; A first metal electrode, at least a portion of which is located within the first opening and in contact with the first transparent conductive layer and the second transparent conductive layer; A third transparent conductive layer is located on the surface of the first transparent conductive layer away from the first metal electrode, and is disposed corresponding to the first metal electrode.

2. The heterojunction solar cell according to claim 1, characterized in that, The second transparent conductive layer is located on the sidewall of the first metal electrode.

3. The heterojunction solar cell according to claim 2, characterized in that, The thickness of the first metal electrode along the first direction is greater than or equal to the thickness of the second transparent conductive layer along the first direction, and the first direction is perpendicular to the surface of the substrate.

4. The heterojunction solar cell according to claim 1, characterized in that, The matrix includes: Substrate; A first type of semiconductor layer is located between the substrate and the first transparent conductive layer.

5. The heterojunction battery according to claim 4, characterized in that, The first type of semiconductor layer has a second opening corresponding to the first metal electrode, and the third transparent conductive layer is embedded in the second opening.

6. The heterojunction battery according to claim 5, characterized in that, The thickness of the third transparent conductive layer along the first direction is equal to the thickness of the first semiconductor layer along the first direction, and the first direction is perpendicular to the surface of the substrate.

7. The heterojunction solar cell according to claim 1, characterized in that, The thickness of the second transparent conductive layer along the first direction is greater than or equal to the thickness of the first transparent conductive layer along the first direction, and the first direction is perpendicular to the surface of the substrate.

8. The heterojunction battery according to claim 7, characterized in that, The thickness of the first transparent conductive layer along the first direction is 10nm~50nm.

9. The heterojunction battery according to claim 6, characterized in that, The thickness of the second transparent conductive layer along the first direction is 50nm~100nm.

10. The heterojunction solar cell according to claim 1, characterized in that, The thickness of the second transparent conductive layer along the first direction is greater than or equal to the thickness of the third transparent conductive layer along the first direction, and the first direction is perpendicular to the surface of the substrate.

11. The heterojunction solar cell according to claim 1, characterized in that, The material of the first transparent conductive layer includes a first transparent oxide, and the material of the second transparent conductive layer includes a second transparent oxide, wherein the indium content in the second transparent oxide is less than or equal to the indium content in the first transparent oxide.

12. The heterojunction solar cell according to claim 1, characterized in that, The first metal electrode includes a fine grid structure, the linewidth of which is less than or equal to 1 micrometer.

13. The heterojunction solar cell according to claim 1, characterized in that, The surface of the first transparent conductive layer away from the substrate has protrusions.

14. The heterojunction solar cell according to claim 13, characterized in that, The sidewall of the protrusion is an inclined plane.

15. The heterojunction solar cell according to claim 13, characterized in that, The sidewall of the protrusion is curved.

16. The heterojunction solar cell according to claim 1, characterized in that, Also includes: An antireflective layer is located on the surface of the second transparent conductive layer and on the sidewall of the first metal electrode.

17. The heterojunction solar cell according to claim 16, characterized in that, The thickness of the antireflection layer along the first direction is less than the thickness of the first metal electrode along the first direction, and the first direction is perpendicular to the surface of the substrate.

18. The heterojunction solar cell according to claim 17, characterized in that, The thickness of the antireflective layer along the first direction is 50nm~200nm.

19. The heterojunction solar cell according to claim 16, characterized in that, Also includes: The second metal electrode is located on the surface of the first metal electrode and the surface of the antireflection layer, and the second metal electrode is arranged intersecting with the first metal electrode.

20. The heterojunction solar cell according to claim 4, characterized in that, The matrix also includes: The first intrinsic semiconductor layer is located between the first type semiconductor layer and the substrate, and between the third transparent conductive layer and the substrate.

21. The heterojunction solar cell according to claim 4, characterized in that, Also includes: The second intrinsic semiconductor layer is located on the side of the substrate away from the first transparent conductive layer; A second type semiconductor layer is located on the surface of the second intrinsic semiconductor layer, and the second type is the inverse of the first type. A fourth transparent conductive layer is located on the surface of the second type semiconductor layer; The third metal electrode is located on the surface of the fourth transparent conductive layer.

22. The heterojunction solar cell according to claim 21, characterized in that, Also includes: A fifth transparent conductive layer is located on the surface of the fourth transparent conductive layer and has a third opening, with at least a portion of the third metal electrode located within the third opening.

23. The heterojunction solar cell according to claim 22, characterized in that, Also includes: The fourth metal electrode is located on the surface of the third metal electrode and is arranged intersecting with the third metal electrode.

24. A photovoltaic module, characterized in that, Including the heterojunction solar cell according to any one of claims 1 to 23.

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