An integrated watchdog reset device for multiple trigger sources

Abstract

The utility model belongs to the field of aircraft electromechanical control, relates to a kind of integrated watchdog reset device of multiple trigger source.Electric power management circuit component, watchdog logic processing component, reset source comprehensive processing component are included.The integrated watchdog reset device of multiple trigger source of this, can guarantee +5V power reset, power recovery reset, external watchdog timeout reset and the reset of a variety of reset source comprehensive reliablely, and the device has the advantages of less device type quantity, small size, high reliability.

Description

Technical Field

[0001] This utility model belongs to the field of aircraft electromechanical control and relates to an integrated watchdog reset device with multiple trigger sources. Background Technology

[0002] With the rapid development of more-electric aircraft, the use of electric drive controllers in airborne equipment is increasing. These controllers typically utilize CPU processors such as DSPs for algorithmic logic processing, leading to increasingly stringent reliability requirements. To prevent software malfunctions and other anomalies in the electric drive control, reliable CPU resets are necessary to ensure mission reliability. Multiple reset sources for electric drive controllers should include +5V power-on reset, power-off recovery reset, and external watchdog timeout reset. Traditional reset circuits may only have a single trigger source, such as the CPU's timed watchdog signal. In multi-sequential load electric drive control systems, multiple anomalies, including power-on and power-off, need to be addressed to ensure reliable operation under various complex abnormal conditions. This multi-trigger integrated watchdog reset device provides a comprehensive and reliable reset from multiple sources, including +5V power-on reset, power-off recovery reset, and external watchdog timeout reset. The device boasts advantages such as fewer component types, smaller size, and higher reliability. It has already been successfully applied in a certain type of aircraft. Utility Model Content

[0003] Utility Model Purpose

[0004] The purpose of this invention is to provide an integrated watchdog reset device with multiple trigger sources. The multi-channel electrical function is fully automated by hardware, requiring no external command signals. The device integrates multiple reset sources, including +5V power-on reset, power-off recovery reset, and external watchdog timeout reset, providing comprehensive and reliable reset capabilities.

[0005] Technical solution

[0006] An integrated watchdog reset device with multiple trigger sources includes a power management circuit component, a watchdog logic processing component, and a reset source integrated processing component.

[0007] The power management circuit assembly includes resistors R1 and R2. One end of R1 is connected to the monitoring power supply VCC1, and the other end is connected to one end of R2. The other end of R2 is connected to the negative terminal of the monitoring power supply VCC1. The voltage divider between R1 and R2 is connected to pin 4 of U1.

[0008] The watchdog logic processing component includes a watchdog reset chip U1 and a resistor R3. The power supply VCC and GND are connected to pins 2 and 3 of the watchdog reset chip U1, respectively. One end of the resistor R3 is connected to VCC, and the other end is connected to pin 1 of U1. Pin 6 of the watchdog reset chip U1 is responsible for receiving the periodic feed signal, and pin 7 of the watchdog reset chip U1 is responsible for outputting the reset signal.

[0009] The reset source processing component includes a logic AND gate N1. The connection relationship is as follows: pin 5 of the watchdog reset chip U1 is connected to pin 1 of N1, pin 6 of the watchdog reset chip U1 is connected to pin 2 of N1, and pin 3 of N1 is connected to pin 1 of chip U1.

[0010] Furthermore, the JS706T-25 hardware reset management chip is used to manage the reset source.

[0011] Furthermore, the watchdog reset chip U1 includes functions such as power-on reset, watchdog timer overflow, power undervoltage warning, power undervoltage reset, and external hardware reset.

[0012] Furthermore, the operation of the reset function circuit is explained as follows:

[0013] (1) When the chip's VCC voltage reaches 1V, the RESET port outputs a low level. The VCC voltage gradually increases, and when it exceeds the reset voltage threshold, the low level output by the RESET terminal is removed after a typical duration of 25ms, the circuit reset is complete, and the watchdog starts working;

[0014] Furthermore, (2) when the VCC voltage gradually decreases and falls below the reset voltage threshold, the RESET port outputs a low level. This is an external reset function; when the MR port is low, the RESET port outputs a low level.

[0015] Furthermore, (3) if there is no toggle signal input to WDI within the typical watchdog overflow time of 1.6s, the WDO port outputs a low level; otherwise, the WDO port outputs a high level. The control channel and the monitoring channel DSP send the inverted level to the JS706T-25 through the GPIO pin at 500ms intervals to realize hardware watchdog feeding.

[0016] Furthermore, (4) power undervoltage warning function: when the PFI port voltage is higher than the typical value of 1.25V, the PFO port outputs a high level, otherwise it outputs a low level; the PFO signal and the WDO signal in (3) are connected to the RESET_COM signal through an AND gate and connected to the MR of the reset chip. The low level output of either of the reset sources in (3) and (4) can enable the DSP to perform an effective reset.

[0017] The beneficial effects of this application are as follows:

[0018] Compared to traditional reset source circuits that may only have a single trigger source for reset, such as the CPU's timed watchdog signal, this invention, in a multi-sequential load electric drive control system, needs to include handling of various abnormal situations such as power-on and power-off to ensure reliable operation of the electric drive control system under various complex abnormal conditions. This multi-trigger integrated watchdog reset device can reliably reset through a combination of multiple reset sources, including +5V power-on reset, power-off recovery reset, and external watchdog timeout reset. The device has advantages such as fewer component types, smaller size, and higher reliability. Attached Figure Description

[0019] Figure 1 A schematic diagram of the connection of an integrated watchdog reset device with multiple trigger sources;

[0020] Figure 2 Hardware watchdog circuit diagram;

[0021] Figure 3 Reset source integrated circuit. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions in the embodiments of this utility model will be described in more detail below with reference to the embodiments of this utility model. In the examples, the same or similar reference numerals denote the same or similar components or elements having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this utility model. The embodiments described below with reference to the embodiments are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. The embodiments of this utility model will be described in detail below with reference to their specific implementation.

[0023] An integrated watchdog reset device with multiple trigger sources includes three components: a power management circuit component, a watchdog logic processing component, and a reset source integrated processing component.

[0024] The power management circuit assembly includes resistors R1 and R2. One end of R1 is connected to the monitoring power supply VCC1, and the other end is connected to one end of R2. The other end of R2 is connected to the negative terminal of the monitoring power supply VCC1. The voltage divider between R1 and R2 is connected to pin 4 of U1.

[0025] The watchdog logic processing component includes a watchdog reset chip U1 and a resistor R3. The power supply VCC and GND of chip U1 are connected to pins 2 and 3 of U1, respectively. One end of resistor R3 is connected to VCC, and the other end is connected to pin 1 of U1. Pin 6 of chip U1 is responsible for receiving the periodic watchdog feed signal, and pin 7 of chip U1 is responsible for outputting the reset signal.

[0026] The reset source processing component includes a logic AND gate N1. The connection relationship is as follows: pin 5 of chip U1 is connected to pin 1 of N1, pin 6 of chip U1 is connected to pin 2 of N1, and pin 3 of N1 is connected to pin 1 of chip U1.

[0027] The reset function circuit diagram of the DSP is as follows: Figure 2 As shown, the JS706T-25 hardware reset management chip is used to manage the reset source. This chip's functions include power-on reset, watchdog timer overflow, undervoltage warning, undervoltage reset, and external hardware reset. The operation of its reset function circuit is described below:

[0028] (1) When the chip's VCC voltage reaches 1V, the RESET port outputs a low level. The VCC voltage gradually increases, and when it exceeds the reset voltage threshold, the low level output by the RESET terminal typically lasts for 25ms before being removed, completing the circuit reset and the watchdog timer begins operation. Figure 2 As shown;

[0029] (2) When the VCC voltage gradually decreases and falls below the reset voltage threshold (typically 3.15V), the RESET port outputs a low level. This is an external reset function; when the MR port is low, the RESET port outputs a low level, such as... Figure 2 As shown;

[0030] (3) If there is no toggle signal input to WDI within the typical watchdog overflow time of 1.6s, the WDO port outputs a low level; otherwise, the WDO port outputs a high level. The control channel and monitoring channel DSP send an inverted level to the JS706T-25 through GPIO pins at 500ms intervals to implement hardware watchdog feeding. Figure 2 As shown;

[0031] (4) Undervoltage warning function: When the PFI port voltage is higher than the typical value of 1.25V, the PFO port outputs a high level; otherwise, it outputs a low level. The PFO signal and the WDO signal in (3) are connected to the MR of the reset chip through an AND gate to form a RESET_COM signal. The low level output of either reset source in (3) and (4) can enable the DSP to perform an effective reset, such as... Figure 3 As shown;

[0032] Furthermore, unless otherwise defined, the technical or scientific terms used in this application description shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "upper," "lower," "left," "right," "center," "vertical," "horizontal," "inner," and "outer," etc., used in this application description to indicate relative direction or positional relationship are used only to indicate relative orientation or positional relationship, and do not imply that the device or component must have a specific orientation, or be constructed and operated in a specific orientation. When the absolute position of the described object changes, its relative positional relationship may also change accordingly, and therefore should not be construed as a limitation on this application. The terms "first," "second," "third," and similar terms used in this application description are used only for descriptive purposes to distinguish different components, and should not be construed as indicating or implying relative importance. The terms "a," "one," or "the," etc., used in this application description should not be construed as an absolute limitation on quantity, but should be construed as indicating the existence of at least one. The terms "including," "comprising," etc., used in this application description mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0033] Furthermore, it should be noted that, unless otherwise explicitly specified and limited, terms such as “installation,” “connection,” and “linkage” used in the description of this application should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; or it can be a connection within two components. Those skilled in the art can understand its specific meaning in this application according to the specific circumstances.

[0034] The above description is merely a specific embodiment of this utility model and is not intended to limit this utility model. Within the spirit and principles of this utility model, any person skilled in the art may use the above-disclosed technical content to make changes or modifications to equivalent embodiments for application in other fields. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of this utility model without departing from the technical solution of this utility model, as well as any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of this utility model.

Claims

1. An integrated watchdog reset device with multiple trigger sources, characterized in that, This includes power management circuit components, watchdog logic processing components, and reset source integrated processing components; The power management circuit assembly includes resistors R1 and R2. One end of R1 is connected to the monitoring power supply VCC1, and the other end is connected to one end of R2. The other end of R2 is connected to the negative terminal of the monitoring power supply VCC1. The voltage divider between R1 and R2 is connected to pin 4 of U1. The watchdog logic processing component includes a watchdog reset chip U1 and a resistor R3. The power supply VCC and GND are connected to pins 2 and 3 of the watchdog reset chip U1, respectively. One end of the resistor R3 is connected to VCC, and the other end is connected to pin 1 of U1. Pin 6 of the watchdog reset chip U1 is responsible for receiving the periodic feed signal, and pin 7 of the watchdog reset chip U1 is responsible for outputting the reset signal. The reset source processing component includes a logic AND gate N1. The connection relationship is as follows: pin 5 of the watchdog reset chip U1 is connected to pin 1 of N1, pin 6 of the watchdog reset chip U1 is connected to pin 2 of N1, and pin 3 of N1 is connected to pin 1 of chip U1.

2. The apparatus as claimed in claim 1, characterized in that, The JS706T-25 hardware reset management chip is used to manage the reset source.

3. The apparatus as described in claim 2, characterized in that, The watchdog reset chip U1 has the following functions: power-on reset, watchdog timer overflow, power undervoltage warning, power undervoltage reset, and external hardware reset.

4. The apparatus as described in claim 3, characterized in that, The operation of the reset function circuit is described below: (1) When the chip VCC voltage reaches 1V, the RESET port outputs a low level; the VCC voltage gradually increases, and when it exceeds the reset voltage threshold, the low level output by the RESET terminal lasts for a typical time of 25ms before being removed, the circuit reset is completed, and the watchdog starts to work.

5. The apparatus as described in claim 4, characterized in that, (2) When the VCC voltage gradually decreases and falls below the reset voltage threshold, the RESET port outputs a low level; the circuit has an external reset function, and when the MR port is low, the RESET port outputs a low level.

6. The apparatus as claimed in claim 5, characterized in that, (3) If there is no toggle signal input to WDI within the typical watchdog overflow time of 1.6s, the WDO port outputs a low level; otherwise, the WDO port outputs a high level. The control channel and the monitoring channel DSP send the inverted level to JS706T-25 through the GPIO pin at 500ms intervals to realize hardware watchdog feeding.

7. The apparatus as claimed in claim 6, characterized in that, (4) Power undervoltage warning function: When the PFI port voltage is higher than the typical value of 1.25V, the PFO port outputs a high level; otherwise, it outputs a low level. The PFO signal and the WDO signal in (3) are connected to the RESET_COM signal through an AND gate and connected to the MR of the reset chip. The low level output of either of the reset sources in (3) and (4) can enable the DSP to perform an effective reset.

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