Display panel and display terminal

Abstract

This application relates to a display panel and a display terminal. The display panel includes a substrate, an active portion, a source electrode, a drain electrode, and an isolation layer. The active portion includes a source contact portion and a drain contact portion. The source electrode and drain electrode are disposed on the side of the active portion away from the substrate. The isolation layer is disposed on the side of the active portion close to the substrate, and the isolation layer includes a first functional portion corresponding to the source electrode and a second functional portion corresponding to the drain electrode. The source electrode is connected to the source contact portion and the first functional portion through a first via, and the drain electrode is connected to the drain contact portion and the second functional portion through a second via. In the embodiments of this application, by connecting the source electrode to the source contact portion and the first functional portion through the first via, and the drain electrode to the drain contact portion and the second functional portion through the second via, the first and second functional portions can be used to isolate impurity ions, thereby preventing impurity ions from entering the active portion along the first and second vias and affecting the performance of the active portion, and improving the stability of the thin-film transistor.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display terminal. Background Technology

[0002] The display panel contains multiple thin-film transistors (TFTs). The stability of TFTs is easily affected by external factors, which can lead to a deterioration in their stability. Utility Model Content

[0003] This application provides a display panel and a display terminal to improve the technical problem of thin-film transistor stability degradation.

[0004] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising:

[0005] substrate;

[0006] An active portion is disposed on one side of the substrate, and the active portion includes a source contact portion and a drain contact portion;

[0007] The source and drain are disposed on the side of the active portion away from the substrate;

[0008] An isolation layer is disposed on the side of the active portion near the substrate, and the isolation layer includes a first functional portion corresponding to the source and a second functional portion corresponding to the drain.

[0009] The source electrode is connected to the source electrode contact portion and the first functional portion through a first via, and the drain electrode is connected to the drain electrode contact portion and the second functional portion through a second via.

[0010] Optionally, the display panel further includes a gate disposed on the side of the active portion away from the substrate, the active portion includes a channel portion located between the source contact portion and the drain contact portion, and the isolation layer further includes an isolation portion corresponding to the channel portion;

[0011] Wherein, the orthographic projection of the channel portion on the substrate is located within the orthographic projection of the isolation portion on the substrate.

[0012] Optionally, the isolation section, the first functional section, and the second functional section are arranged at intervals; or, the isolation section, the first functional section, and the second functional section are all connected.

[0013] Optionally, the display panel further includes a light-shielding layer disposed between the isolation portion and the active portion. The light-shielding layer includes a light-shielding portion, and the orthographic projection of the channel portion on the substrate is located within the orthographic projection of the light-shielding portion on the substrate.

[0014] Optionally, the light-shielding layer further includes a first terminal and a second terminal, wherein the orthographic projection of the first terminal on the substrate is located within the orthographic projection of the first functional part on the substrate, and the orthographic projection of the second terminal on the substrate is located within the orthographic projection of the second functional part on the substrate, and the first terminal, the second terminal and the light-shielding part are all spaced apart.

[0015] Optionally, the orthographic projection pattern of the light-shielding portion on the substrate is the same as the orthographic projection pattern of the isolation portion on the substrate; and / or,

[0016] The orthographic projection pattern of the first terminal on the substrate is the same as the orthographic projection pattern of the first functional part on the substrate, and the orthographic projection pattern of the second terminal on the substrate is the same as the orthographic projection pattern of the second functional part on the substrate.

[0017] Optionally, the display panel further includes:

[0018] The routing section is connected to the first parallel section disposed on the same layer as the gate through a third via, and the routing section is connected to the second parallel section disposed on the same layer as the light-shielding section through a fourth via.

[0019] Optionally, the isolation layer further includes a third functional unit, which is configured corresponding to the second parallel unit.

[0020] Optionally, the channel portion includes a first sub-portion and a second sub-portion arranged along a first direction and extending along a second direction, and a connecting portion connecting the first sub-portion and the second sub-portion, wherein the first direction intersects the second direction;

[0021] The gate extends along the first direction, and a portion of the first sub-part overlaps with the gate to form a first channel, and a portion of the second sub-part overlaps with the gate to form a second channel.

[0022] According to a second aspect of this application, a display terminal is provided, including the display panel described above.

[0023] In the display panel of this application embodiment, by connecting the source electrode to the source contact portion and the first functional portion through a first via, and connecting the drain electrode to the drain contact portion and the second functional portion through a second via, the first functional portion and the second functional portion can be used to isolate impurity ions, thereby preventing impurity ions from entering the active portion along the first via and the second via and affecting the performance of the active portion, and improving the stability of the thin film transistor.

[0024] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0027] Figure 1 This is a top view of a display panel provided in an exemplary embodiment of this disclosure;

[0028] Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure;

[0029] Figure 3 yes Figure 2 A top view schematic diagram of a thin-film transistor structure;

[0030] Figure 4 yes Figure 2 Another top view schematic diagram of the structure at the thin-film transistor in the image;

[0031] Figure 5 yes Figure 1 Another cross-sectional structural diagram;

[0032] Figure 6 yes Figure 5 A top view schematic diagram of a thin-film transistor structure;

[0033] Figure 7 yes Figure 5 Another top view schematic diagram of the structure at the thin-film transistor in the image;

[0034] Figure 8 This is a schematic diagram of the structure of a display terminal provided in an exemplary embodiment of this disclosure.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1-Display panel; AA-Display area; NA-Non-display area; 11-Pixel electrode; 12-Common electrode; 13-Gate insulating layer; 14-Planarization layer; 15-Interlayer insulating layer; 16-Buffer layer; 17-Passivation layer;

[0037] 10-Substrate;

[0038] 20 - Active part; 21 - First sub-part; 22 - Second sub-part; 23 - Connector; 201 - Channel; 21a - First channel; 22a - Second channel; 24 - Source contact; 25 - Drain contact;

[0039] 30-gate;

[0040] 40 - Isolation layer; 41 - Isolation section; 42 - First functional section; 43 - Second functional section; 44 - Third functional section;

[0041] 50 - Light-shielding layer; 51 - Light-shielding part; 52 - First terminal; 53 - Second terminal;

[0042] 61 - Source; 62 - Drain;

[0043] 71a - First via; 72a - Second via; 73a - Third via; 74a - Fourth via;

[0044] 81-Way routing section; 82-First parallel connection section; 83-Second parallel connection section;

[0045] D1 - First direction; D2 - Second direction;

[0046] 2-Display terminal; 3-Terminal body. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0048] According to a first aspect of this application, a display panel 1 is provided, such as... Figures 1 to 4 As shown, the system includes a substrate 10, an active portion 20, a source electrode 61, a drain electrode 62, and an isolation layer 40. The active portion 20 is disposed on one side of the substrate 10 and includes a source electrode contact portion 24 and a drain electrode contact portion 25. The source electrode 61 and the drain electrode 62 are disposed on the side of the active portion 20 away from the substrate 10. The isolation layer 40 is disposed on the side of the active portion 20 close to the substrate 10 and includes a first functional portion 42 corresponding to the source electrode 61 and a second functional portion 43 corresponding to the drain electrode 62. The source electrode 61 is connected to the source electrode contact portion 24 and the first functional portion 42 through a first via 71a, and the drain electrode 62 is connected to the drain electrode contact portion 25 and the second functional portion 43 through a second via 72a.

[0049] In some embodiments, the display panel 1 may be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0050] like Figure 1 As shown, the display panel 1 includes a display area AA and a non-display area NA disposed around the periphery of the display area AA. The display area AA may be provided with multiple sub-pixels (not shown in the figure), which may include red sub-pixels, green sub-pixels, and blue sub-pixels, thereby realizing color display. The display area AA may be provided with pixel driving circuits, etc., which are used to control the display of sub-pixels. The non-display area NA may be provided with gate driving circuits, etc., which are used to provide driving signals to the sub-pixels.

[0051] In some embodiments, such as Figure 2 As shown, the active portion 20 can be disposed in the display area AA or the non-display area NA. For example, the active portion 20 can be disposed in the display area AA and located in the pixel driving circuit. Alternatively, the active portion 20 can be disposed in the non-display area NA and located in the gate driving circuit.

[0052] In some embodiments, the substrate 10 may be a rigid material, such as glass.

[0053] In some embodiments, the active part 20 is a semiconductor material, such as amorphous silicon, polycrystalline silicon, metal oxide semiconductor, etc.

[0054] In some embodiments, the active part 20 is made of low-temperature polycrystalline silicon.

[0055] like Figure 2 As shown, the source electrode 61 and the drain electrode 62 are disposed on the side of the active portion 20 away from the substrate 10.

[0056] In some embodiments, the source electrode 61 and the drain electrode 62 can be arranged on the same layer, thereby simplifying the manufacturing process of the display panel 1.

[0057] In some embodiments, the source electrode 61 and the drain electrode 62 may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0058] like Figure 2 and Figure 3 As shown, the isolation layer 40 is disposed between the active portion 20 and the substrate 10. The isolation layer 40 is used to block alkali metal impurity ions such as sodium and potassium in the glass from entering the active portion 20, thereby preventing impurity ions from causing device stability degradation of the thin-film transistor.

[0059] In some embodiments, the material of the isolation layer 40 is a film such as silicon nitride. Silicon nitride is a high-density, amorphous film with a low diffusion coefficient for alkali metal impurity ions, thus significantly suppressing impurity ion migration. Simultaneously, silicon nitride is composed of strong covalent bonds, resulting in high molecular chemical stability, making it difficult for impurity ions to react with or replace its lattice positions.

[0060] In other embodiments, the material of the isolation layer 40 may also be other films that can block impurity ions.

[0061] In some embodiments, the thickness of the isolation layer 40 is 50 to 500 angstroms. Thickness refers to the dimension in the direction perpendicular to the first direction D1 and the second direction D2.

[0062] Please combine Figures 2 to 4 The source contact 24 is used for electrical connection to the source 61 of the thin-film transistor, and the drain contact 25 is used for electrical connection to the drain 62 of the thin-film transistor. It should be understood that the source contact 24 and the drain contact 25 are conductively treated to have low resistance. Conductivity treatment methods include doping with ions, etc.

[0063] like Figures 2 to 4 As shown, the source electrode 61 is connected to the source contact portion 24 and the first functional portion 42 through a first via 71a. The first via 71a penetrates the source contact portion 24 and exposes the first functional portion 42, and the source electrode 61 is connected to the first functional portion 42. With the above arrangement, impurity ions in the substrate 10 can be prevented from entering the active portion 20 along the first via 71a.

[0064] The drain 62 is connected to the drain contact portion 25 and the second functional portion 43 through the second via 72a. The second via 72a penetrates the drain contact portion 25 and exposes the second functional portion 43, and the drain 62 is connected to the second functional portion 43. With the above arrangement, impurity ions in the substrate 10 can be prevented from entering the active portion 20 along the second via 72a.

[0065] In some embodiments, such as Figure 2 As shown, a buffer layer 16 is provided between the isolation layer 40 and the active part 20. The material of the buffer layer 16 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0066] In some embodiments, the display panel 1 may be a liquid crystal panel. The liquid crystal panel includes a counter substrate (not shown) disposed opposite to and spaced apart from the substrate 10. A liquid crystal layer (not shown) is disposed between the substrate 10 and the counter substrate. The display panel 1 also includes a pixel electrode 11 and a common electrode 12. The pixel electrode 11 and the common electrode 12 may both be disposed on the substrate 10, or the pixel electrode 11 may be disposed on the substrate 10, and the common electrode 12 may be disposed on the counter substrate. Liquid crystal molecules in the liquid crystal layer are deflected in the electric field formed by the pixel electrode 11 and the common electrode 12, thereby controlling the transmittance of the display panel 1 and achieving brightness control of the image.

[0067] In some embodiments, such as Figure 5 As shown, the drain 62 can be electrically connected to the pixel electrode 11, thereby providing a driving voltage to the pixel electrode 11. The common electrode 12 can be located between the pixel electrode 11 and the substrate 10.

[0068] In some embodiments, the pixel electrode 11 and the common electrode 12 can be transparent conductive materials, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), IGO (indium gallium oxide), InO (indium oxide), etc.

[0069] In some embodiments, such as Figure 2 As shown, the display panel 1 includes a planarization layer 14 located between the source electrode 61 and the common electrode 12. The planarization layer 14 can be made of an organic material, such as an acrylic resin, an epoxy resin, or a perfluoroalkoxy resin (PFA). The planarization layer 14 has leveling properties, providing a relatively flat surface, thereby making the terrain under the common electrode 12 relatively flat.

[0070] In some embodiments, such as Figure 2 As shown, a passivation layer 17 is disposed between the common electrode 12 and the pixel electrode 11. The material of the passivation layer 17 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride stacked together.

[0071] Optionally, such as Figure 3As shown, the display panel 1 further includes a gate 30 disposed on the side of the active portion 20 away from the substrate 10. The active portion 20 includes a channel portion 201 located between the source contact portion 24 and the drain contact portion 25. The isolation layer 40 also includes an isolation portion 41 corresponding to the channel portion 201. The orthographic projection of the channel portion 201 on the substrate 10 overlaps with the orthographic projection of the gate 30 on the substrate 10, and the orthographic projection of the channel portion 201 on the substrate 10 is located within the orthographic projection of the isolation portion 41 on the substrate 10.

[0072] The gate 30 is disposed correspondingly to the channel portion 201, and the overlapping area of ​​the orthographic projection of the gate 30 on the substrate 10 and the orthographic projection of the channel portion 201 on the substrate 10 forms a channel for carrier flow.

[0073] In some embodiments, the gate 30 may be made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0074] An interlayer insulating layer 15 is disposed between the gate 30 and the source. The material of the interlayer insulating layer 15 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0075] A gate insulating layer 13 is provided between the gate 30 and the channel portion 201. The material of the gate insulating layer 13 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0076] like Figure 3 and Figure 4 As shown, the orthographic projection of the channel portion 201 on the substrate 10 lies within the orthographic projection of the isolation portion 41 on the substrate 10. This means that the isolation portion 41 is disposed directly below the channel portion 201, and the area of ​​the orthographic projection of the isolation portion 41 on the substrate 10 is greater than or equal to the area of ​​the orthographic projection of the channel portion 201 on the substrate 10. The isolation portion 41 can isolate ions directly below the channel portion 201, thereby further reducing the risk of impurity ions in the substrate 10 entering the active portion 20.

[0077] In some embodiments, such as Figure 3 and Figure 4 As shown, one isolation section 41 can be provided corresponding to one active section 20. That is to say, the number of isolation sections 41 can be the same as the number of active sections 20, and one isolation section 41 is provided directly below one active section 20.

[0078] Optionally, such as Figures 2 to 4 As shown, the isolation section 41, the first functional section 42, and the second functional section 43 are arranged at intervals; or, the isolation section 41, the first functional section 42, and the second functional section 43 are all connected.

[0079] In some embodiments, such as Figure 4 As shown, the isolation section 41, the first functional section 42, and the second functional section 43 are arranged at intervals. That is to say, the isolation section 41, the first functional section 42, and the second functional section 43 are all arranged separately, and there is no continuity between any two of them.

[0080] In some embodiments, such as Figure 3 As shown, the isolation section 41, the first functional section 42, and the second functional section 43 are all connected. This means that the isolation section 41, the first functional section 42, and the second functional section 43 can be a single unit, and any two of them can be arranged continuously.

[0081] Optionally, such as Figures 2 to 4 As shown, the display panel 1 also includes a light-shielding layer 50, which is disposed between the isolation portion 41 and the active portion 20. The light-shielding layer 50 includes a light-shielding portion 51, and the orthographic projection of the channel portion 201 on the substrate 10 is located within the orthographic projection of the light-shielding portion 51 on the substrate 10.

[0082] In some embodiments, the material of the light-shielding layer 50 can be a non-transparent material, such as a metal. For example, the light-shielding layer 50 can be a low-resistivity metal stack structure such as W / Mo, Al / Mo, Mo / Al / Mo, Ti / Al / Ti, Mo / Cu / Mo, Ti / Cu / Ti. Here, W / Mo represents a stack of tungsten and molybdenum. The slash " / " indicates that the two metal layers before and after the slash are stacked.

[0083] In some embodiments, such as Figure 2 As shown, the light-shielding layer 50 can be located in the display area AA. When the display panel 1 is a liquid crystal panel, the light from the backlight module will shine on the display area AA. The light-shielding layer 50 can shield the active part 20 of the display area AA from light, reducing the risk of the active part 20 becoming unstable due to light exposure.

[0084] In other embodiments, such as Figure 2 As shown, the light-shielding layer 50 can also be located in the non-display area NA.

[0085] Optionally, such as Figure 5 As shown, another cross-sectional structural diagram of the display panel 1 is illustrated. Figure 5 Display panel 1 and Figure 2 The difference in the display panel 1 is that the light-shielding layer 50 also includes a first terminal 52 and a second terminal 53. The orthographic projection of the first terminal 52 on the substrate 10 is located within the orthographic projection of the first functional part 42 on the substrate 10, and the orthographic projection of the second terminal 53 on the substrate 10 is located within the orthographic projection of the second functional part 43 on the substrate 10. The first terminal 52, the second terminal 53 and the light-shielding part 51 are all spaced apart.

[0086] The first terminal 52, the second terminal 53, and the light-shielding part 51 are made of the same material and are insulated from each other. The source electrode 61 is connected to the source electrode contact part 24 and the first terminal 52 through the first through hole 71a, and the drain electrode 62 is connected to the drain electrode contact part 25 and the second terminal 53 through the second through hole 72a.

[0087] like Figures 5 to 7 As shown, the first terminal 52 is disposed on the same layer as the light-shielding part 51 and spaced apart, thereby insulating the first terminal 52 from the light-shielding part 51. The second terminal 53 is disposed on the same layer as the light-shielding part 51 and spaced apart, thereby insulating the second terminal 53 from the light-shielding part 51. The first terminal 52 and the second terminal 53 are spaced apart, thereby insulating the first terminal 52 from the second terminal 53.

[0088] The source electrode 61 is connected to the source contact portion 24 and the first terminal 52 through a first via 71a. The first via 71a penetrates the source contact portion 24 and exposes the first terminal 52, and the source electrode 61 is electrically connected to the first terminal 52. With the above arrangement, the resistance of the source electrode 61 can be reduced.

[0089] In some embodiments, to prevent a short circuit between the source electrode 61 and the light-shielding portion 51, the minimum distance between the first via 71a corresponding to the source electrode 61 and the light-shielding portion 51 is greater than or equal to 1 micrometer. To prevent a short circuit between the drain electrode 62 and the light-shielding portion 51, the minimum distance between the second via 72a corresponding to the drain electrode 62 and the light-shielding portion 51 is greater than or equal to 1 micrometer.

[0090] like Figure 5 As shown, the drain 62 is connected to the drain contact 25 and the second terminal 53 through a second via 72a. The second via 72a penetrates the drain contact 25 and exposes the second terminal 53, and the drain 62 is electrically connected to the second terminal 53. This configuration reduces the resistance of the drain 62.

[0091] Optionally, such as Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown, the orthographic projection pattern of the light-shielding portion 51 on the substrate 10 is the same as the orthographic projection pattern of the isolation portion 41 on the substrate 10; and / or, the orthographic projection pattern of the first terminal 52 on the substrate 10 is the same as the orthographic projection pattern of the first functional portion 42 on the substrate 10, and the orthographic projection pattern of the second terminal 53 on the substrate 10 is the same as the orthographic projection pattern of the second functional portion 43 on the substrate 10.

[0092] It should be noted that identical orthographic projection patterns refer to identical patterns within the allowable range of process errors. For example, when the parameters in the etching process fluctuate, the isolation portion 41 may completely overlap with the light-shielding portion 51. Alternatively, the isolation portion 41 may be slightly larger than the light-shielding portion 51. Or, the isolation portion 41 may be slightly smaller than the light-shielding portion 51.

[0093] In some embodiments, such as Figure 4 and Figure 7 As shown, by adjusting the parameters in the etching process, the isolation portion 41 can be made slightly larger than the light-shielding portion 51, meaning the edge of the isolation portion 41 slightly extends beyond the edge of the light-shielding portion 51. For example, the distance between one edge of the isolation portion 41 and the edge of the light-shielding portion 51 can be greater than or equal to 0 micrometers and less than or equal to 1.5 micrometers. This setting softens the slope of the edges of the isolation portion 41 and the light-shielding portion 51, reducing the difficulty of the active portion 20 climbing the slope, thereby reducing the risk of the active portion 20 breaking at the edges of the light-shielding portion 51 and the isolation portion 41.

[0094] In some embodiments, when the parameters in the etching process fluctuate, the first terminal 52 may completely overlap with the first functional part 42. Alternatively, the first terminal 52 may be slightly larger than the first functional part 42. Alternatively, the first terminal 52 may be slightly smaller than the first functional part 42.

[0095] Similarly, when the parameters in the etching process fluctuate, the second terminal 53 may completely overlap with the second functional unit 43. Alternatively, the second terminal 53 may be slightly larger than the second functional unit 43. Or, the second terminal 53 may be slightly smaller than the second functional unit 43.

[0096] In some embodiments, such as Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown, the orthogonal projection area of ​​the light-shielding portion 51 on the substrate 10 is smaller than the orthogonal projection area of ​​the isolation portion 41 on the substrate 10. That is to say, the orthogonal projection pattern of the isolation portion 41 on the substrate 10 covers the orthogonal projection pattern of the light-shielding portion 51 on the substrate 10, and the edge of the orthogonal projection pattern of the isolation portion 41 extends beyond the edge of the orthogonal projection pattern of the light-shielding portion 51.

[0097] In some embodiments, the orthographic projection area of ​​the light-shielding portion 51 on the substrate 10 is equal to the orthographic projection area of ​​the isolation portion 41 on the substrate 10, that is, the orthographic projection pattern of the light-shielding portion 51 coincides with the orthographic projection pattern of the isolation portion 41.

[0098] In some embodiments, the orthographic projection pattern of the light-shielding portion 51 is the same as the orthographic projection pattern of the isolation portion 41. With the above arrangement, the light-shielding portion 51 and the isolation portion 41 can be patterned using the same photomask, thereby saving the manufacturing cost of the display panel 1 and simplifying the manufacturing process of the display panel 1.

[0099] Specifically, an isolation film layer is formed on the substrate 10, and a light-shielding film layer is formed on the isolation film layer. A photoresist is coated on the light-shielding film layer, and the photoresist is exposed and developed using a photomask to form an isolation pattern and a light-shielding pattern corresponding to the photoresist. Since the same photomask is used, the isolation pattern and the light-shielding pattern are identical. The remaining light-shielding film layers are etched, for example, by wet etching. The remaining isolation film layers are etched, for example, by dry etching. After etching, the light-shielding portion 51 and the isolation portion 41 are obtained.

[0100] In some embodiments, the distance between the first terminal 52 and the edge of the first functional part 42 may be greater than or equal to 0 micrometers and less than or equal to 1.5 micrometers.

[0101] In some embodiments, such as Figure 4 and Figure 7 As shown, the orthographic projection pattern of the first functional unit 42 is slightly larger than the orthographic projection pattern of the first terminal 52. This arrangement softens the slope of the edges of the first functional unit 42 and the first terminal 52, reducing the difficulty of the active unit 20 climbing the slope, thereby reducing the risk of the active unit 20 breaking at the edges of the first functional unit 42 and the first terminal 52. Similarly, the orthographic projection pattern of the second functional unit 43 is slightly larger than the orthographic projection pattern of the second terminal 53. This arrangement softens the slope of the edges of the second functional unit 43 and the second terminal 53, reducing the difficulty of the active unit 20 climbing the slope, thereby reducing the risk of the active unit 20 breaking at the edges of the second functional unit 43 and the second terminal 53.

[0102] like Figure 5 As shown, both the first functional unit 42 and the second functional unit 43 are disposed on the same layer as the isolation unit 41. The first functional unit 42 is located directly below the first terminal 52, and the second functional unit 43 is located directly below the second terminal 53.

[0103] In some embodiments, such as Figure 7 As shown, the orthographic projection pattern of the first terminal 52 on the substrate 10 is the same as the orthographic projection pattern of the first functional part 42 on the substrate 10. With the above arrangement, the first terminal 52 and the first functional part 42 can be formed using the same photomask, and the photomask forming the first terminal 52 and the photomask forming the light-shielding part 51 are the same photomask, thereby simplifying the manufacturing process of the display panel 1.

[0104] The orthographic projection pattern of the second terminal 53 on the substrate 10 is the same as the orthographic projection pattern of the second functional part 43 on the substrate 10. With the above arrangement, the second terminal 53 and the second functional part 43 can be formed using the same photomask, and the photomask forming the second terminal 53 and the photomask forming the light-shielding part 51 are the same photomask, thereby simplifying the manufacturing process of the display panel 1.

[0105] In some embodiments, the materials of the first functional portion 42 and the second functional portion 43 are the same as the material of the isolation portion 41. For example, the materials of the first functional portion 42, the second functional portion 43, and the isolation portion 41 are all silicon nitride. By providing the first functional portion 42 directly below the first terminal 52, the first functional portion 42 can isolate impurity ions, preventing impurity ions from entering the first channel 21a through the first via 71a and affecting the stability of the thin-film transistor. Similarly, by providing the second functional portion 43 directly below the second terminal 53, the second functional portion 43 can isolate impurity ions, preventing impurity ions from entering the second channel 22a through the second via 72a and affecting the stability of the thin-film transistor.

[0106] Optionally, such as Figure 2 and Figure 5 As shown, the display panel 1 includes a wiring section 81, which is connected to a first parallel section 82 disposed on the same layer as the gate 30 through a third via 73a, and the wiring section 81 is connected to a second parallel section 83 disposed on the same layer as the light-shielding section 51 through a fourth via 74a.

[0107] In some embodiments, the trace portion 81 may be located in the non-display area NA, and the trace portion 81 may be used to transmit signals. By connecting the trace portion 81, the first parallel portion 82, and the second parallel portion 83, the impedance of the trace portion 81 can be reduced.

[0108] The first parallel section 82 is disposed on the same layer as the gate 30. The first parallel section 82 can be formed using the same patterning process as the gate 30, thereby simplifying the manufacturing process of the display panel 1.

[0109] The second parallel section 83 is disposed on the same layer as the light-shielding section 51. The second parallel section 83 can be formed using the same patterning process as the light-shielding section 51, thereby simplifying the manufacturing process of the display panel 1.

[0110] In some embodiments, such as Figure 2 and Figure 5 As shown, the trace portion 81 can be disposed on the same layer as the source electrode 61. Since the fourth via 74a connects the trace portion 81 and the second parallel portion 83, and the first via 71a connects the source electrode 61 and the first terminal 52, the trace portion 81 is disposed on the same layer as the source electrode 61, and the second parallel portion 83 is disposed on the same layer as the first terminal 52. Therefore, the fourth via 74a and the first via 71a can also be formed using the same patterning process.

[0111] In some embodiments, such as Figure 2 and Figure 5As shown, the source electrode 61 and the drain electrode 62 are disposed on the same layer. Since the second via 72a connects the drain electrode 62 and the second terminal 53, and the first via 71a connects the source electrode 61 and the first terminal 52, the fourth via 74a, the first via 71a, and the second via 72a can all be formed using the same patterning process. This arrangement not only reduces the impedance of the trace section 81 but also does not increase the number of photomasks used.

[0112] Optionally, such as Figure 5 As shown, the isolation layer 40 also includes a third functional section 44, which is provided corresponding to the second parallel section 83. The material of the third functional section 44 is the same as that of the first functional section 42. The third functional section 44 can prevent impurity ions from entering the upper film layer along the fourth via 74a, thereby reducing the risk of impurity ions entering the active section 20 in the upper film layer.

[0113] The third functional part 44 is located directly below the second parallel part 83, and the area of ​​the orthographic projection pattern of the third functional part 44 on the substrate 10 is greater than or equal to the area of ​​the orthographic projection pattern of the second parallel part 83 on the substrate 10.

[0114] Optionally, such as Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown, the active portion 20 includes a first sub-portion 21 and a second sub-portion 22 arranged along a first direction D1 and extending along a second direction D2, and a connecting portion 23 connecting the first sub-portion 21 and the second sub-portion 22. The first direction D1 intersects the second direction D2. The gate 30 extends along the first direction D1. A portion of the first sub-portion 21 overlaps with the gate 30 to form a first channel 21a, and a portion of the second sub-portion 22 overlaps with the gate 30 to form a second channel 22a.

[0115] like Figure 3 As shown, both the first sub-part 21 and the second sub-part 22 extend along the second direction D2, and the first sub-part 21 and the second sub-part 22 are arranged along the first direction D1. A connecting part 23 is located between the first sub-part 21 and the second sub-part 22, with one end of the connecting part 23 connected to the first sub-part 21 and the other end connected to the second sub-part 22. With this arrangement, the active part 20 can be formed into a U-shaped configuration.

[0116] The gate 30 extends along the first direction D1. A portion of the first sub-section 21 overlaps with the gate 30 to form a first channel 21a, and a second sub-section 22 overlaps with another portion of the gate 30 to form a second channel 22a. The first channel 21a and the second channel 22a are separately disposed. Since the gate 30 corresponds to two channel portions 201, the portion corresponding to the first channel 21a and the portion corresponding to the second channel 22a form a dual gate, and the dual-gate thin-film transistor has higher device stability.

[0117] In the active section 20, the current flows from the first subsection 21 through the connecting section 23, and then through the second subsection 22.

[0118] In the first sub-section 21, lightly doped regions can be provided on both sides of the first channel 21a, which can reduce the leakage current of the thin-film transistor. In the second sub-section 22, lightly doped regions can be provided on both sides of the second channel 22a, which can also reduce the leakage current of the thin-film transistor. The region other than the first channel 21a, the second channel 22a, and the lightly doped regions can be heavily doped regions. The average concentration of carriers in the heavily doped regions is greater than the average concentration of carriers in the lightly doped regions, and the impedance of the heavily doped regions is less than that of the lightly doped regions. The heavily doped region located at the end of the first sub-section 21 away from the connection portion 23 can be used for electrical connection with the source 61 of the thin-film transistor, and the heavily doped region located at the end of the second sub-section 22 away from the connection portion 23 can be used for electrical connection with the drain 62 of the thin-film transistor. Since the impedance of the heavily doped regions is smaller, the contact resistance between the source 61, the drain 62, and the heavily doped regions can be reduced.

[0119] The orthographic projections of the first channel 21a and the second channel 22a on the substrate 10 lie within the orthographic projection of the isolation portion 41 on the substrate 10. This means that the orthographic projection of the isolation portion 41 on the substrate 10 at least covers the orthographic projections of the first channel 21a and the second channel 22a on the substrate 10. The isolation portion 41 is used to block alkali metal impurity ions such as sodium and potassium from entering the first channel 21a and the second channel 22a, thereby preventing impurity ions from causing a deterioration in the device stability of the thin-film transistor.

[0120] In some embodiments, such as Figure 4 and Figure 7 As shown, the isolation portion 41 does not overlap with the connecting portion 23, and the end of the first sub-part 21 away from the connecting portion 23 and the end of the second sub-part 22 away from the connecting portion 23 do not overlap with the isolation portion 41.

[0121] According to the second aspect of this application, such as Figure 8 As shown, a display terminal 2 is provided, including the display panel 1 described above.

[0122] In this embodiment, as Figure 8 As shown, the display terminal 2 includes a display panel 1 and a terminal body 3, which are combined into one unit.

[0123] In this embodiment, the display terminal 2 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0124] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0125] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0126] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0127] The above description is merely a preferred embodiment of this application and does not constitute any limitation on this application. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: substrate; An active portion is disposed on one side of the substrate, and the active portion includes a source contact portion and a drain contact portion; The source and drain are disposed on the side of the active portion away from the substrate; An isolation layer is disposed on the side of the active portion near the substrate, and the isolation layer includes a first functional portion corresponding to the source and a second functional portion corresponding to the drain. The source electrode is connected to the source electrode contact portion and the first functional portion through a first via, and the drain electrode is connected to the drain electrode contact portion and the second functional portion through a second via.

2. The display panel according to claim 1, characterized in that, The display panel further includes a gate disposed on the side of the active portion away from the substrate, the active portion includes a channel portion located between the source contact portion and the drain contact portion, and the isolation layer further includes an isolation portion corresponding to the channel portion; Wherein, the orthographic projection of the channel portion on the substrate overlaps with the orthographic projection of the gate on the substrate, and the orthographic projection of the channel portion on the substrate is located within the orthographic projection of the isolation portion on the substrate.

3. The display panel according to claim 2, characterized in that, The isolation section, the first functional section, and the second functional section are arranged at intervals; or, the isolation section, the first functional section, and the second functional section are all connected.

4. The display panel according to claim 2 or 3, characterized in that, The display panel further includes a light-shielding layer disposed between the isolation portion and the active portion. The light-shielding layer includes a light-shielding portion, and the orthographic projection of the channel portion on the substrate is located within the orthographic projection of the light-shielding portion on the substrate.

5. The display panel according to claim 4, characterized in that, The light-shielding layer further includes a first terminal and a second terminal. The orthographic projection of the first terminal on the substrate is located within the orthographic projection of the first functional part on the substrate. The orthographic projection of the second terminal on the substrate is located within the orthographic projection of the second functional part on the substrate. The first terminal, the second terminal, and the light-shielding part are all spaced apart.

6. The display panel according to claim 5, characterized in that, The orthographic projection pattern of the light-shielding part on the substrate is the same as the orthographic projection pattern of the isolation part on the substrate; And / or, The orthographic projection pattern of the first terminal on the substrate is the same as the orthographic projection pattern of the first functional part on the substrate, and the orthographic projection pattern of the second terminal on the substrate is the same as the orthographic projection pattern of the second functional part on the substrate.

7. The display panel according to claim 4, characterized in that, The display panel also includes: The routing section is connected to the first parallel section disposed on the same layer as the gate through a third via, and the routing section is connected to the second parallel section disposed on the same layer as the light-shielding section through a fourth via.

8. The display panel according to claim 7, characterized in that, The isolation layer also includes a third functional unit, which is configured corresponding to the second parallel unit.

9. The display panel according to claim 7, characterized in that, The channel portion includes a first sub-portion and a second sub-portion arranged along a first direction and extending along a second direction, and a connecting portion connecting the first sub-portion and the second sub-portion, wherein the first direction intersects the second direction; The gate extends along the first direction, and a portion of the first sub-part overlaps with the gate to form a first channel, and a portion of the second sub-part overlaps with the gate to form a second channel.

10. A display terminal, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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