Semiconductor device and integrated circuit device

Abstract

A semiconductor device and an integrated circuit device. The integrated circuit device includes an active region; a first wire extending in a first direction and corresponding to a first transistor, and a second wire corresponding to a second transistor, the first transistor and the second transistor connected in series and divided into two or more nets; a first gate structure connected to the first wire and corresponding to the first transistor; a second gate structure connected to the second wire and corresponding to the second transistor, the second gate structure equal in number to the first gate structure; and a first contact structure between a first of the first gate structures and a first of the second gate structures, and a second contact structure between a second of the first gate structures and a second of the second gate structures, the number of the contact structures equal to the number of the nets.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and an integrated circuit device, and more particularly to a metal oxide semiconductor device and an integrated circuit device. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of devices to solve problems in many different fields. The structure of the device components and the routing of signal and power lines affect signal integrity and power consumption. As ICs become smaller and more complex, the resistance of the wires within these devices also changes, thus affecting the operating voltage of these devices and the overall IC performance. Utility Model Content

[0003] In some embodiments, an integrated circuit device is provided, comprising: an active region; a first wire extending along a first direction and corresponding to a first transistor, and a second wire extending along the first direction and corresponding to a second transistor, the first transistor and the second transistor being connected in series and divided into two or more meshes; a plurality of first gate structures connected to the first wire and corresponding to the first transistor, the first gate structures being spaced apart in a first direction and extending in a second direction; a plurality of second gate structures connected to the second wire and corresponding to the second transistor, the number of the second gate structures being equal to the number of the first gate structures; and a first contact structure between a first of the first gate structures and a first of the second gate structures, and a second contact structure between a second of the first gate structures and a second of the second gate structures, the number of contact structures being equal to the number of meshes.

[0004] In some embodiments, an integrated circuit device is provided. The integrated circuit device includes an active region, a plurality of first gate structures corresponding to a first transistor, a plurality of second gate structures corresponding to a second transistor, a first contact structure, a second contact structure, a first wire extending in a first direction and connected to the first gate structures and corresponding to the first transistor; and a second wire extending in the first direction and connected to the second gate structures and corresponding to the second transistor. The first gate structures are spaced apart in the first direction and extend in a second direction. The second gate structures are formed in a number equal to the number of first gate structures. A first contact structure is formed between a first of the first gate structures and a first of the second gate structures. A second contact structure is formed between a second of the first gate structures and a second of the second gate structures. The first transistor and the second transistor are formed in series and divided into two or more grids. The plurality of contact structures including the first and second contact structures are formed in a number equal to the number of grids.

[0005] In some embodiments, a semiconductor device is provided, comprising: an active region; a plurality of gate structures intersecting the active region, the gate structures including: a plurality of first gate structures corresponding to a first transistor, the first gate structures being spaced apart in a first direction and extending in a second direction, and a plurality of second gate structures corresponding to a second transistor, the number of the second gate structures being equal to the number of the first gate structures, the first transistor and the second transistor being connected in series and divided into two or more grids; a plurality of contact structures intersecting the active region, the contact structures including: a first contact structure between a first of the first gate structures and a first of the second gate structures, and a second contact structure between a second of the first gate structures and a second of the second gate structures, the number of the contact structures being equal to the number of grids; a first wire extending in the first direction and connected to the first gate structures and corresponding to the first transistor; and a second wire extending in the first direction and connected to the second gate structures and corresponding to the second transistor. Attached Figure Description

[0006] The present disclosure of the embodiments is similar to the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 It is a layout diagram of a multi-transistor circuit with a series configuration and separate interconnections according to some embodiments;

[0008] Figures 2A to 2D This is a schematic diagram of a multi-transistor circuit with a series configuration and separate interconnections according to some embodiments;

[0009] Figure 3 It is a layout diagram of a multi-transistor circuit with a series configuration and separate interconnections according to some embodiments;

[0010] Figure 4 It is a layout diagram of a multi-transistor circuit with a series configuration and separate interconnections according to some embodiments;

[0011] Figure 5 It is a layout diagram of a multi-transistor circuit with a series configuration and separate interconnections according to some embodiments;

[0012] Figure 6 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments;

[0013] Figure 7A This is a flowchart of a method for generating a layout diagram according to some embodiments;

[0014] Figure 7B This is a method for manufacturing a semiconductor device based on a layout drawing, according to some embodiments;

[0015] Figure 8 This is a block diagram of an electronic design automation (EDA) system according to some embodiments;

[0016] Figure 9 This is a block diagram of a semiconductor device manufacturing system and its associated IC manufacturing process according to some embodiments.

[0017] [Symbol Explanation]

[0018] 100: Layout

[0019] 104: First conductor

[0020] 105: Multi-transistor circuit

[0021] 106: Second conductor

[0022] 107: Unit

[0023] 114: Active Zone

[0024] 116: Gate Structure

[0025] 116_oa~116_ob: Outermost gate structure

[0026] 120: Contact Structure

[0027] 122: Through hole

[0028] 205-235: Multi-transistor circuits

[0029] 300: Layout

[0030] 304: First conductor

[0031] 305: Multi-transistor circuit

[0032] 306: Second conductor

[0033] 307: Unit

[0034] 314: Active Zone

[0035] 316: Gate structure

[0036] 320:MD contact structure

[0037] 322: Through hole

[0038] 400: Layout

[0039] 404: First conductor

[0040] 405: Multi-transistor circuit

[0041] 406: Second conductor

[0042] 407: Unit

[0043] 414: Active Zone

[0044] 416: Gate structure

[0045] 420:MD contact structure

[0046] 422: Through hole

[0047] 500: Layout

[0048] 504: First conductor

[0049] 505: Multi-transistor circuit

[0050] 506: Second conductor

[0051] 507: Unit

[0052] 514: Active Zone

[0053] 516: Gate Structure

[0054] 520:MD contact structure

[0055] 522: Through hole

[0056] 600: Method

[0057] 602~604: Square

[0058] 700: Method

[0059] 702~708: Square

[0060] 750: Method

[0061] 752~758: Square

[0062] 800: EDA System

[0063] 802: Hardware Processor

[0064] 804: Computer-readable storage media

[0065] 806: Computer Program Code

[0066] 807: Standard Cell Library

[0067] 808: Bus

[0068] 810: I / O Interface

[0069] 812: Network Interface

[0070] 814: Network

[0071] 842:UI

[0072] 900: IC Manufacturing System

[0073] 920: Design Studio

[0074] 922: IC Design Layout

[0075] 930: Covered Room

[0076] 932: Masking Data Preparation

[0077] 944: Mask Manufacturing

[0078] 945: Mask

[0079] 950: IC wafer fab

[0080] 952: Manufacturing Tools

[0081] 953: Semiconductor wafer

[0082] 960: IC device Detailed Implementation

[0083] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific instances of components, materials, values, steps, configurations, or the like are described below to simplify the embodiments of this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, configurations, or the like are also contemplated. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0084] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0085] Circuit design and layout co-optimization improves circuit performance. In unoptimized circuits or layouts, parasitic resistance and capacitance degrade circuit performance in terms of speed and power consumption, for example, in circuits and layouts where the interconnect of two series-connected MOS transistors passes through too many vias and metal routes. According to some embodiments, circuit design and layout co-optimization reduces the parasitic resistance and capacitance of each net in the circuit to improve circuit performance relative to devices with additional vias and / or metal routes. In some embodiments, circuit design and layout co-optimization improves circuit performance in terms of speed by reducing RC delay and reduces active power by reducing parasitic capacitance. In some embodiments, a fully interleaved layout helps reduce the equivalent resistance of each path in a circuit including two series-connected MOS transistors. In some embodiments, the first and second of the two series-connected MOS transistors are interleaved in the same group, the interconnect of the two MOS transistors is separated, and excessive vias and metal routes are avoided.

[0086] Figure 1 This is a schematic diagram of a layout 100 of a multi-transistor circuit 105 having a series configuration and separate interconnections according to some embodiments.

[0087] exist Figure 1 In the circuit 105, a first transistor MOS_A and a second transistor MOS_B are connected in series. The first transistor MOS_A and the second transistor MOS_B are metal oxide semiconductor (MOS) transistors, such as field effect transistors (FETs), finned FETs (finFETs), or similar.

[0088] Layout 100 represents various configurations of a cell 107. In layout 100, a first conductor 104 and a second conductor 106 extend parallel to a first direction (X direction) in a first metal layer (MO) over a substrate (e.g., a semiconductor substrate). The first conductor 104 and the second conductor 106 are spaced apart in a second direction (Y direction). A first transistor MOS_A and a second transistor MOS_B correspond to an active region 114. The active region 114 is an oxide-defined (OD) region extending parallel to the first direction (X direction) on the substrate. Each of the first transistor MOS_A and the second transistor MOS_B has a number of conductive gate structures 116 (e.g., polysilicon or the like) extending parallel to the second direction (Y direction) and corresponding in number to the pointers of the first transistor MOS_A and the second transistor MOS_B. A gate insulating film (e.g., a silicon oxide film) is interposed between the gate structures 116 and the active region 114. The gate structure 116 of the first transistor MOS_A (corresponding to the "A" in the first transistor MOS_A) is connected to the first conductor 104 through a via 122. The gate structure 116 of the second transistor MOS_B (corresponding to the "B" in the second transistor MOS) is connected to the second conductor 106 through a via 122.

[0089] In layout 100, the first transistor MOS_A has the same conductivity type (e.g., PMOS or NMOS) as the second transistor MOS_B (e.g., NMOS or PMOS). A first active region and a second active region having the same conductivity type are provided, each extending parallel to a first direction (X direction) and spaced apart in a second direction (Y direction), and underlying corresponding ones of the first conductor 104 and the second conductor 106. Accordingly, the conductivity type of the first transistor MOS_A is the same as that of the second transistor MOS_B. For example, in an embodiment, the first active region is N-type, the second active region is N-type, and the first transistor MOS_A is NMOS, and the second transistor MOS_B is NMOS. For example, in an embodiment, the first active region is P-type, the second active region is P-type, and the first transistor MOS_A is PMOS, and the second transistor MOS_B is PMOS.

[0090] In layout 100, a metal-to-diffusion (MD) contact structure 120 (in the MD layer on the active region) extends parallel to the second direction (Y direction) and is disposed between the "A" and "B" fingers of the first transistor MOS_A and the second transistor MOS_B. The contact structure 120 is interlocked with each other along the active region 114 between the gate structures 116 of the opposite transistors MOS_A and MOS_B. The contact structure 120 overlaps with the active region 114.

[0091] In circuit 105, the first transistor MOS_A includes six fingers (MOS_A<5:0>), and the second transistor MOS_B includes six fingers (MOS_B<5:0>). The interconnection between MOS_A and MOS_B is divided into six distinct nodes (corresponding to the six contact structures 120 in layout 100). Therefore, circuit 105 includes six nets (net_a<5:0>). The number of contact structures 120 is equal to the number of nets in circuit 105. In some embodiments, the number of fingers in each of the first transistor MOS_A and the second transistor MOS_B is greater than six or less than six, and correspondingly, the number of nets is greater than six or less than six. Thus, for example, in an embodiment, the number of fingers in each of the first transistor MOS_A and the second transistor MOS_B is two, and the number of nets is two.

[0092] exist Figure 1 In layout 100, the gate structure 116 (i.e., the pointer) of the first transistor MOS_A and the pointer of the second transistor MOS_B are completely interleaved in the pattern "ABBA" repeated in layout 100 (where "A" is the pointer of the first transistor MOS_A and "B" is the pointer of the second transistor MOS_B). In layout 100, the pattern "ABBA" is repeated twice, such that the six pointers of the first transistor MOS_A (MOS_A<5:0>) and the six pointers of the second transistor MOS_B (MOS_B<5:0>) are arranged in the overall pattern "ABBAABBAABBA". Therefore, in the cell represented by layout 100, gate structures 116_oa and 116_ob are the outermost of the twelve gate structures 116 of the first transistor MOS_A and the second transistor MOS_B. In addition, the outermost gate structures 116_oa and 116_ob both correspond to the same transistor. For example, in Figure 1 In this embodiment, both the outermost gate structures 116_oa and 116_ob correspond to the first transistor MOS_A (i.e., correspond to "A"). In another embodiment, both the outermost gate structures 116_oa and 116_ob correspond to the second transistor MOS_B (or another transistor when more than two transistors are connected in series in circuit 105).

[0093] Because the series-connected first transistor MOS_A and second transistor MOS_B are configured with a completely interleaved "ABBAABBAABBA", the connection structure of circuit 105 is simplified in layout 100 compared to configurations of "AAAAAABBBBBB" or "AABBAABBAABB". This would require additional metal routing (e.g., in the first metal layer M0) and vias (e.g., vias in the via layer VD below the first metal layer M0 and above the MD layer) to connect the outermost fingers (one "A" finger and one "B" finger). In some embodiments, one or more of the contact structures 120 are not electrically connected to the overlying metal layer (such as the first metal layer M0) (e.g., no direct connection or vias in the via layer VD directly above the MD layer).

[0094] As mentioned above, in Figure 1 In layout 100, the interconnect between the first transistor MOS_A and the second transistor MOS_B is formed in the MD layer (i.e., using the contact structure 120 in the MD layer), thereby minimizing vias and metal routing in the first metal layer M0. This contrasts with layouts where some or all of the two series-connected transistors are connected via metal layers (such as the first metal layer M0). Figure 1 A fully interleaved layout 100 reduces the total equivalent resistance of the connection paths. Therefore, compared to a layout that forms a larger number of connections in, for example, layer M0, Figure 1 The fully interleaved layout 100 reduces parasitic resistance and capacitance (RC) from vias and metal routes, improving circuit performance (speed) by reducing RC delay and improving power consumption (i.e., reducing active power) by reducing parasitic capacitance.

[0095] Similarly, the nodes in net_a of circuit 105 are all different nodes. In layout 100, the MD layer is used to connect the first transistor MOS_A and the second transistor MOS_B. Accordingly, each contact structure 120 is included in a different node. Conversely, if the pointers of the first transistor MOS_A and the second transistor MOS_B are configured as "AAAABBBB" or "ABABABABABAB" (instead of "ABBAABBAABBA" in layout 100), the net cannot be separated.

[0096] Figure 1The fully interleaved layout 100 includes pointers to a first transistor MOS_A and a second transistor MOS_B configured in pattern ABBA. Layout 100 can be extended to cases where the first transistor MOS_A, the second transistor MOS_B, and the third transistor MOS_C are connected in series in pattern ABCCBA, or where the first transistor MOS_A, the second transistor MOS_B, the third transistor MOS_C, and the fourth transistor MOS_D are connected in series in pattern ABCDCBA. Layout 100 can be applied to all process nodes.

[0097] Figure 2A This is a schematic diagram of a multi-transistor circuit 205, which has two PMOS transistors arranged in series (with separate interconnects). Figure 2A In this configuration, the first transistor MOS_A is a PMOS transistor, and the second transistor MOS_B is a PMOS crystal. In some embodiments, using... Figure 1 The layout will be implemented in 100. Figure 2A Circuit 205.

[0098] Figure 2B This is a schematic diagram of a multi-transistor circuit 215, which has PMOS transistors and NMOS transistors arranged in series (with separate interconnections). Figure 2B In this configuration, the first transistor MOS_A is a PMOS transistor, and the second transistor MOS_B is an NMOS transistor. In some embodiments, the pair is used... Figure 1 To implement the layout modification of 100 Figure 2B The circuit 215 provides first and second active regions, each active region extending parallel to a first direction (X direction) and having a different conductivity type.

[0099] Figure 2C This is a schematic diagram of a multi-transistor circuit 225, which has NMOS transistors and PMOS transistors arranged in series (with separate interconnects). Figure 2C In this configuration, the first transistor MOS_A is an NMOS transistor, and the second transistor MOS_B is a PMOS transistor. In some embodiments, using... Figure 1 The layout will be implemented in 100. Figure 2C Circuit 225.

[0100] Figure 2D This is a schematic diagram of a multi-transistor circuit 235, which has two NMOS transistors arranged in series (with separate interconnects). Figure 2D In this configuration, the first transistor MOS_A is an NMOS transistor, and the second transistor MOS_B is an NMOS crystal. In some embodiments, the pair... Figure 1To implement the layout modification of 100 Figure 2D The circuit 235 provides first and second active regions, each active region extending parallel to a first direction (X direction) and having a different conductivity type.

[0101] As mentioned above, Figure 1 The layout 100 can be implemented for all combinations of PMOS and NMOS transistors serving as the first transistor MOS_A and the second transistor MOS_B, that is, the first combination of PMOS transistor + PMOS transistor serving as the first transistor MOS_A and the second transistor MOS_B. Figure 2A ), as a second combination of the first transistor MOS_A and the second crystal MOS_B, a PMOS transistor + NMOS transistor (using the first and second active regions). Figure 2B ), as the third combination of NMOS transistor + PMOS transistor (using the first and second active regions) of the first transistor MOS_A and the second transistor MOS_B ( Figure 2C ), or as a fourth combination of NMOS transistor + NMOS transistor, consisting of the first transistor MOS_A and the second transistor MOS_B ( Figure 2D ).

[0102] Figure 3 This is a schematic diagram of a layout 300 of a multi-transistor circuit 305 having a series configuration and separate interconnections according to some embodiments.

[0103] exist Figure 3 In the circuit 305, two nets (net_a<1:0>) are used for series connection of two transistors MOS_A and MOS_B, and the interconnection between the first transistor MOS_A and the second transistor MOS_B is separate. The first transistor MOS_A has two fingers (MOS_A<1:0>), and the second transistor MOS_B has two fingers (MOS_B<1:0>).

[0104] Layout 300 represents various states of a cell 307. In layout 300, a first conductor 304 and a second conductor 306 extend parallel to a first direction (X direction) in a first metal layer MOS. The first conductor 304 and the second conductor 306 are spaced apart in a second direction (Y direction). A first transistor MOS_A and a second transistor MOS_B correspond to an active region 314. The active region 314 extends parallel to the first direction (X direction). The gate structure 316 of the first transistor MOS_A (corresponding to the "A" in the first transistor MOS_A) is connected to the first conductor 304 through a via 322 in the via layer VD. The gate structure 316 of the second transistor MOS_B (corresponding to the "B" in the second transistor MOS_B) is connected to the second conductor 306 through a via 322 in the via layer VD.

[0105] The first transistor MOS_A and the second transistor MOS_B are connected by an MD contact structure 320 in the MD layer. The contact structure 320 extends parallel to the second direction (Y direction) and overlaps with the active region 314.

[0106] exist Figure 3 In the diagram, the pointers of the first transistor MOS_A and the second transistor MOS_B are completely interleaved, as shown below. Figure 1 As shown. That is, the pointers of the first transistor MOS_A and the second transistor MOS_B are arranged in a fully interleaved "ABBA" pattern in layout 300 (where "A" is the pointer of the first transistor MOS_A and "B" is the pointer of the second transistor MOS_B).

[0107] Figure 4 This is a schematic diagram of a layout 400 of a multi-transistor circuit 405 having a series configuration and separate interconnections according to some embodiments.

[0108] exist Figure 4 In the circuit 405, three nets (net_a<2:0>) are used for connecting two transistors MOS_A and MOS_B in series, and the interconnection between the first transistor MOS_A and the second transistor MOS_B is separate. The first transistor MOS_A has three fingers (MOS_A<2:0>), and the second transistor MOS_B has three fingers (MOS_B<2:0>).

[0109] Layout 400 represents various states of a cell 407. In layout 400, a first conductor 404 and a second conductor 406 extend parallel to a first direction (X direction) in a first metal layer MOS. The first conductor 404 and the second conductor 406 are spaced apart in a second direction (Y direction). A first transistor MOS_A and a second transistor MOS_B correspond to an active region 414. The active region 414 extends parallel to the first direction (X direction). The gate structure 416 of the first transistor MOS_A (corresponding to the "A" in the first transistor MOS_A) is connected to the first conductor 404 through a via 422 in the via layer VD. The gate structure 416 of the second transistor MOS_B (corresponding to the "B" in the second transistor MOS) is connected to the second conductor 406 through a via 422 in the via layer VD.

[0110] The first transistor MOS_A and the second transistor MOS_B are connected by an MD contact structure 420 in the MD layer. The contact structure 420 extends parallel to the second direction (Y direction) and overlaps with the active region 414.

[0111] exist Figure 4In this configuration, the pointers of the first transistor MOS_A and the second transistor MOS_B are completely interleaved. That is, the pointers of the first transistor MOS_A and the second transistor MOS_B are arranged in a partially repeating "ABBA" layout, thus forming the overall pattern "ABBAAB" in layout 400 (where "A" is the pointer of the first transistor MOS_A and "B" is the pointer of the second transistor MOS_B). This structure avoids similar combinations... Figure 1 The described method necessitates additional through-hole connections.

[0112] Figure 5 This is a schematic diagram of a layout 500 of a multi-transistor circuit 505 having a series configuration and separate interconnections according to some embodiments.

[0113] exist Figure 5 In the circuit 505, four nets (net_a<3:0>) are used for connecting two transistors MOS_A and MOS_B in series, and the interconnection between the first transistor MOS_A and the second transistor MOS_B is separate. The first transistor MOS_A has four fingers (MOS_A<3:0>), and the second transistor MOS_B has four fingers (MOS_B<3:0>).

[0114] Layout 500 represents various configurations of a cell 507. In layout 500, a first conductor 504 and a second conductor 506 extend parallel to a first direction (X direction) in a first metal layer M0. The first conductor 504 and the second conductor 506 are spaced apart in a second direction (Y direction). An active region 514 extends parallel to the first direction (X direction). The gate structure 516 of the first transistor MOS_A (corresponding to the pointer "A" of the first transistor MOS_A) is connected to the first conductor 504 through a via 522 in the via layer VD. The gate structure 516 of the second transistor MOS_B (corresponding to the pointer "B" of the second transistor MOS) is connected to the second conductor 506 through a via 522 in the via layer VD.

[0115] The first transistor MOS_A and the second transistor MOS_B are connected by an MD contact structure 520 in the MD layer. The contact structure 520 extends parallel to the second direction (Y direction) and overlaps with the active region 514.

[0116] exist Figure 5 In this configuration, the pointers of the first transistor MOS_A and the second transistor MOS_B are completely interleaved. That is, the pointers of the first transistor MOS_A and the second transistor MOS_B are arranged in a completely interleaved pattern "ABBA", which is repeated in layout 500 to form the overall pattern "ABBAABBA" (where "A" is the pointer of the first transistor MOS_A and "B" is the pointer of the second transistor MOS_B).

[0117] Figure 6 This is a flowchart of a method 600 for generating a layout according to some embodiments.

[0118] According to some embodiments, method 600 is implementable, for example, by using the following combination Figure 8 The described electronic design automation (EDA) system is 800 and below. Figure 9 The integrated circuit (IC) manufacturing system 900 is discussed. Examples of layouts for method 600 include layouts 100, 300, 400, and 500 disclosed herein.

[0119] exist Figure 6 In this method 600, blocks 602 and 604 are included. At block 602, a layout is generated. According to some embodiments, the layout is one of layouts 100, 300, 400, and 500 disclosed herein. Reference will be made below. Figure 7A Let's discuss block 602 in more detail. The flow proceeds from block 602 to block 604.

[0120] At block 604, based on the layout, at least one of the following is performed: (A) performing one or more optical lithography exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating one or more components in a layer of a semiconductor device. See below. Figure 7B The discussion.

[0121] Figure 7A This is a flowchart of a method 700 for generating a layout according to some embodiments.

[0122] More specifically, according to one or more embodiments, Figure 7A The flowchart shows additional blocks, which can be displayed in... Figure 6 An example of the operation implemented in block 602.

[0123] exist Figure 7A In the game, block 602 includes blocks 702, 704, 706, and 708.

[0124] At block 702, a first layer of substrate is created in the layout to include at least one active region. In some embodiments, the at least one active region corresponds to a representation Figure 1 Active area 114 in Figure 3 Active area 314 in Figure 4 Active region 414, or Figure 5 The active area 514 is the area in the layout.

[0125] At block 704, a gate layer is formed over a first layer of the substrate to include a plurality of gate structure patterns spaced apart in a first direction, extending parallel to a second direction, and intersecting at least one active region. The plurality of gate structure patterns correspond to at least two transistors, each transistor comprising first and second transistors connected in series and divided into a number of n grids, where n is an integer greater than 1. The plurality of gate structure patterns includes a number of first gate structure patterns equal to a multiple of n (where m is an integer greater than 1), and a number of second gate structure patterns equal to the number of first gate structure patterns. In some embodiments, the gate structure patterns correspond to... Figure 1 Gate structure 116 in Figure 3 Gate structure 316 in Figure 4 Gate structure 416, or Figure 5 The region in the layout of the gate structure 516.

[0126] At block 706, an MD layer is formed above the first layer of the substrate to include a plurality of contact structure patterns extending parallel to the second direction and intersecting at least one active region. The plurality of contact structure patterns includes a number of contact structure patterns equal to the number n of meshes. A first contact structure pattern in the plurality of contact structure patterns is located between a first one of a first gate structure pattern and a first one of a second gate structure pattern, and a second contact structure pattern in the plurality of contact structure patterns is located between a second one of a second gate structure pattern and a second one of a second gate structure pattern. In some embodiments, the contact structure patterns correspond to representations of... Figure 1 Contact structure 120 in Figure 3 Contact structure 320 in Figure 4 Contact structure 420, or Figure 5 The contact structure 520 is arranged in the area.

[0127] At block 708, a metal layer is formed above the MD layer to include a plurality of wire patterns, including a first wire pattern corresponding to a first transistor and a second wire pattern corresponding to a second transistor, a first and a second contact structure pattern, and a second gate structure pattern, one of which is between the first and the second of the first gate structure pattern. The first gate structure pattern corresponds to the first transistor and overlaps with the first wire pattern to be connected to the first wire pattern, and the second gate structure pattern corresponds to the second transistor and overlaps with the second wire pattern to be connected to the second wire pattern. In some embodiments, the wire patterns correspond to representations of... Figure 1 Wires 104 and 106 in the middle, Figure 3 The wires 304 and 306 in the middle, Figure 4 The wires in the 404, 406, or Figure 5 The layout of conductors 504 and 506 in the circuit.

[0128] Figure 7B This is a flowchart of a method 750 for manufacturing one or more components of a semiconductor device based on layout, according to some embodiments.

[0129] More specifically, according to one or more embodiments, Figure 7B The flowchart shows additional squares, demonstrating what can be seen. Figure 6 An example of the operation implemented in block 604.

[0130] exist Figure 7B In the game, block 604 includes blocks 752, 754, 756, and 758.

[0131] At block 752, the method includes forming at least one active region. In some embodiments, the at least one active region corresponds to Figure 1 Active area 114 in Figure 3 Active area 314 in Figure 4 Active region 414, or Figure 5 Active region 514.

[0132] At block 754, the method includes forming a plurality of gate structures spaced apart in a first direction, extending parallel to a second direction, and intersecting at least one active region. The plurality of gate structures correspond to at least two transistors, each transistor comprising first and second transistors connected in series and divided into a number of n grids, where n is an integer greater than 1. The plurality of gate structures includes a number of first gate structures equal to a multiple of n (where m is an integer greater than 1); and a number of second gate structures equal to the number of first gate structures. In some embodiments, the gate structures correspond to... Figure 1 Gate structure 116 in Figure 3 Gate structure 316 in Figure 4 Gate structure 416, or Figure 5 The gate structure 516 in the middle, and the first and second transistors correspond to Figure 1 , Figures 2A to 2D ,and Figures 3 to 5 MOS_A and MOS_B.

[0133] At block 756, the method includes forming a plurality of contact structures extending parallel to a second direction and intersecting at least one active region. The plurality of contact structures includes a number of contact structures equal to the number n of the mesh. A first contact structure in the plurality of contact structures is located between a first contact structure in a first gate structure and a first contact structure in a second gate structure. A second contact structure in the plurality of contact structures is located between a second contact structure in a first gate structure and a second contact structure in a second gate structure. In some embodiments, the contact structures correspond to... Figure 1 Contact structure 120 in Figure 3Contact structure 320 in Figure 4 Contact structure 420, or Figure 5 The contact structure in the middle is 520.

[0134] The described methods include instance operations, but they do not necessarily need to be performed in the order shown and / or described. Operations may be appropriately added, substituted, ordered, and / or eliminated according to the spirit and scope of the embodiments disclosed herein. Embodiments combining different features and / or different embodiments are within the scope of the embodiments disclosed herein and will be apparent to those skilled in the art upon review of the embodiments disclosed herein.

[0135] In some embodiments, at least one of the methods described above is performed, in whole or in part, by at least one EDA system. In some embodiments, the EDA system may be used as part of the design room of the IC manufacturing system described below.

[0136] Figure 8 This is a block diagram of an EDA system 800 according to some embodiments. The EDA system 800 is used to generate data as described above. Figure 7A The layout described above.

[0137] In some embodiments, EDA system 800 includes an automatic placement and routing (APR or APnR) system. The methods described herein for representing a design layout of cabling routing configurations according to one or more embodiments can be implemented using EDA system 800 according to some embodiments.

[0138] In some embodiments, the EDA system 800 is a general-purpose computing device including at least one hardware processor 802 and a non-transitory computer-readable storage medium 804. Among other things, the computer-readable storage medium 804 is encoded with, i.e., stores, computer program code 806, i.e., a set of computer-executable instructions. Execution of the instructions 806 by the processor 802 (at least partially) represents an EDA tool that implements some or all of the methods described herein (which may be referred to herein as the mentioned processes and / or methods) according to one or more embodiments.

[0139] Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 can be connected to network 814, allowing processor 802 and computer-readable storage medium 804 to be connected to external components via network 814. Processor 802 is used to execute computer program code 806 (instructions) encoded in (or stored in) computer-readable storage medium 804 so that EDA system 800 can be used to perform some or all of the mentioned processes and / or methods. In some embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0140] In some embodiments, computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). In some embodiments, computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disk, computer-readable storage medium 804 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W) memory, and / or digital video disc (DVD) memory.

[0141] In some embodiments, computer-readable storage medium 804 stores computer program code 806, which enables an EDA system 800 (where such execution represents (at least partially) EDA tools) to perform part or all of the mentioned processes and / or methods. In some embodiments, computer-readable storage medium 804 also stores information that facilitates the performance of part or all of the mentioned processes and / or methods. In some embodiments, computer-readable storage medium 804 stores a library 807 of standard cells, representing or including one or more of the layouts disclosed herein.

[0142] EDA system 800 includes I / O interface 810. I / O interface 810 is coupled to external circuitry or controllers, such as a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor keys for transmitting information and commands to processor 802.

[0143] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with network 814, where one or more other computer systems can be connected. In some embodiments, network interface 812 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In some embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EDA systems 800.

[0144] EDA system 800 receives information through I / O interface 810. The information received through I / O interface 810 includes instructions, data, design rules, standard cell libraries, and / or one or more other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. EDA system 800 also receives information related to user interface (UI) 842 through I / O interface 810. In some embodiments, information stored in computer-readable storage medium 804 encodes UI 842.

[0145] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by an EDA system 800. In some embodiments, a layout including standard cells is generated using a layout generation tool such as Cadence Design Systems' VIRTUOSO or other suitable layout generation tools.

[0146] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of such computer-readable recording media include external / removable and / or internal / built-in storage units or memory units, such as one or more of optical discs (such as DVDs), magnetic disks (such as hard disks), and semiconductor memories (such as ROM, RAM, memory cards, and the like).

[0147] Figure 9 This is a block diagram of an IC manufacturing system 900 and its associated IC manufacturing processes according to some embodiments. The IC manufacturing system 900 is used to manufacture semiconductor devices or integrated circuits according to the embodiments described herein.

[0148] In some embodiments, based on the layout, for example, at least one of the following is manufactured using IC manufacturing system 900: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0149] exist Figure 9 In this IC manufacturing system 900, entities such as design studio 920, masking room 930, and IC manufacturer / fab (“fabricator, fab”) 950 interact in the design, development, and manufacturing cycle and / or services related to the manufacturing of IC device 960. The entities in IC manufacturing system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. In some embodiments, the communication network includes wired and / or wireless communication channels. In some embodiments, each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design studio 920, masking room 930, and IC fab 950 are owned by a single, larger company. In some embodiments, two or more of design studio 920, masking room 930, and IC fab 950 coexist in a shared facility and use shared resources.

[0150] Design studio (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 960 to be manufactured. These layers are combined to form various IC features. For example, a portion of IC design layout 922 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and include various material layers disposed on the semiconductor substrate. In some embodiments, design studio 920 performs a formal design process to form IC design layout 922. In some embodiments, the design process includes one or more of logic design, physical design, or placement and routing. In some embodiments, IC design layout 922 is presented in one or more data files containing information of geometric patterns. For example, IC design layout 922 may be represented in GDSII file format or DFII file format.

[0151] Masking chamber 930 includes mask data preparation 932 and mask fabrication 944. Masking chamber 930 uses IC design layout 922 to fabricate one or more masks 945 for fabricating various layers of IC device 960 according to IC design layout 922. Masking chamber 930 performs mask data preparation 932, wherein IC design layout 922 is translated into a representative data file (RDF). Mask data preparation 932 provides the RDF to mask fabrication 944. In some embodiments, mask fabrication 944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 945 or a semiconductor wafer 953. IC design layout 922 is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of IC wafer fab 950. Figure 9 In the figure, mask data preparation 932 and mask manufacturing 944 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 944 may be collectively referred to as mask data preparation.

[0152] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as those that can cause self-diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0153] In some embodiments, mask data preparation 932 includes checking the IC design layout 922 with a mask rule checker (MRC). The MRC has undergone a process using an OPC that applies a set of mask generation rules, which contain certain geometric and / or connectivity constraints to ensure sufficient margin, take into account variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 922 to compensate for constraints during mask manufacturing 944, which may undo modifications performed via the OPC to satisfy the mask generation rules.

[0154] In some embodiments, mask data preparation 932 includes lithography process checking (LPC), an LPC simulation performed by IC wafer fab 950 to manufacture IC device 960. In some embodiments, LPC simulates this process based on IC design layout 922 to produce a simulated manufactured device, such as IC device 960. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture IC device 960, and / or other aspects of the manufacturing process. In some embodiments, LPC considers various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), similar factors, or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by LPC, if the simulated device does not adequately approximate the design rules in shape, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0155] For clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, mask data preparation 932 includes additional features, such as logic operations (LOPs), to modify the IC design layout 922 according to manufacturing rules. Additionally, the processes applied to the IC design layout 922 during mask data preparation 932 can be performed in a variety of different sequences.

[0156] After mask data preparation 932 and during mask manufacturing 944, mask 945 or a group of masks 945 is manufactured based on a modified IC design layout 922. In some embodiments, mask manufacturing 944 includes performing one or more lithography exposures based on the IC design layout 922. In some embodiments, an electron beam (e-beam, e-beam) or multiple electron beams are used to form a pattern on the mask (photomask or master photomask) 945 based on the modified IC design layout 922. Mask 945 can be formed using various techniques. In some embodiments, mask 945 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer, is blocked through the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas. In another example, mask 945 is formed using a phase shift mask (PSM) technique. In the phase shift mask (PSM) version of mask 945, various features in the pattern formed on the phase shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In some embodiments, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 944 can be used in a variety of processes. For example, such a mask can be used in ion implantation processes to form various doped regions in semiconductor wafer 953, in etching processes to form various etched regions in semiconductor wafer 953, and / or in other suitable processes.

[0157] IC wafer fab 950 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer fab 950 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple IC products, a second manufacturing facility that provides back-end-of-line (BEOL) manufacturing for interconnecting and packaging of IC products, and a third manufacturing facility that provides other services for the foundry business.

[0158] IC wafer fab 950 includes manufacturing tools 952 for performing various manufacturing operations on semiconductor wafers 953 to manufacture IC devices 960 according to masks(e.g., mask 945). In some embodiments, manufacturing tools 952 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0159] IC wafer fab 950 uses multiple masks 945 fabricated in mask chamber 930 to manufacture IC device 960. Therefore, IC wafer fab 950 uses IC design layout 922 at least indirectly to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is fabricated by IC wafer fab 950 using multiple masks 945 to form IC device 960. In some embodiments, IC fabrication includes performing one or more lithography exposures at least indirectly based on IC design layout 922. In some embodiments, semiconductor wafer 953 includes a silicon substrate or other suitable substrate on which material layers may be formed. In some embodiments, semiconductor wafer 953 includes one or more of various doped regions, dielectric features, multilevel interconnects, or the like (which may be formed at subsequent fabrication steps).

[0160] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 9 For detailed information on the IC manufacturing system 900 and its associated IC manufacturing processes, please refer to U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Principal Publication No. 2015 / 0278429A1, published October 1, 2015; U.S. Pre-Principal Publication No. 2014 / 0040838A1, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0161] This disclosure relates to an integrated circuit (IC) device. In some embodiments, the integrated circuit (IC) device includes an active region; a first wire extending along a first direction and corresponding to a first transistor, and a second wire extending along the first direction and corresponding to a second transistor, the first and second transistors being connected in series and divided into two or more meshes; a first gate structure connected to the first wire and corresponding to the first transistor, the first gate structures being spaced apart in a first direction and extending in a second direction; a second gate structure connected to the second wire and corresponding to the second transistor, the number of second gate structures being equal to the number of first gate structures; and a first contact structure between the first in the first gate structure and the first in the second gate structure, and a second contact structure between the second in the first gate structure and the second in the second gate structure, the number of contact structures being equal to the number of meshes.

[0162] In some embodiments, the active region is an N-type active region, and the first transistor and the second transistor are multiple NMOS transistors.

[0163] In some embodiments, the active region is a P-type active region, and the first transistor and the second transistor are multiple PMOS transistors.

[0164] In some embodiments, the first contact structure and the second contact structure, as well as the first and second of these second gate structures, are between the first of these first gate structures and the second of these first gate structures.

[0165] In some embodiments, the first gate structures and the second gate structures are configured in a first direction in a sequence “ABBA” in a cell region of an integrated circuit, wherein the first and second of the first gate structures are references to the first transistor “A”, and the first and second of the second gate structures are references to the second transistor “B”.

[0166] In some embodiments, the sequence “ABBA” is repeated a number i times in the cell region, where i is an integer greater than 0, and each of the first transistor and the second transistor has a number of pointers equal to 4i.

[0167] In some embodiments, the integrated circuit device includes a number of 4i of these contact structures that extend parallel to the second direction and intersect with the active region.

[0168] In some embodiments, the first gate structures and the second gate structures are disposed in a cell region of an integrated circuit, and in the cell region, a plurality of outermost gate structures correspond to an identical one of the first transistor and the second transistor.

[0169] In some embodiments, the first contact structure and the second contact structure do not have through holes in the through-hole layer, which is above the first contact structure and the second contact structure and below an overlay metal layer including the first wire and the second wire.

[0170] Another aspect of this disclosure relates to a method of manufacturing an integrated circuit (IC) device. In some embodiments, the method of manufacturing an integrated circuit (IC) device includes forming an active region; forming a first gate structure corresponding to a first transistor, the first gate structures being spaced apart in a first direction and extending in a second direction; forming a second gate structure corresponding to a second transistor, the second gate structures being formed in a number equal to the number of first gate structures; forming a first contact structure between a first of the first gate structures and a first of the second gate structures; forming a second contact structure between a second of the first gate structures and a second of the second gate structures; forming a first wire extending in a first direction and connected to the first gate structure and corresponding to the first transistor; and forming a second wire extending in a first direction and connected to the second gate structure and corresponding to the second transistor. The first transistor and the second transistor are formed in series and divided into two or more meshes, and the contact structures are formed in a number equal to the number of meshes.

[0171] In some embodiments, the step of forming an active region includes the following steps: forming an N-type active region, wherein the first transistor and the second transistor are multiple NMOS transistors.

[0172] In some embodiments, the step of forming an active region includes the following steps: forming a P-type active region, wherein the first transistor and the second transistor are a plurality of PMOS transistors.

[0173] In some embodiments, the step of forming a first contact structure and a second contact structure and the first and second of these second gate structures includes the step of forming the first contact structure and the second contact structure and the first and second of these second gate structures between the first of these first gate structures and the second of these first gate structures.

[0174] In some embodiments, the first gate structures and the second gate structures are formed in a first direction in a cell region of an integrated circuit device in a sequence “ABBA”, wherein the first and second of the first gate structures are references to the first transistor “A”, and the first and second of the second gate structures are references to the second transistor “B”.

[0175] In some embodiments, the first gate structures and the second gate structures are configured such that the sequence “ABBA” is repeated a number i times in the cell region, where i is an integer greater than 0, and each of the first transistor and the second transistor has a number of pointers equal to 4i.

[0176] In some embodiments, the step of forming the first contact structure and the second contact structure includes the following steps: forming a number of 4i contact structures that extend parallel to the second direction and intersect with the active area.

[0177] In some embodiments, the first gate structures and the second gate structures are formed in a cell region of an integrated circuit, and in the cell region, a plurality of outermost gate structures correspond to an identical one of the first transistor and the second transistor.

[0178] In some embodiments, the first contact structure and the second contact structure are formed without through holes in a through-hole layer, the through-hole layer being above a metal-to-diffusion layer including the first contact structure and the second contact structure and below a metal layer including the first conductor and the second conductor.

[0179] Another aspect of this disclosure relates to an integrated circuit device. The integrated circuit device includes an active region, a plurality of first gate structures corresponding to a first transistor, a plurality of second gate structures corresponding to a second transistor, a first contact structure, a second contact structure, a first wire extending in a first direction and connected to these first gate structures and corresponding to the first transistor; and a second wire extending in the first direction and connected to these second gate structures and corresponding to the second transistor. The first gate structures are spaced apart in the first direction and extend in a second direction. The second gate structures are formed in a number equal to the number of first gate structures. A first contact structure is formed between a first of these first gate structures and a first of these second gate structures. A second contact structure is formed between a second of these first gate structures and a second of these second gate structures. The first transistor and the second transistor are formed in series and divided into two or more grids. The plurality of contact structures including the first and second contact structures are formed in a number equal to the number of grids.

[0180] In some embodiments, the first gate structures and the second gate structures are configured in a sequence “ABBA” in a first direction within a cell region of the integrated circuit device, wherein the first and second of the first gate structures are pointers “A” to a first transistor, and the first and second of the second gate structures are pointers “B” to a second transistor. The sequence “ABBA” is repeated a number i times in the cell region, where i is an integer greater than 0, and each of the first and second transistors has a number of pointers equal to 4i. The integrated circuit device also includes a number 4i of the plurality of contact structures extending parallel to the second direction and intersecting the active region.

[0181] In some embodiments, the first contact structure and the second contact structure do not have through holes in the through-hole layer, which is above the first contact structure and the second contact structure and below the overlying metal layer including the first conductor and the second conductor.

[0182] Another aspect of this disclosure relates to an integrated circuit (IC) device. In some embodiments, the integrated circuit (IC) device includes an active region; gate structures intersecting the active region, the gate structures including: a first gate structure corresponding to a first transistor, the first gate structures being spaced apart in a first direction and extending in a second direction, and a second gate structure corresponding to a second transistor, the number of second gate structures being equal to the number of first gate structures, the first and second transistors being connected in series and divided into two or more meshes; contact structures intersecting the active region, the contact structures including: a first contact structure between a first one in the first gate structure and a first one in the second gate structure, and a second contact structure between a second one in the first gate structure and a second one in the second gate structure, the number of contact structures being equal to the number of meshes; a first wire extending in the first direction and connected to the first gate structure and corresponding to the first transistor; and a second wire extending in the first direction and connected to the second gate structure and corresponding to the second transistor.

[0183] In some embodiments, the first transistor has the same conductivity type as the second transistor.

[0184] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of the embodiments disclosed herein. Those skilled in the art will understand that the embodiments disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same benefits. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of the embodiments disclosed herein.

Claims

1. An integrated circuit device, characterized in that, Include: One active zone; A first wire extending along a first direction and corresponding to a first transistor, and a second wire extending along the first direction and corresponding to a second transistor, the first transistor and the second transistor being connected in series and divided into two or more meshes; A plurality of first gate structures are connected to the first wire and correspond to the first transistor, the plurality of first gate structures being spaced apart in the first direction and extending in a second direction; A plurality of second gate structures connected to the second wire and corresponding to the second transistor, wherein the number of the plurality of second gate structures is equal to the number of the first gate structures; and A first contact structure between a first of the plurality of first gate structures and a first of the plurality of second gate structures, and a second contact structure between a second of the plurality of first gate structures and a second of the plurality of second gate structures, wherein the number of contact structures is equal to the number of meshes.

2. The integrated circuit device as claimed in claim 1, characterized in that, The active region is an N-type active region, and the first transistor and the second transistor are multiple NMOS transistors.

3. The integrated circuit device as claimed in claim 1, characterized in that, The active region is a P-type active region, and the first transistor and the second transistor are multiple PMOS transistors.

4. The integrated circuit device as claimed in claim 1, characterized in that, The first contact structure, the second contact structure, and the first and second of the plurality of second gate structures are located between the first of the plurality of first gate structures and the second of the plurality of first gate structures.

5. The integrated circuit device as claimed in claim 1, characterized in that, The plurality of first gate structures and the plurality of second gate structures are arranged in a sequence "ABBA" in a first direction in a cell region of the integrated circuit device, wherein the first and second of the plurality of first gate structures are references to the first transistor "A", and the first and second of the plurality of second gate structures are references to the second transistor "B". The sequence "ABBA" is repeated i times in the cell region, where i is an integer greater than 0, and each of the first transistor and the second transistor has a number of pointers equal to 4i. It includes a number of 4i contact structures that extend parallel to the second direction and intersect the active area.

6. The integrated circuit device as claimed in claim 1, characterized in that, The plurality of first gate structures and the plurality of second gate structures are disposed in a cell region of the integrated circuit device, and the plurality of outermost gate structures in the cell region correspond to an identical one of the first transistor and the second transistor.

7. An integrated circuit device, characterized in that, Include: One active zone; A plurality of first gate structures corresponding to a first transistor, the plurality of first gate structures being spaced apart in a first direction and extending in a second direction; A plurality of second gate structures corresponding to a second transistor, the plurality of second gate structures being formed in a number equal to the number of first gate structures; A first contact structure is located between a first of the plurality of first gate structures and a first of the plurality of second gate structures; A second contact structure is located between a second of the plurality of first gate structures and a second of the plurality of second gate structures; A first wire extending in the first direction and connected to the plurality of first gate structures and corresponding to the first transistor; and A second wire extends in the first direction and connects to the plurality of second gate structures and corresponds to the second transistor. in: The first transistor and the second transistor are connected in series and divided into two or more meshes, and Multiple contact structures, including the first contact structure and the second contact structure, are formed in a number equal to the number of the mesh.

8. The integrated circuit device as claimed in claim 7, characterized in that, The plurality of first gate structures and the plurality of second gate structures are arranged in a sequence "ABBA" in a first direction in a cell region of the integrated circuit device, wherein the first and second of the plurality of first gate structures are references to the first transistor "A", and the first and second of the plurality of second gate structures are references to the second transistor "B". The sequence "ABBA" is repeated i times in the cell region, where i is an integer greater than 0, and each of the first transistor and the second transistor has a number of pointers equal to 4i. The integrated circuit device also includes a plurality of contact structures, numbered 4i, that extend parallel to the second direction and intersect the active region.

9. The integrated circuit device as claimed in claim 7, characterized in that, The first contact structure and the second contact structure do not have through holes in a through-hole layer, which is above the first contact structure and the second contact structure and below an overlay metal layer including the first wire and the second wire.

10. A semiconductor device, characterized in that, Include: One active zone; A plurality of gate structures intersecting the active region, the plurality of gate structures including: A plurality of first gate structures corresponding to a first transistor, the plurality of first gate structures being spaced apart in a first direction and extending in a second direction, and A plurality of second gate structures corresponding to a second transistor, wherein the number of the plurality of second gate structures is equal to the number of the plurality of first gate structures. The first transistor and the second transistor are connected in series and are divided into two or more grids; Multiple contact structures intersecting the active area, the multiple contact structures including: A first contact structure between a first of the plurality of first gate structures and a first of the plurality of second gate structures, and A second contact structure between one of the plurality of first gate structures and another of the plurality of second gate structures. The number of the plurality of contact points is equal to the number of the mesh; A first wire extending in the first direction and connected to the plurality of first gate structures and corresponding to the first transistor; and A second wire extends in the first direction and is connected to the plurality of second gate structures and corresponds to the second transistor.

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