Clock generation circuit, chip, and electronic device
By introducing an error amplification module, a voltage feedback module, and a voltage-controlled oscillator module into the RC oscillator, and using a random resistor and a frequency resistor conversion unit to adjust the clock signal frequency, the electromagnetic interference problem caused by the fixed output frequency of the RC oscillator is solved, and random frequency variation is achieved to reduce electromagnetic interference.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEFEI CHIPSEA ELECTRONICS TECH CO LTD
- Filing Date
- 2025-05-09
- Publication Date
- 2026-06-12
Smart Images
Figure CN224356087U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically to a clock generating circuit, chip, and electronic device. Background Technology
[0002] Currently, an RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor. Due to its advantages such as low cost, fast circuit startup, and ease of on-chip integration, it is widely used in on-chip systems where the accuracy and frequency requirements of the clock source are not high.
[0003] However, when the RC oscillator outputs a clock signal of a fixed frequency to control the operation of the corresponding circuit, such as when the working circuit (e.g., DC-DC circuit) is controlled by a clock signal of a fixed frequency, the working circuit will usually generate electromagnetic interference (EMI) signals with large energy, which may cause other circuit modules of the on-chip system to malfunction. Utility Model Content
[0004] In view of the above problems, embodiments of this application provide a clock generating circuit, chip, and electronic device to solve the above technical problems.
[0005] In a first aspect, embodiments of this application provide a clock generation circuit, including:
[0006] A voltage feedback module used to output feedback voltage based on a clock signal;
[0007] An error amplification module is connected to a reference voltage and is connected to a voltage feedback module to output a control voltage based on the reference voltage and the feedback voltage.
[0008] A voltage-controlled oscillator module is connected to an error amplifier module to oscillate under the control of a control voltage and output a clock signal.
[0009] The voltage feedback module includes a random resistor unit and a frequency resistor conversion unit. During the operation of the clock generation circuit, the resistance of the random resistor unit changes randomly, and the resistance of the frequency resistor conversion unit is related to the frequency of the clock signal.
[0010] Secondly, embodiments of this application also provide a chip including the clock generation circuit described above.
[0011] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip or clock generating circuit.
[0012] This application forms a loop using an error amplification module, a voltage feedback module, and a voltage-controlled oscillator module. Feedback control enables the voltage-controlled oscillator module to output a clock signal. Since the random resistor unit and frequency conversion unit of the voltage feedback module can affect the magnitude of the feedback voltage, and the resistance of the random resistor unit varies randomly, the frequency of the clock signal output by the clock generation circuit can also vary randomly according to the resistance of the random resistor unit. This achieves a spread spectrum process for the clock signal, ultimately helping to reduce the electromagnetic interference radiation energy generated by the circuit operating under clock signal control.
[0013] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 A circuit diagram of an RC oscillator in related technologies is shown.
[0016] Figure 2 A schematic diagram of a clock generation circuit in an embodiment of this application is shown.
[0017] Figure 3 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.
[0018] Figure 4 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.
[0019] Figure 5 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.
[0020] Figure 6 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.
[0021] Figure 7 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown.
[0022] Figure 8 This illustration shows a schematic diagram of a switched resistor array and a frequency-resistance conversion unit in an embodiment of this application.
[0023] Among them, there are 10 voltage feedback modules, 11 random resistor units, 111 random signal generators, 112 switched resistor arrays, 12 frequency resistor conversion units, 121 non-overlapping clock units, 20 error amplifier modules, and 30 voltage-controlled oscillator modules.
[0024] Power supply VDD, ground GND, feedback voltage Vfb, reference voltage Vref, control voltage Vctrl, clock signal CLK, operational amplifier OP, first capacitor C1, second capacitor C2, first switch S11~S1(n+1), first resistor R11~R1n, second switch S2, third switch S3, first clock signal CLKA, second clock signal CLKB, random signal D[1:n+1]. Detailed Implementation
[0025] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0026] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0027] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0028] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0029] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.
[0030] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.
[0031] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0032] Currently, an RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltage during the charging and discharging process. (See also...) Figure 1 , Figure 1 The diagram shows a circuit diagram of an RC oscillator in the related art. The RC oscillator includes comparator COMP1, comparator COMP2, an RS flip-flop composed of two NAND gates, capacitor Cx, capacitor Cy, transistor MN1 for controlling the charging and discharging of capacitor Cx, and transistor MN2 for controlling the charging and discharging of capacitor Cy.
[0033] During the operation of the RC oscillator, the two NAND gates output control signals OUT1 and OUT2 respectively, thereby controlling transistors MN1 and MN2 to alternately charge capacitors Cx and Cy. When the output voltages IN1 and IN2 of capacitors Cx and Cy exceed the reference voltage Vref, one of capacitors Cx and Cy is switched to charge while the other is discharged, so that the output terminals of comparators COMP1 and COMP2 output clock signals that alternate between high and low levels.
[0034] In an ideal scenario where feedback loop delay (e.g., comparator delay) is neglected, and the capacitor Cx\Cy charges to the reference voltage Vref for half a cycle of the clock signal, the oscillation frequency f of the output clock signal can be determined as follows:
[0035] f = N / (2RC)
[0036] Where N is the ratio of the charging current NIref of capacitor Cx\Cy to the reference current Iref, R is the resistor corresponding to the generated reference voltage Vref, and C is the capacitance value of capacitor Cx\Cy.
[0037] As can be seen, an RC oscillator can output a clock signal at a fixed frequency. However, when a fixed-frequency clock signal controls the operation of the corresponding circuit, such as controlling the switching action of a DC-DC circuit, the DC-DC circuit will usually generate electromagnetic interference signals with high energy, which may cause other circuits in the on-chip system to malfunction.
[0038] Therefore, this application provides a clock generating circuit, a chip, and an electronic device, which are described in detail below.
[0039] First, refer to Figure 2 , Figure 2 A schematic diagram of a clock generation circuit in an embodiment of this application is shown, wherein the clock generation circuit includes a voltage feedback module 10, an error amplification module 20, and a voltage-controlled oscillator module 30.
[0040] Specifically, the voltage feedback module 10 is used to output a feedback voltage Vfb according to the clock signal CLK. Generally, the magnitude of the feedback voltage Vfb is negatively correlated with the frequency of the clock signal CLK. For example, when the frequency of the clock signal CLK is higher, the voltage value of the feedback voltage Vfb is smaller; conversely, when the frequency of the clock signal CLK is lower, the voltage value of the feedback voltage Vfb is larger.
[0041] In some embodiments of this application, the voltage feedback module 10 may include a switched capacitor circuit. Since a capacitor has the characteristic of passing AC while blocking DC, the higher the frequency at which the clock signal CLK controls the switch to open / close, the lower the impedance of the capacitor; conversely, the lower the frequency at which the clock signal CLK controls the switch to open / close, the higher the impedance of the capacitor. Because the impedance of the switched capacitor circuit affects the magnitude of the feedback voltage Vfb, the voltage feedback module 10 can output a feedback voltage Vfb whose magnitude is related to the frequency of the clock signal CLK.
[0042] In some embodiments of this application, the voltage feedback module 10 may include a switched inductor circuit. Since an inductor has the characteristic of passing DC and blocking AC, the higher the frequency at which the clock signal CLK controls the switch to open / close, the greater the impedance of the inductor; conversely, the lower the frequency at which the clock signal CLK controls the switch to open / close, the smaller the impedance of the inductor. Because the impedance of the switched inductor circuit affects the magnitude of the feedback voltage Vfb, the voltage feedback module 10 can output a feedback voltage Vfb whose magnitude is related to the frequency of the clock signal CLK.
[0043] The error amplification module 20 outputs a control voltage Vctrl based on the reference voltage Vref and the feedback voltage Vfb, so as to control the voltage-controlled oscillator module 30 to oscillate and output a clock signal CLK. As an example, see [reference needed]. Figure 3 , Figure 3 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown. In this circuit, the error amplification module 20 may include an operational amplifier OP. The non-inverting input of the operational amplifier OP is connected to a reference voltage Vref, and the inverting input of the operational amplifier OP is connected to a feedback voltage Vfb. Due to the virtual short and virtual open characteristics of the operational amplifier OP, the control voltage Vctrl output by the operational amplifier OP changes the frequency of the clock signal CLK, thereby causing the feedback voltage Vfb to follow the frequency of the clock signal CLK and approach the reference voltage Vref. Finally, after the loop formed by the error amplification module 20, the voltage feedback module 10, and the voltage-controlled oscillator module 30 stabilizes, the frequency of the clock signal CLK is locked.
[0044] The control terminal of the voltage-controlled oscillator module 30 is connected to the output terminal of the error amplifier module 20 to oscillate under the control of the control voltage Vctrl and output a clock signal CLK. In some embodiments of this application, the frequency of the clock signal CLK output by the voltage-controlled oscillator module 30 is positively correlated with the magnitude of the control voltage Vctrl. For example, when the control voltage Vctrl is larger, the frequency of the clock signal CLK output by the voltage-controlled oscillator module 30 is larger; conversely, when the control voltage Vctrl is smaller, the frequency of the clock signal CLK output by the voltage-controlled oscillator module 30 is smaller.
[0045] In some embodiments of this application, the frequency of the clock signal CLK output by the voltage-controlled oscillator module 30 is negatively correlated with the magnitude of the control voltage Vctrl. For example, the smaller the control voltage Vctrl, the higher the frequency of the clock signal CLK output by the voltage-controlled oscillator module 30; conversely, the higher the control voltage Vctrl, the lower the frequency of the clock signal CLK output by the voltage-controlled oscillator module 30.
[0046] For example, the voltage-controlled oscillator module 30 may include, but is not limited to, a harmonic oscillator or a relaxation oscillator, wherein the harmonic oscillator is such as an LC crystal oscillator and a crystal oscillator, and the relaxation oscillator is such as a delay-based ring voltage-controlled oscillator, a ground capacitance-based voltage-controlled oscillator, or an emitter-coupled voltage-controlled oscillator.
[0047] In this embodiment of the application, the voltage feedback module 10 includes a random resistor unit 11 and a frequency resistor conversion unit 12. The magnitude of the feedback voltage Vfb is related to the resistance of the random resistor unit 11 and the magnitude of the feedback voltage Vfb is related to the resistance of the frequency resistor conversion unit 12.
[0048] For example, with Figure 2 For example, the random resistor unit 11 and the frequency resistor conversion unit 12 are connected in series between the power supply terminal VDD and the ground terminal GND. At this time, the feedback voltage Vfb output by the voltage feedback module 10 satisfies the following relationship:
[0049]
[0050] Where Rx is the resistance of the frequency resistor conversion unit 12, and Ry is the resistance of the random resistor unit 11.
[0051] As can be seen from the above formula, the magnitude of the feedback voltage Vfb is negatively correlated with the resistance of the random resistor unit 11, and the magnitude of the feedback voltage Vfb is positively correlated with the resistance of the frequency resistor conversion unit 12.
[0052] For example, see Figure 4 , Figure 4 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown, wherein the frequency resistor conversion unit 12 and the random resistor unit 11 are connected in series between the power supply terminal VDD and the ground terminal GND. In this case, the feedback voltage Vfb output by the voltage feedback module 10 satisfies the following relationship:
[0053]
[0054] As can be seen from the above formula, the magnitude of the feedback voltage Vfb is positively correlated with the resistance of the random resistor unit 11, and the magnitude of the feedback voltage Vfb is negatively correlated with the resistance of the frequency resistor conversion unit 12.
[0055] Meanwhile, in this embodiment of the application, during the operation of the clock generation circuit, the resistance of the random resistor unit 11 changes randomly, and the resistance of the frequency resistor conversion unit 12 is related to the frequency of the clock signal CLK. Therefore, the frequency of the clock signal CLK output by the clock generation circuit can change randomly following the resistance of the random resistor unit 11.
[0056] For example, the feedback voltage Vfb output by the voltage feedback module 10, the resistance of the frequency-resistance conversion unit 12, and the frequency of the clock signal CLK satisfy the following relationship:
[0057]
[0058] Rx=k*f
[0059] Where k is a fixed coefficient and f is the frequency of the clock signal CLK.
[0060] During the feedback control operation of the clock generation circuit, the magnitude of the feedback voltage Vfb always approaches the reference voltage Vref. Therefore, combining the above formula, we can obtain:
[0061]
[0062] Therefore, based on the above formula, the frequency of the clock signal CLK satisfies the following relationship:
[0063]
[0064] As can be seen from the above calculation formula, since the resistance Ry of the random resistor unit 11 changes randomly, the frequency of the clock signal CLK output by the clock generation circuit will change randomly with the resistance of the random resistor unit 11. This can achieve the spread spectrum of the clock signal CLK, which ultimately helps to reduce the electromagnetic interference radiation energy generated by the working circuit under the control of the clock signal CLK.
[0065] In some embodiments of this application, the resistance of the frequency resistor conversion unit 12 is negatively correlated with the frequency of the clock signal CLK. That is, the higher the frequency of the clock signal CLK, the larger the resistance of the frequency resistor conversion unit 12; conversely, the lower the frequency of the clock signal CLK, the smaller the resistance of the frequency resistor conversion unit 12.
[0066] As an example, see Figure 5 , Figure 5 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown, wherein the frequency resistor conversion unit 12 includes a non-overlapping clock unit 121 for outputting a first clock signal CLKA and a second clock signal CLKB according to the clock signal CLK, a first capacitor C1, a second switch S2, and a third switch S3; the first terminal of the second switch S2 is connected to the random resistor unit 11, and the second terminal of the second switch S2 is connected to the first terminal of the first capacitor C1; the first terminal of the third switch S3 is connected to the first terminal of the first capacitor C1, and the second terminal of the third switch S3 is connected to the second terminal of the first capacitor C1; wherein the control terminal of the second switch S2 is connected to the non-overlapping clock unit 121 to receive the first clock signal CLKA, and the control terminal of the third switch S3 is connected to the non-overlapping clock unit 121 to receive the second clock signal CLKB.
[0067] It should be noted that the first clock signal CLKA and the second clock signal CLKB do not overlap. The non-overlapping first clock signal CLKA and second clock signal CLKB allow the second switch S2 and the third switch S3 to not close or open simultaneously. For example, when the second switch S2 is closed and the third switch S3 is open, the power supply terminal VDD charges the first capacitor C1 through the random resistor unit 11; when the second switch S2 is open and the third switch S3 is closed, the first capacitor C1 discharges into the ground terminal GND. According to the formula for calculating the equivalent impedance of a switched capacitor, the equivalent impedance R of the first capacitor C1 at this time is:
[0068]
[0069] Where f is the frequency of the first clock signal CLKA and the second clock signal CLKB (i.e., the frequency of the clock signals), and C is the capacitance value of the first capacitor C1.
[0070] As can be seen from the above formula, the resistance of the frequency-resistance conversion unit 12 is negatively correlated with the frequency of the clock signal CLK. Furthermore, based on the foregoing, the magnitude of the feedback voltage Vfb generated by the voltage feedback module 10 can be calculated using the following formula:
[0071]
[0072] Therefore, it can be known that in Figure 5 In the embodiment, the frequency of the clock signal CLK satisfies the following relationship:
[0073]
[0074] As can be seen from the above formula, during the operation of the clock generation circuit, the frequency of the clock signal CLK output by the clock generation circuit will also change randomly because the resistance of the random resistor unit 11 changes randomly.
[0075] In some embodiments of this application, see Figure 6 , Figure 6 Another schematic diagram of the clock generation circuit in an embodiment of this application is shown, wherein the frequency resistor conversion unit 12 further includes a second capacitor C2, the first end of the second capacitor C2 is connected to the first end of the second switch S2, and the second end of the second capacitor C2 is connected to the second end of the first capacitor C1.
[0076] It should be noted that since the second switch S2 and the third switch S3 do not close or open simultaneously, the feedback voltage Vfb output by the voltage feedback module 10 may exhibit significant jitter, which could degrade the periodic jitter performance of the clock signal CLK. In the above embodiment, the second capacitor C2 in the frequency resistor conversion unit 12 can stabilize the feedback voltage Vfb, thereby solving the problem of significant jitter in the feedback voltage Vfb causing degraded periodic jitter performance of the clock signal CLK.
[0077] In some embodiments of this application, see Figure 7 , Figure 7Another schematic diagram of the clock generation circuit in an embodiment of this application is shown, wherein the random resistor unit 11 includes a random signal generator 111 for outputting a random signal D[1:n+1] and a switched resistor array 112; the switched resistor array 112 is connected in series with the frequency resistor conversion unit 12, and the switched resistor array 112 changes its resistance in response to the random signal D[1:n+1] output by the random signal generator 111.
[0078] It should be noted that the random signal generator 111 can output a random signal D[1:n+1]. For example, the random signal generator 111 can be, but is not limited to, a true random number generator, a pseudo random number generator, or a hybrid random number generator. The random signal D[1:n+1] can be a multi-byte digital signal, and each byte of the signal can control a corresponding switch. Therefore, by controlling the closing of the switches in the switch resistor array 112 through the random signal D[1:n+1], the resistance of the switch resistor array 112 can be changed.
[0079] As an exemplary embodiment, see [reference] Figure 8 , Figure 8 The diagram shows a schematic of a switch resistor array 112 and a frequency resistor conversion unit 12 in an embodiment of this application. The switch resistor array 112 includes a plurality of first resistors R11, R12...R1n and a plurality of first switches S11, S12...S1(n+1). The plurality of first resistors R11, R12...R1n are connected in series. One end of each first resistor is connected to the first end of a first switch, and the second ends of the plurality of first switches S11, S12...S1(n+1) are connected to each other.
[0080] It should be noted that, in Figure 8 In the process, the random signal generator 111 outputs a random signal D[1:n+1] with an n+1-bit random one-hot code, which can control n+1 first switches S11 to S1(n+1). Normally, the random signal D[1:n+1] will only control one first switch to close, thus making the resistance value of the switch resistor array 112 change randomly.
[0081] For example, when the first switch S11 is closed, the total resistance of the switch resistor array 112 is R0; when the first switch S12 is closed, the total resistance of the switch resistor array 112 is R0+R11; when the first switch S13 is closed, the total resistance of the switch resistor array 112 is R0+R11+R12; and so on. When the first switch S1n is closed, the total resistance of the switch resistor array 112 is R0+R11+R12+...+R1(n-1); when the first switch S1(n+1) is closed, the total resistance of the switch resistor array 112 is R0+R11+R12+...+R1n.
[0082] In other words, the total resistance value of the switch resistor array 112 can be randomly varied between R0 and R0+R11+R12+...+R1n by using the random signal D[1:n+1].
[0083] Based on the foregoing, the frequency range of the clock signal CLK output by the clock generation circuit of this application is:
[0084]
[0085] It can be seen that when the random signal D[1:n+1] controls the closing of one of the first switches in the switch resistor array 112, the resistance value of the switch resistor array 112 will change. Since the random signal D[1:n+1] changes randomly, the resistance value of the switch resistor array 112 can change randomly, thereby realizing the spread spectrum process of the clock signal CLK.
[0086] It is understood that the above embodiments are only exemplary embodiments of the switch resistor array 112, and are not actually limited thereto. For example, this application may also connect multiple first resistors in the switch resistor array 112 in parallel, and change the number of first resistors in parallel by multiple first switches, so that the total resistance value of the switch resistor array 112 changes randomly.
[0087] It is worth noting that the above description of the clock generation circuit is intended to clearly illustrate the implementation and verification process of this application. Those skilled in the art can make equivalent modifications under the guidance of this application. For example, the switched resistor array 112 and the frequency resistor conversion unit 12 can be connected in parallel. After the parallel connection, the resistance value of either the switched resistor array 112 or the frequency resistor conversion unit 12 changes, and the resistance value of the voltage feedback module 10 changes, thereby changing the magnitude of the feedback voltage Vfb and spreading the clock signal CLK.
[0088] This application also provides a chip that includes the clock generation circuit described above. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip of this application possesses the clock generation circuit described in the above embodiments, it has all the beneficial effects of the clock generation circuit in the above embodiments, and will not be repeated here.
[0089] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.
[0090] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A clock generating circuit, characterized in that, include: A voltage feedback module used to output feedback voltage based on a clock signal; An error amplification module is connected to a reference voltage and is connected to the voltage feedback module to output a control voltage based on the reference voltage and the feedback voltage. A voltage-controlled oscillator module, which is connected to the error amplifier module, oscillates under the control of the control voltage and outputs the clock signal; The voltage feedback module includes a random resistor unit and a frequency resistor conversion unit. During the operation of the clock generation circuit, the resistance of the random resistor unit changes randomly, and the resistance of the frequency resistor conversion unit is related to the frequency of the clock signal.
2. The clock generation circuit as described in claim 1, characterized in that, The resistance of the frequency-resistance conversion unit is negatively correlated with the frequency of the clock signal.
3. The clock generating circuit as described in claim 1, characterized in that, The magnitude of the feedback voltage is related to the resistance of the random resistor unit, and the magnitude of the feedback voltage is related to the resistance of the frequency resistor conversion unit.
4. The clock generating circuit as described in claim 3, characterized in that, The magnitude of the feedback voltage is negatively correlated with the resistance of the random resistor unit, and positively correlated with the resistance of the frequency resistor conversion unit.
5. The clock generating circuit as described in claim 3, characterized in that, The magnitude of the feedback voltage is positively correlated with the resistance of the random resistor unit, and negatively correlated with the resistance of the frequency resistor conversion unit.
6. The clock generating circuit as described in claim 1, characterized in that, The random resistor unit includes a random signal generator and a switched resistor array; The switched resistor array is connected in series with the frequency-resistance conversion unit, and the switched resistor array changes its resistance in response to the random signal output by the random signal generator.
7. The clock generating circuit as described in claim 6, characterized in that, The switched resistor array includes a plurality of first resistors and a plurality of first switches; Multiple first resistors are connected in series, one end of each first resistor is connected to the first end of a first switch, and the second ends of the multiple first switches are connected to each other.
8. The clock generating circuit as described in claim 1, characterized in that, The frequency-resistance conversion unit includes a non-overlapping clock unit for outputting a first clock signal and a second clock signal according to the clock signal, a first capacitor, a second switch, and a third switch. The first terminal of the second switch is connected to the random resistor unit, and the second terminal of the second switch is connected to the first terminal of the first capacitor. The first terminal of the third switch is connected to the first terminal of the first capacitor, and the second terminal of the third switch is connected to the second terminal of the first capacitor. Wherein, the first clock signal and the second clock signal do not overlap, the control terminal of the second switch is connected to the non-overlapping clock unit to access the first clock signal, and the control terminal of the third switch is connected to the non-overlapping clock unit to access the second clock signal.
9. The clock generating circuit as described in claim 8, characterized in that, The frequency-resistance conversion unit also includes a second capacitor; The first terminal of the second capacitor is connected to the first terminal of the second switch, and the second terminal of the second capacitor is connected to the second terminal of the first capacitor.
10. A chip, characterized in that, Includes the clock generation circuit as described in any one of claims 1 to 9.
11. An electronic device, characterized in that, It includes a device body and a chip as described in claim 10 disposed on the device body.