A semiconductor device

Abstract

The utility model discloses a semiconductor device, wherein, the semiconductor device includes: substrate, the channel layer and the barrier layer of substrate one side, the gate structure is located barrier layer far from substrate one side, the first passivation layer, the first passivation layer includes first opening and second opening, and first opening and second opening are located at the both sides of gate structure respectively, and first opening and second opening expose barrier layer, and the barrier layer that first opening and second opening expose includes electronegativity atom doped layer far from substrate, and the electronegativity of electronegativity atom is greater than or equal to the electronegativity of oxygen atom, the second passivation layer, the first electrode, and the first electrode is located first opening far from the one side of gate structure, the second electrode, and the second electrode is located second opening far from the one side of gate structure. The utility model realizes the lower leakage current of gate structure at the same time, and improves the concentration and mobility of two-dimensional electron gas of device.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] For existing gallium nitride (GaN) high electron mobility transistors (HEMTs), the surface of the barrier layer and the surface of the gate structure are covered by the same passivation layer. That is, the drift region of the GaN HEMT device away from the substrate is covered by the same passivation layer as the surface of the gate structure. The setting of the same passivation layer cannot simultaneously meet the requirements of high concentration, high mobility of two-dimensional electron gas and effective protection of the gate structure. Utility Model Content

[0003] This invention provides a semiconductor device to solve the problem that current passivation layer settings cannot simultaneously meet the requirements of high concentration and high mobility of two-dimensional electron gas and effective protection of the gate structure.

[0004] In a first aspect, the present invention provides a semiconductor device, wherein the semiconductor device comprises:

[0005] Substrate;

[0006] The channel layer is located on one side of the substrate;

[0007] Barrier layer, located on the side of the channel layer away from the substrate;

[0008] The gate structure is located on the side of the barrier layer away from the substrate;

[0009] A first passivation layer, comprising a first sub-passivation layer and a second sub-passivation layer; the first sub-passivation layer is located on the side of the gate structure and barrier layer away from the substrate, and the second sub-passivation layer is located on the side of the first sub-passivation layer away from the substrate; the first passivation layer includes a first opening and a second opening, the first opening and the second opening being located on opposite sides of the gate structure, the first opening and the second opening exposing the barrier layer; the side of the barrier layer exposed by the first opening and the second opening away from the substrate includes an electronegative atom doped layer, the electronegativity of the electronegative atoms being greater than or equal to the electronegativity of oxygen atoms;

[0010] The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer; the third sub-passivation layer is located on the side of the first passivation layer away from the substrate, and the third sub-passivation layer fills the first opening and the second opening; the fourth sub-passivation layer is located on the side of the third sub-passivation layer away from the substrate.

[0011] The gate field plate is located on the side of the second passivation layer away from the substrate, and the vertical projection of the gate field plate onto the substrate covers the vertical projection of the gate structure onto the substrate.

[0012] The first electrode is located on the side of the first opening away from the gate structure;

[0013] The second electrode is located on the side of the second opening away from the gate structure.

[0014] Optionally, the thickness of the third sub-passivation layer is less than the thickness of the first sub-passivation layer.

[0015] Optionally, the thickness of the first sub-passivation layer is 5nm-100nm, and the thickness of the third sub-passivation layer is 0.5nm-5nm.

[0016] Optionally, the first sub-passivation layer includes a first aluminum nitride layer, and the second sub-passivation layer includes a second aluminum nitride layer.

[0017] Optionally, the electronegative atom doped layer includes an oxygen atom doped layer and / or a fluorine atom doped layer.

[0018] Optionally, the gate structure is located in the middle region of the barrier layer on the side away from the substrate, and the center line of the gate field plate coincides with the center line of the gate structure; the distance between the vertical projection of the first opening on the substrate and the vertical projection of the gate structure on the substrate is the same as the distance between the vertical projection of the second opening on the substrate and the vertical projection of the gate structure on the substrate; the opening size of the first opening is the same as the opening size of the second opening.

[0019] The distance between the vertical projection of the first electrode onto the substrate and the vertical projection of the first opening onto the substrate is the same as the distance between the vertical projection of the second electrode onto the substrate and the vertical projection of the second opening onto the substrate; both the first electrode and the second electrode are in contact with the barrier layer.

[0020] Optionally, the vertical projection of the gate field plate onto the substrate does not overlap with the vertical projection of the first opening onto the substrate, and the vertical projection of the gate field plate onto the substrate does not overlap with the vertical projection of the second opening onto the substrate.

[0021] Alternatively, the vertical projection of the gate field plate onto the substrate at least partially overlaps with the vertical projection of the first opening onto the substrate, and the vertical projection of the gate field plate onto the substrate at least partially overlaps with the vertical projection of the second opening onto the substrate.

[0022] Optionally, the first passivation layer includes a third opening and a fourth opening, and the second passivation layer includes a fifth opening and a sixth opening;

[0023] The third opening is located on the side of the first opening away from the gate structure, the fourth opening is located on the side of the second opening away from the gate structure, the vertical projection of the fifth opening on the substrate coincides with the vertical projection of the third opening on the substrate, and the vertical projection of the sixth opening on the substrate coincides with the vertical projection of the fourth opening on the substrate.

[0024] The first electrode is located inside the third and fifth openings, and the second electrode is located inside the fourth and sixth openings.

[0025] Optionally, the gate structure includes a group III-V semiconductor layer and a gate;

[0026] The III-V semiconductor layer is located on the side of the barrier layer away from the substrate, and the gate is located on the side of the III-V semiconductor layer away from the substrate.

[0027] Optionally, the second sub-passivation layer includes a first silicon nitride layer, a first silicon oxide layer, and / or a first silicon oxynitride layer, and the fourth sub-passivation layer includes a second silicon nitride layer, a second silicon oxide layer, and / or a second silicon oxynitride layer.

[0028] In this embodiment of the invention, the first passivation layer can be located on the side of the gate structure away from the substrate. The first sub-passivation layer is thicker and has better electric field shielding capability, so that the first passivation layer composed of the first sub-passivation layer and the second sub-passivation layer has a better passivation protection effect on the gate structure, thereby reducing the leakage current of the gate structure. In addition, the first sub-passivation layer and the second sub-passivation layer cover the entire gate structure, which avoids the damage to the gate structure region by plasma such as oxygen or fluorine gas when electronegative atoms are doped on the surface of the barrier layer away from the substrate at the first opening and the second opening to form an electronegative atom doped layer. The first passivation layer may include a first opening and a second opening. The barrier layer exposed by the first and second openings is located away from the substrate surface. When electronegative atoms are doped to form an electronegative atom doped layer, since the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms (i.e., the doped electronegative atoms have strong oxidizing properties), the surface of the barrier layer is oxidized and the interface is improved during the doping process. This improves the surface states of the barrier layer in the drift region, increases the concentration of two-dimensional electron gas in the drift region, and thus enhances the performance of the power device. The second passivation layer is located on the side of the first passivation layer away from the substrate and fills the first and second openings. The second passivation layer, which is in direct contact with the barrier layer within the first and second openings, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device.

[0029] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0032] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0033] Figures 3-8 This is a schematic diagram of the structure corresponding to some steps in the method for fabricating a semiconductor device provided in this embodiment of the utility model;

[0034] Figure 9 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention;

[0035] Figures 10-11 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the present invention.

[0036] Figure 12 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this utility model, as shown below. Figure 1 As shown, the semiconductor device includes: a substrate 1, a channel layer 2 located on one side of the substrate 1, and a barrier layer 3 located on the side of the channel layer 2 away from the substrate 1. A gate structure 4 is located on the side of the barrier layer 3 away from the substrate 1. A first passivation layer 5 includes a first sub-passivation layer 51 and a second sub-passivation layer 52. The first sub-passivation layer 51 is located on the side of the gate structure 4 and the barrier layer 3 away from the substrate 1, and the second sub-passivation layer 52 is located on the side of the first sub-passivation layer 51 away from the substrate 1. The first passivation layer 5 includes a first opening 53 and a second opening 54, located on opposite sides of the gate structure 4, exposing the barrier layer 3. The side of the barrier layer 3 exposed by the first opening 53 and the second opening 54 away from the substrate 1 includes an electronegative atom doping layer, where the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of the oxygen atoms. The second passivation layer 6 includes a third sub-passivation layer 61 and a fourth sub-passivation layer 62. The third sub-passivation layer 61 is located on the side of the first passivation layer 5 away from the substrate 1, and fills the first opening 53 and the second opening 54. The fourth sub-passivation layer 62 is located on the side of the third sub-passivation layer 61 away from the substrate 1. A first electrode 71 is located on the side of the first opening 53 away from the gate structure 4. A second electrode 72 is located on the side of the second opening 54 away from the gate structure 4.

[0040] Specifically, substrate 1 can be a Si substrate, a sapphire substrate, or a GaN substrate. Channel layer 2 can be intrinsic GaN, and barrier layer 3 can be AlGaN. Gate structure 4 can be located in the middle region of the barrier layer 3 on the side away from substrate 1. Gate structure 4 can include a doped III-V semiconductor layer 41 and a gate 42. The doped III-V semiconductor layer 41 can be located in the middle region of the barrier layer 3 on the side away from substrate 1, and the gate 42 can be located in the middle region of the doped III-V semiconductor layer 41 on the side away from substrate 1. The doped III-V semiconductor layer 41 can include a P-GaN layer, and the gate 42 can include a titanium nitride metal layer.

[0041] The first passivation layer 5 may include a first sub-passivation layer 51 and a second sub-passivation layer 52. The first sub-passivation layer 51 may be located on the side of the gate structure 4 away from the substrate 1, and may also be located on a portion of the barrier layer 3 away from the substrate 1. The second sub-passivation layer 52 may be located on the side of the first sub-passivation layer 51 away from the substrate 1. The first passivation layer 5 may completely surround the gate structure 4, and is mainly used for passivation protection of the gate structure 4. The first sub-passivation layer 51 is thicker and has better electric field shielding ability, so that the first passivation layer 5 composed of the first sub-passivation layer 51 and the second sub-passivation layer 52 has a better passivation protection effect on the gate structure 4, thereby reducing the leakage current of the gate structure 4. In addition, the first sub-passivation layer 51 and the second sub-passivation layer 52 cover the entire gate structure 4, thus avoiding the damage to the gate structure 4 region by plasma such as oxygen or fluorine gas when electronegative atoms are doped onto the surface of the barrier layer 3 away from the substrate 1 at the first opening 53 and the second opening 54 to form an electronegative atom doped layer. The opening sizes of the first opening 53 and the second opening 54 can be the same, and the opening sizes of the first opening 53 and the second opening 54 can be set according to actual conditions. A certain distance can be set between the edges of the first opening 53 and the second opening 54 near the gate structure 4 and the gate structure 4. The distance between the edges of the first opening 53 and the second opening 54 near the gate structure 4 and the gate structure 4 can be set according to actual conditions to ensure that the first passivation layer 5 between the edges of the first opening 53 and the second opening 54 near the gate structure 4 and the gate structure 4 can completely surround the gate structure 4, effectively passivating and protecting the gate structure 4. The edge of the first opening 53 away from the gate structure 4 can be located between the first electrode 71 and the gate structure 4. The edge of the first opening 53 away from the gate structure 4 can also extend to the area of ​​the first electrode 71, and can also extend to the area of ​​the first electrode 71 away from the gate structure 4. The edge of the second opening 54 away from the gate structure 4 can be located between the second electrode 72 and the gate structure. The edge of the second opening 54 away from the gate structure 4 can also extend further. The edge of the second opening 54 away from the gate structure 4 can extend to the area of ​​the second electrode 72, and can also extend to the area of ​​the second electrode 72 away from the gate structure 4.

[0042] Experiments revealed that when electronegative atoms are doped onto the surface of the barrier layer 3 exposed by the first opening 53 and the second opening 54, away from the substrate 1, to form an electronegative atom doped layer, the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms, meaning these doped electronegative atoms have strong oxidizing properties. During the doping process of these electronegative atoms onto the surface of the barrier layer 3 to form the electronegative atom doped layer, the surface is oxidized and the interface is improved. This improves the surface states of the barrier layer 3 in the drift region, increases the concentration of two-dimensional electron gas in the drift region, and thus enhances the performance of the power device. The larger the opening size of the first opening 53 and the second opening 54, the better the effect on improving the concentration and mobility of the two-dimensional electron gas in the drift region.

[0043] The second passivation layer 6 may include a third sub-passivation layer 61 and a fourth sub-passivation layer 62. The third sub-passivation layer 61 may be located on the side of the second sub-passivation layer 52 away from the substrate 1, and the third sub-passivation layer 61 may fill the first opening 53 and the second opening 54, covering the barrier layer 3 exposed by the first opening 53 and the second opening 54. The fourth sub-passivation layer 62 may be located on the side of the third sub-passivation layer 61 away from the substrate 1. The thickness of the third sub-passivation layer 61 may be less than the thickness of the first sub-passivation layer 51. The second passivation layer 6, which is in direct contact with the barrier layer 3 in the first opening 53 and the second opening 54, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The larger the opening size of the first opening 53 and the second opening 54, the larger the contact area between the second passivation layer 6 and the barrier layer 3 will be, and the concentration and mobility of the two-dimensional electron gas of the GaN HEMT device can be further improved.

[0044] The GaN HEMT device provided in this embodiment of the present invention can have a completely symmetrical structure along the center line of the gate structure 4. The first electrode 71 can be used as the source or the drain, and the second electrode 72 can be used as the drain or the source.

[0045] In this embodiment of the present invention, the first passivation layer 5 can be located on the side of the gate structure 4 away from the substrate 1. The first sub-passivation layer 51 is thicker and has better electric field shielding ability, so that the first passivation layer 5 composed of the first sub-passivation layer 51 and the second sub-passivation layer 52 has a better passivation protection effect on the gate structure 4, thereby reducing the leakage current of the gate structure 4. In addition, the first sub-passivation layer 51 and the second sub-passivation layer 52 cover the entire gate structure 4, thus avoiding the damage to the gate structure 4 region by plasma such as oxygen or fluorine gas when electronegative atoms are doped on the surface of the barrier layer 3 away from the substrate 1 at the first opening 53 and the second opening 54 to form an electronegative atom doped layer. The first passivation layer 5 may include a first opening 53 and a second opening 54. When the surface of the barrier layer 3 exposed by the first opening 53 and the second opening 54 is doped with electronegative atoms to form an electronegative atom doped layer, since the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms (i.e., the doped electronegative atoms have strong oxidizing properties), the surface of the barrier layer 3 is oxidized and the interface is improved during the doping process. This improves the surface states of the barrier layer 3 in the drift region, increases the concentration of two-dimensional electron gas in the drift region, and thus enhances the performance of the power device. The second passivation layer 6 is located on the side of the first passivation layer 5 away from the substrate 1 and fills the first opening 53 and the second opening 54. The second passivation layer 6, which is in direct contact with the barrier layer 3 within the first opening 53 and the second opening 54, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The technical solution of this utility model embodiment can achieve separate modulation of the gate structure 4 and the device drift region through the first passivation layer 5 and the second passivation layer 6. While achieving a low leakage current of the gate structure 4, it can improve the concentration and mobility of the two-dimensional electron gas of the device, thereby effectively improving the device performance.

[0046] Optionally, based on the above embodiments, refer to... Figure 1 The thickness of the third sub-passivation layer 61 is less than the thickness of the first sub-passivation layer 51.

[0047] Specifically, the thicker first sub-passivation layer 51 provides better electric field shielding, resulting in better passivation protection of the gate structure 4 by the first passivation layer 51 and the second sub-passivation layer 52, thereby reducing leakage current in the gate structure 4. Furthermore, the first and second sub-passivation layers 51 and 52 cover the entire gate structure 4, preventing damage to the gate structure 4 region from plasmas such as oxygen or fluorine gas when electronegative atoms are doped onto the surface of the barrier layer 3 away from the substrate 1 at the first opening 53 and the second opening 54 to form an electronegative atom doped layer. The thickness of the third sub-passivation layer 61 can be less than that of the first sub-passivation layer 51, allowing the second passivation layer 6, which is in direct contact with the barrier layer 3 within the first opening 53 and the second opening 54, to effectively enhance the stress in the drift region of the GaN HEMT device. This increases the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reduces the on-resistance, and improves the dynamic performance of the GaN HEMT device.

[0048] In this embodiment of the invention, the thickness and other parameters of the first sub-passivation layer 51 and the third sub-passivation layer 61 are different, which is mainly achieved by adjusting the process temperature, gas ratio and pretreatment of the formation of the first sub-passivation layer 51 and the third sub-passivation layer 61.

[0049] Optionally, based on the above embodiments, refer to... Figure 1 The first sub-passivation layer 51 includes a first aluminum nitride layer, and the second sub-passivation layer 61 includes a second aluminum nitride layer.

[0050] Specifically, the materials of the first sub-passivation layer 51 and the third sub-passivation layer 61 can both be aluminum nitride. In some embodiments of this utility model, the materials of the first passivation layer 51 and the second passivation layer 61 can also be aluminum oxide, etc.

[0051] Optionally, based on the above embodiments, refer to... Figure 1 The materials of the second sub-passivation layer 52 and the fourth sub-passivation layer 62 can be set to at least one of silicon nitride, silicon oxide and silicon oxynitride.

[0052] Optionally, based on the above embodiments, refer to... Figure 1 Electronegative atom doping layers include oxygen atom doping layers and / or fluorine atom doping layers.

[0053] Specifically, in this embodiment of the GaN HEMT device, after forming the gate structure 4, a first passivation layer 5 is formed on the side of the gate structure 4 away from the substrate 1 and on the side of the barrier layer 3 away from the substrate 1. Then, the drift region of the GaN HEMT device is selectively opened through photolithography and etching processes, forming a first opening 53 and a second opening 54. Oxygen and / or fluorine gas are then introduced into the surface of the barrier layer 3 exposed by the first opening 53 and the second opening 54 to perform interface enhancement treatment on the surface of the barrier layer 3 exposed by the first opening 53 and the second opening 54. That is, the side of the barrier layer 3 exposed by the first opening 53 and the second opening 54 away from the substrate 1 is surface doped with electronegative atoms to form an electronegative atom doped layer. Since the electronegativity of electronegative atoms is relatively strong, it can improve the surface states of the barrier layer 3, increase the concentration and mobility of the two-dimensional electron gas in the drift region, and thus improve the performance of the device.

[0054] Optionally, based on the above embodiments, refer to... Figure 1 The gate structure 4 is located in the middle region of the barrier layer 3 on the side away from the substrate 1. The distance between the vertical projection of the first opening 53 onto the substrate 1 and the vertical projection of the gate structure 4 onto the substrate 1 is the same as the distance between the vertical projection of the second opening 54 onto the substrate 1 and the vertical projection of the gate structure 4 onto the substrate 1. The opening size of the first opening 53 is the same as the opening size of the second opening 54. The distance between the vertical projection of the first electrode 71 onto the substrate 1 and the vertical projection of the first opening 53 onto the substrate 1 is the same as the distance between the vertical projection of the second electrode 72 onto the substrate 1 and the vertical projection of the second opening 54 onto the substrate 1. Both the first electrode 71 and the second electrode 72 are in contact with the barrier layer 3.

[0055] Specifically, the distance between the centerline of the gate structure 4 and the centerline of the first opening 53 is the same as the distance between the centerline of the gate structure 4 and the centerline of the second opening 54. The gate structure 4 is located in the middle region of the barrier layer 3 away from the substrate 1, and the first opening 53 and the second opening 54 are symmetrically located on both sides of the gate structure 4. The distance between the centerline of the first electrode 71 and the centerline of the first opening 53 is also equal to the distance between the centerline of the second electrode 72 and the centerline of the second opening 54. This allows the GaN HEMT device to have a completely symmetrical structure along the centerline of the gate structure 4. The first electrode 71 can serve as either the source or the drain, and the second electrode 72 can serve as either the drain or the source.

[0056] The first passivation layer 5 may also have a third opening 55 and a fourth opening 56, and the second passivation layer 6 may also have a fifth opening 63 and a sixth opening 64. The third opening 55 may be located on the side of the first opening 53 away from the gate structure 4, and the vertical projection of the fifth opening 63 onto the substrate 1 may coincide with the vertical projection of the third opening 55 onto the substrate 1. The fourth opening 56 may be located on the side of the second opening 54 away from the gate structure 4, and the vertical projection of the sixth opening 64 onto the substrate 1 may coincide with the vertical projection of the fourth opening 56 onto the substrate 1. The first electrode 71 is located within the third opening 55 and the fifth opening 63 and is in contact with the barrier layer 3, and the second electrode 72 is located within the fourth opening 56 and the sixth opening 64 and is in contact with the barrier layer 3.

[0057] Optionally, based on the above embodiments, refer to... Figure 1 The thickness of the first sub-passivation layer 51 is 5nm-100nm, and the thickness of the third sub-passivation layer 61 is 0.5nm-5nm.

[0058] Specifically, the thickness of the third sub-passivation layer 61 can be less than the thickness of the first sub-passivation layer 51. For example, the thickness of the first sub-passivation layer 51 can be 5nm-100nm, and the thickness of the third sub-passivation layer 61 can be 0.5nm-5nm. By forming the first sub-passivation layer 51 and the third sub-passivation layer 61 separately and setting the thicknesses of the first sub-passivation layer 51 and the third sub-passivation layer 61 to be different, the first passivation layer 5 can effectively passivate and protect the gate structure 4, and the second passivation layer 6, which is in direct contact with the barrier layer 3 in the first opening 53 and the second opening 54, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby improving the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device.

[0059] Optionally, based on the above embodiments, refer to... Figure 1The semiconductor device may further include a gate field plate 8, which may be located on the side of the fourth sub-passivation layer 62 away from the substrate 1. The centerline of the gate field plate 8 may coincide with the centerline of the gate structure 4, and the vertical projection of the gate field plate 8 onto the substrate 1 may cover the vertical projection of the gate structure 4 onto the substrate 1. The vertical projection of the gate field plate 8 onto the substrate 1 may not overlap with the vertical projection of the first opening 53 onto the substrate 1. Alternatively, the gate field plate 8 may extend along the direction of the gate structure 4 pointing to the first opening 53, such that the vertical projection of the gate field plate 8 onto the substrate 1 may at least partially overlap with the vertical projection of the first opening 53 onto the substrate 1. The vertical projection of the gate field plate 8 onto the substrate 1 may not overlap with the vertical projection of the second opening 54 onto the substrate 1. Alternatively, the gate field plate 8 may extend along the direction of the gate structure 4 pointing to the second opening 54, such that the vertical projection of the gate field plate 8 onto the substrate 1 may at least partially overlap with the vertical projection of the second opening 54 onto the substrate 1. The gate field plate 8 can be made of metal. The gate field plate 8 can be used for electric field modulation to avoid electric field concentration between the gate structure 4 and the first electrode 71 or the second electrode 72, thereby improving the breakdown voltage of the device.

[0060] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 3-8 This is a schematic diagram of the structure corresponding to some steps in the method for fabricating a semiconductor device provided in this embodiment of the utility model, as shown below. Figure 2 As shown, the preparation method includes:

[0061] S100: Provides a substrate.

[0062] Specifically, such as Figure 3 As shown, a substrate 1 is first provided, which can be a Si substrate, a sapphire substrate or a GaN substrate.

[0063] S110: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0064] Specifically, such as Figure 4 As shown, a channel layer 2 is first formed on one side of the substrate 1, and a barrier layer 3 is formed on the side of the channel layer 2 away from the substrate 1. The channel layer 2 can be made of intrinsic GaN, and the barrier layer 3 can be made of AlGaN material.

[0065] S120: A gate structure is formed on the side of the barrier layer away from the substrate.

[0066] Specifically, such as Figure 5As shown, a gate structure 4 can be formed in the middle region of the barrier layer 3 on the side away from the substrate 1. The gate structure 4 may include a doped III-V semiconductor layer 41 and a gate 42. The doped III-V semiconductor layer 41 may be located in the middle region of the barrier layer 3 on the side away from the substrate 1, and the gate 42 may be located in the middle region of the doped III-V semiconductor layer 41 on the side away from the substrate 1. The doped III-V semiconductor layer 41 may include a P-GaN layer, and the gate 42 may include a titanium nitride metal layer.

[0067] S130: A first passivation layer is formed on the side of the gate structure and barrier layer away from the substrate. The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer. The first sub-passivation layer is located on the side of the gate structure and barrier layer away from the substrate, and the second sub-passivation layer is located on the side of the first sub-passivation layer away from the substrate.

[0068] Specifically, such as Figure 6 As shown, a first passivation layer 5 is formed on the side of the gate structure 4 and the barrier layer 3 away from the substrate 1. The first passivation layer 5 can be formed on the entire surface of the side of the gate structure 4 and the barrier layer 3 away from the substrate 1.

[0069] S140: Etch the first sub-passivation layer and the second sub-passivation layer on both sides of the gate structure to form a first opening and a second opening, the first opening and the second opening exposing the barrier layer.

[0070] Specifically, such as Figure 7 As shown, using a photomask, the drift region of the GaNHEMT device is selectively opened through photolithography and etching processes, forming the first opening 53 and the second opening 54. The first passivation layer 5 can completely surround the gate structure 4, and the first passivation layer 5 is mainly used to passivate and protect the gate structure 4. The first sub-passivation layer 51 is thicker and has stronger electric field shielding ability; thus, the first passivation layer 5, composed of the first sub-passivation layer 51 and the second sub-passivation layer 52, provides better passivation and protection for the gate structure 4, thereby reducing the leakage current of the gate structure 4.

[0071] S150: Electronegative atoms are doped onto the surface of the barrier layer exposed away from the substrate by plasma surface treatment process in the first and second openings. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0072] Specifically, such as Figure 7As shown, when electronegative atoms are doped onto the surfaces of the barrier layer 3 exposed away from the substrate 1 through the plasma surface treatment process of the first opening 53 and the second opening 54, the specific process involves placing the surfaces of the barrier layer 3 exposed away from the substrate 1 through the first opening 53 and the second opening 54 in a plasma atmosphere of oxygen and / or fluorine. In this process, because the entire device is placed in a plasma atmosphere, the function of the second sub-passivation layer 52 is to isolate the first sub-passivation layer 51 and the gate structure 4 from the plasma atmosphere, thereby preventing them from being damaged by the plasma. That is to say, without the second sub-passivation layer 52, the surface of the first sub-passivation layer 51 would be exposed to the plasma atmosphere, and the effect of reducing gate leakage current would not be achieved. The second sub-passivation layer 52 is used to protect the first sub-passivation layer 51 and the gate structure, specifically, to prevent adverse effects when electronegative atoms are doped onto the surfaces of the barrier layer 3 exposed away from the substrate 1 through the first opening 53 and the second opening 54.

[0073] S160: A second passivation layer is formed on the side of the first passivation layer away from the substrate, inside the first opening and the second opening. The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer. The third sub-passivation layer is located on the side of the first passivation layer away from the substrate, and the third sub-passivation layer fills the first opening and the second opening. The fourth sub-passivation layer is located on the side of the third sub-passivation layer away from the substrate.

[0074] Specifically, such as Figure 8 As shown, a second passivation layer 6 is formed on the side of the first passivation layer 5 away from the substrate 1, within the first opening 53 and the second opening 54. The thickness of the third sub-passivation layer 61 can be less than the thickness of the first sub-passivation layer 51. The second passivation layer 6, which is in direct contact with the barrier layer 3 within the first opening 53 and the second opening 54, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The larger the opening size of the first opening 53 and the second opening 54, the larger the contact area between the second passivation layer 6 and the barrier layer 3, and the higher the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device can be.

[0075] S170: A first electrode is formed on the side of the first opening away from the gate structure.

[0076] Specifically, such as Figure 1 As shown, the first passivation layer 5 may also have a third opening 55, and the second passivation layer 6 may also have a fifth opening 63. The third opening 55 may be located on the side of the first opening 53 away from the gate structure 4, and the vertical projection of the fifth opening 63 onto the substrate 1 may coincide with the vertical projection of the third opening 55 onto the substrate 1. The first electrode 71 is located within the third opening 55 and the fifth opening 63 and is in contact with the barrier layer 3.

[0077] S180: A second electrode is formed on the side of the second opening away from the gate structure.

[0078] Specifically, such as Figure 1 As shown, the first passivation layer 5 may also have a fourth opening 56, and the second passivation layer 6 may also have a sixth opening 64. The fourth opening 56 may be located on the side of the second opening 54 away from the gate structure 4, and the vertical projection of the sixth opening 64 onto the substrate 1 may coincide with the vertical projection of the fourth opening 56 onto the substrate 1. The second electrode 72 is located within the fourth opening 56 and the sixth opening 64 and is in contact with the barrier layer 3.

[0079] Optionally, based on the above embodiments, Figure 9 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention. Figures 10-11 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided by this utility model embodiment, as shown below. Figure 8 As shown, the preparation method includes:

[0080] S200: Provides a substrate.

[0081] S210: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0082] S220: A gate structure is formed on the side of the barrier layer away from the substrate.

[0083] S230: A first sub-passivation layer is formed on the entire surface of the gate structure on the side away from the substrate and the barrier layer on the side away from the substrate.

[0084] Specifically, such as Figure 10 As shown, a first sub-passivation layer 51 is formed on the entire surface of the gate structure 4 on the side away from the substrate 1 and the barrier layer 3 on the side away from the substrate 1. For example, the material of the first sub-passivation layer 51 can be aluminum nitride or aluminum oxide, etc.

[0085] S240: A second sub-passivation layer is formed on the side of the first sub-passivation layer away from the substrate.

[0086] Specifically, such as Figure 6 As shown, a second sub-passivation layer 52 is formed on the side of the first sub-passivation layer 51 away from the substrate 1. For example, the material of the second sub-passivation layer 52 can be silicon nitride or silicon oxide, etc.

[0087] S250: The first sub-passivation layer and the second sub-passivation layer on both sides of the gate structure are etched to form a first opening and a second opening, and the first opening and the second opening expose the barrier layer.

[0088] S260: Electronegative atoms are doped onto the surface of the barrier layer exposed away from the substrate by plasma surface treatment process in the first and second openings. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0089] S270: A third sub-passivation layer is formed on the side of the second sub-passivation layer away from the substrate, and within the first and second openings.

[0090] Specifically, such as Figure 11 As shown, a third sub-passivation layer 61 is formed on the side of the second sub-passivation layer 52 away from the substrate 1, and the third sub-passivation layer 61 is formed in the first opening and the second opening. For example, the material of the third sub-passivation layer 61 may include aluminum nitride or aluminum oxide, etc.

[0091] S280: A fourth sub-passivation layer is formed on the side of the third sub-passivation layer away from the substrate.

[0092] Specifically, such as Figure 8 As shown, a fourth sub-passivation layer 62 is formed on the side of the third sub-passivation layer 61 away from the substrate 1. For example, the material of the fourth sub-passivation layer 62 may include silicon nitride or silicon oxide, etc.

[0093] S290: A first electrode is formed on the side of the first opening away from the gate structure.

[0094] S291: A second electrode is formed on the side of the second opening away from the gate structure.

[0095] Optionally, based on the above embodiments, Figure 12 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention, such as... Figure 12 As shown, the preparation method includes:

[0096] S300: Provides a substrate.

[0097] S310: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0098] S320: A gate structure is formed on the side of the barrier layer away from the substrate.

[0099] S330: A first passivation layer is formed on the side of the gate structure and barrier layer away from the substrate. The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer. The first sub-passivation layer is located on the side of the gate structure and barrier layer away from the substrate, and the second sub-passivation layer is located on the side of the first sub-passivation layer away from the substrate.

[0100] S340: Etch the first sub-passivation layer and the second sub-passivation layer on both sides of the gate structure to form a first opening and a second opening, the first opening and the second opening exposing the barrier layer.

[0101] S350: Electronegative atoms are doped onto the surface of the barrier layer exposed away from the substrate through a plasma surface treatment process. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0102] S360: A second passivation layer is formed on the side of the first passivation layer away from the substrate, inside the first opening and the second opening. The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer. The third sub-passivation layer is located on the side of the first passivation layer away from the substrate, and the third sub-passivation layer fills the first opening and the second opening. The fourth sub-passivation layer is located on the side of the third sub-passivation layer away from the substrate.

[0103] S370: Etching the second passivation layer on the side of the first opening away from the gate structure forms the fifth opening.

[0104] Specifically, such as Figure 1 As shown, a fifth opening 63 is formed on a second passivation layer 6 on the side of the first opening 53 away from the gate structure 4 through processes such as photolithography and etching.

[0105] S380: The first passivation layer corresponding to the fifth opening is etched to form the third opening; the vertical projection of the third opening onto the substrate coincides with the vertical projection of the fifth opening onto the substrate.

[0106] Specifically, such as Figure 1 As shown, a third opening 55 is formed on the first passivation layer 5 in the region corresponding to the fifth opening 63 through photolithography and etching processes.

[0107] S390: The first electrode is formed in the third and fifth openings.

[0108] Specifically, such as Figure 1 As shown, a first electrode 71 is formed within the third opening 55 and the fifth opening 63. For example, the first electrode 71 can be a metal electrode.

[0109] S391: Etching the second passivation layer on the side of the second opening away from the gate structure forms the sixth opening.

[0110] Specifically, such as Figure 1 As shown, a sixth opening 64 is formed on the second passivation layer 6 on the side of the second opening 54 away from the gate structure 4 through processes such as photolithography and etching.

[0111] S392: The first passivation layer corresponding to the sixth opening is etched to form the fourth opening; the vertical projection of the fourth opening onto the substrate coincides with the vertical projection of the sixth opening onto the substrate.

[0112] Specifically, such as Figure 1 As shown, a fourth opening 56 is formed on the first passivation layer 5 in the region corresponding to the sixth opening 64 through photolithography and etching processes.

[0113] S393: The first electrode is formed in the fourth and sixth openings.

[0114] Specifically, such as Figure 1 As shown, a second electrode 72 is formed within the fourth opening 56 and the sixth opening 64. For example, the second electrode 72 can be a metal electrode.

[0115] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0116] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A channel layer, wherein the channel layer is located on one side of the substrate; A barrier layer, the barrier layer being located on the side of the channel layer away from the substrate; A gate structure, wherein the gate structure is located on the side of the barrier layer away from the substrate; A first passivation layer, comprising a first sub-passivation layer and a second sub-passivation layer; the first sub-passivation layer is located on the side of the gate structure and the barrier layer away from the substrate, and the second sub-passivation layer is located on the side of the first sub-passivation layer away from the substrate; the first passivation layer comprises a first opening and a second opening, the first opening and the second opening being located on opposite sides of the gate structure, the first opening and the second opening exposing the barrier layer; the side of the barrier layer exposed by the first opening and the second opening away from the substrate comprises an electronegative atom doped layer, wherein the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of oxygen atoms; A second passivation layer, comprising a third sub-passivation layer and a fourth sub-passivation layer; the third sub-passivation layer is located on the side of the first passivation layer away from the substrate, and the third sub-passivation layer fills the first opening and the second opening; the fourth sub-passivation layer is located on the side of the third sub-passivation layer away from the substrate. A gate field plate is located on the side of the second passivation layer away from the substrate, and the vertical projection of the gate field plate on the substrate covers the vertical projection of the gate structure on the substrate. A first electrode is located on the side of the first opening away from the gate structure; The second electrode is located on the side of the second opening away from the gate structure.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the third sub-passivation layer is less than the thickness of the first sub-passivation layer.

3. The semiconductor device according to claim 2, characterized in that, The thickness of the first sub-passivation layer is 5nm-100nm, and the thickness of the third sub-passivation layer is 0.5nm-5nm.

4. The semiconductor device according to claim 1, characterized in that, The first sub-passivation layer includes a first aluminum nitride layer, and the second sub-passivation layer includes a second aluminum nitride layer.

5. The semiconductor device according to claim 1, characterized in that, The electronegative atom doped layer includes an oxygen atom doped layer and / or a fluorine atom doped layer.

6. The semiconductor device according to claim 1, characterized in that, The gate structure is located in the middle region of the barrier layer on the side away from the substrate, and the center line of the gate field plate coincides with the center line of the gate structure; the distance between the vertical projection of the first opening on the substrate and the vertical projection of the gate structure on the substrate is the same as the distance between the vertical projection of the second opening on the substrate and the vertical projection of the gate structure on the substrate. The opening size of the first opening is the same as the opening size of the second opening; The distance between the vertical projection of the first electrode on the substrate and the vertical projection of the first opening on the substrate is the same as the distance between the vertical projection of the second electrode on the substrate and the vertical projection of the second opening on the substrate; both the first electrode and the second electrode are in contact with the barrier layer.

7. The semiconductor device according to claim 1, characterized in that, The vertical projection of the gate field plate onto the substrate does not overlap with the vertical projection of the first opening onto the substrate, and the vertical projection of the gate field plate onto the substrate does not overlap with the vertical projection of the second opening onto the substrate. Alternatively, the vertical projection of the gate field plate onto the substrate at least partially overlaps with the vertical projection of the first opening onto the substrate, and the vertical projection of the gate field plate onto the substrate at least partially overlaps with the vertical projection of the second opening onto the substrate.

8. The semiconductor device according to claim 1, characterized in that, The first passivation layer includes a third opening and a fourth opening, and the second passivation layer includes a fifth opening and a sixth opening; The third opening is located on the side of the first opening away from the gate structure, the fourth opening is located on the side of the second opening away from the gate structure, the vertical projection of the fifth opening on the substrate coincides with the vertical projection of the third opening on the substrate, and the vertical projection of the sixth opening on the substrate coincides with the vertical projection of the fourth opening on the substrate. The first electrode is located within the third and fifth openings, and the second electrode is located within the fourth and sixth openings.

9. The semiconductor device according to claim 1, characterized in that, The gate structure includes a group III-V semiconductor layer and a gate; The III-V semiconductor layer is located on the side of the barrier layer away from the substrate, and the gate is located on the side of the III-V semiconductor layer away from the substrate.

10. The semiconductor device according to claim 1, characterized in that, The second sub-passivation layer includes a first silicon nitride layer, a first silicon oxide layer, and / or a first silicon oxynitride layer, and the fourth sub-passivation layer includes a second silicon nitride layer, a second silicon oxide layer, and / or a second silicon oxynitride layer.

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