Packaging structure of superconducting quantum chip and electronic device

Abstract

The application provides a packaging structure of a superconducting quantum chip and electronic equipment, and relates to the technical field of superconducting quantum technology. A back electromagnetic shielding layer is formed on the superconducting quantum chip away from one side of a functional circuit area, so as to form an electromagnetic shielding structure for the functional circuit on the superconducting quantum chip, and the electromagnetic shielding function of the superconducting quantum chip is realized. In addition, a sealed cavity wrapping the functional circuit area is further formed among the superconducting quantum chip, the sealing ring and the control chip. Not only is the welding interval control between the superconducting quantum chip and the control chip realized through the sealing ring, but also the airtight packaging of the superconducting quantum chip is realized, so that the oxidation and chemical corrosion of the superconducting material of the superconducting quantum chip in a low-temperature environment can be prevented, the long-term stability of the superconducting quantum chip in a dilution refrigerator is improved, the low-temperature performance of the superconducting quantum chip is improved, and the performance and reliability of the superconducting quantum chip are improved.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum technology, and more specifically, to a packaging structure and electronic device for a superconducting quantum chip. Background Technology

[0002] The coherence and gate fidelity of qubits in superconducting quantum chips are highly sensitive to electromagnetic interference (EMI). Therefore, achieving effective electromagnetic shielding is crucial for the performance and reliability of superconducting qubits. Traditional packaging methods for superconducting quantum chips typically use encapsulation boxes and external magnetic shielding barrels from dilution coolers for EMI shielding. While this can reduce external interference to some extent, it cannot effectively shield against EMI within the chip device itself. Utility Model Content

[0003] In view of this, this application provides a packaging structure and electronic device for a superconducting quantum chip, which effectively solves the existing technical problems. It not only realizes the electromagnetic shielding function of the superconducting quantum chip, but also realizes the welding interval control between the superconducting quantum chip and the control chip, and realizes the hermetic packaging of the superconducting quantum chip, thereby improving the performance and reliability of the superconducting quantum chip.

[0004] To achieve the above objectives, the technical solution provided in this application is as follows:

[0005] A packaging structure for a superconducting quantum chip, comprising:

[0006] A superconducting quantum chip, wherein one side surface of the superconducting quantum chip includes a functional circuit region and an edge sealing region surrounding the functional circuit region;

[0007] A control chip is welded and fixed to the superconducting quantum chip.

[0008] A back electromagnetic shielding layer is located on the surface of the superconducting quantum chip that is away from the control chip.

[0009] A sealing ring is located between the superconducting quantum chip and the control chip. The sealing ring is located on the edge sealing area and surrounds the functional circuit area. A sealing cavity is formed between the superconducting quantum chip, the sealing ring, and the control chip. The solder joints at the functional circuit area are welded and fixed to the corresponding solder joints of the control chip and are located within the sealing cavity.

[0010] Optionally, the sealing ring is an electromagnetic shielding sealing ring;

[0011] The packaging structure further includes an electromagnetic shielding connection portion located in the edge sealing area and penetrating the superconducting quantum chip, wherein the electromagnetic shielding sealing ring and the back electromagnetic shielding layer are connected through the electromagnetic shielding connection portion.

[0012] Optionally, the electromagnetic shielding connection includes a plurality of electromagnetic shielding connection posts, which are distributed around the functional circuit area.

[0013] Optionally, the electromagnetic shielding connection includes at least one electromagnetic shielding connection ring, which surrounds the functional circuit area.

[0014] Optionally, an insulating layer may be further included between the sidewall of the electromagnetic shielding connection and the superconducting quantum chip.

[0015] Optionally, the thickness of the back electromagnetic shielding layer ranges from 5 to 10 micrometers.

[0016] Optionally, in the direction from the superconducting quantum chip to the control chip, the thickness of the sealing ring ranges from 5 to 10 micrometers.

[0017] Optionally, the solder joints in the functional circuit area are soldered to the corresponding solder joints of the control chip to form indium solder pillars.

[0018] Optionally, the sealing cavity is used to fill an inert gas, or the sealing cavity is a vacuum sealing cavity.

[0019] Based on the same inventive concept, this application also provides an electronic device, which includes the above-described packaging structure of the superconducting quantum chip.

[0020] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:

[0021] This application provides a packaging structure for a superconducting quantum chip and an electronic device. The packaging structure includes: a superconducting quantum chip, one side surface of which includes a functional circuit region and an edge sealing region surrounding the functional circuit region; a control chip, which is welded and fixed to the superconducting quantum chip; a back electromagnetic shielding layer, which is located on the side surface of the superconducting quantum chip opposite to the control chip; and a sealing ring, which is located between the superconducting quantum chip and the control chip, and is located on the edge sealing region and surrounds the functional circuit region. A sealed cavity is formed between the superconducting quantum chip, the sealing ring, and the control chip. The solder joints at the functional circuit region are welded and fixed to the corresponding solder joints of the control chip and are located within the sealed cavity.

[0022] As described above, the technical solution provided in this application forms a back electromagnetic shielding layer on the superconducting quantum chip, away from the functional circuit region, thereby creating an electromagnetic shielding structure for the functional circuits and achieving the electromagnetic shielding function of the superconducting quantum chip. Furthermore, a sealed cavity encapsulating the functional circuit region is formed between the superconducting quantum chip, the sealing ring, and the control chip. This not only controls the welding spacing between the superconducting quantum chip and the control chip through the sealing ring but also achieves hermetic encapsulation of the superconducting quantum chip. This prevents oxidation and chemical corrosion of the superconducting material in the superconducting quantum chip at low temperatures, improves the long-term stability of the superconducting quantum chip in the dilution refrigerator, enhances the low-temperature performance of the superconducting quantum chip, and improves its overall performance and reliability. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a packaging method for a superconducting quantum chip provided in this application embodiment;

[0025] Figure 2 A schematic diagram of the packaging structure of a superconducting quantum chip provided in this application embodiment;

[0026] Figure 3 A flowchart illustrating another packaging method for a superconducting quantum chip provided in this application embodiment;

[0027] Figure 4 A schematic diagram of the packaging structure of another superconducting quantum chip provided in this application embodiment;

[0028] Figure 5 A schematic diagram of the packaging structure of another superconducting quantum chip provided in this application embodiment;

[0029] Figure 6 A schematic diagram of the packaging structure of another superconducting quantum chip provided in this application embodiment;

[0030] Figures 7 to 15 for Figure 6 A schematic diagram of the corresponding structure of the middle part of the steps;

[0031] Figure 16 A layout diagram of a connection hole provided in an embodiment of this application;

[0032] Figure 17 A layout diagram of another connection hole provided in an embodiment of this application;

[0033] Figure 18 This is a schematic diagram of the structure of an electromagnetic shielding connection provided in an embodiment of this application;

[0034] Figure 19 This is a schematic diagram of another electromagnetic shielding connection provided in an embodiment of this application;

[0035] Figure 20 This is a schematic diagram of the structure of another superconducting quantum chip provided in the embodiments of this application.

[0036] Figure label:

[0037] 100-Superconducting quantum chip; 200-Control chip; 210-Shielding part; 310-Sealing ring, electromagnetic shielding sealing ring; 320-Electromagnetic shielding connection part; 3201-Electromagnetic shielding connecting post; 3202-Electromagnetic shielding connecting ring; 330-Back electromagnetic shielding layer; 400-Sealing cavity; 500-Welding post; 610-First protective film layer; 620-First mask layer; 630-Second protective film layer; 640-Second mask layer; 700-Connecting hole; 710-Columnar hole; 720-Annular hole; 800-Insulating layer; A1-Functional circuit area; A2-Edge sealing area. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] As described in the background section, the coherence and gate fidelity of qubits in superconducting quantum chips are highly sensitive to electromagnetic interference (EMI). Therefore, achieving effective electromagnetic shielding is crucial for the performance and reliability of superconducting qubits. Traditional packaging methods for superconducting quantum chips typically use packaging boxes and external magnetic shielding barrels from dilution coolers for EMI shielding. While this can reduce external interference to some extent, it cannot effectively shield against EMI within the chip device itself.

[0040] Based on this, the embodiments of this application provide a packaging method, packaging structure and electronic device for a superconducting quantum chip, which effectively solves the existing technical problems. It not only realizes the electromagnetic shielding function of the superconducting quantum chip, but also realizes the welding interval control between the superconducting quantum chip and the control chip, and realizes the hermetic packaging of the superconducting quantum chip, thereby improving the performance and reliability of the superconducting quantum chip.

[0041] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 20 The technical solutions provided in the embodiments of this application will be described in detail.

[0042] Combination Figure 1 and Figure 2 As shown, Figure 1 A flowchart illustrating a packaging method for a superconducting quantum chip provided in this application embodiment. Figure 2 This is a schematic diagram of a packaging structure for a superconducting quantum chip provided in an embodiment of this application. The packaging method for the superconducting quantum chip provided in this embodiment includes:

[0043] S1. A superconducting quantum chip 100 and a control chip 200 are provided. One surface of the superconducting quantum chip 100 includes a functional circuit region A1 and an edge sealing region A2 surrounding the functional circuit region A1. That is, after the superconducting quantum chip 100 and the control chip 200 are soldered together, the surface of the superconducting quantum chip 100 facing the control chip 200 includes the functional circuit region A1 and the edge sealing region A2.

[0044] S2. A back electromagnetic shielding layer 330 is formed on the surface of the superconducting quantum chip 100 on the side opposite to the functional circuit region A1, and a sealing ring 310 is formed on the edge sealing region A2 surrounding the functional circuit region A1.

[0045] S3. The superconducting quantum chip 100 and the control chip 200 are welded and fixed relative to each other, forming a sealed cavity 400 between the superconducting quantum chip 100, the sealing ring 310, and the control chip 200. The welding of the superconducting quantum chip 100 and the control chip 200 involves welding and fixing the solder joint at the functional circuit area A1 of the superconducting quantum chip 100 to the corresponding solder joint of the control chip 200, and placing them within the sealed cavity 400. Figure 2The welding post 500 illustrates the welding relationship between the solder joint at functional circuit area A1 and the solder joint of control chip 200. The welding post 500 is located within the sealed cavity 400. In some embodiments, the solder joints of the superconducting quantum chip 100 (i.e., the solder joint at functional circuit area A1) and the solder joint of control chip 200 provided in this application embodiment can be a welding area used only to illustrate the welding connection. When welding the solder joint at functional circuit area A1 and the solder joint of control chip 200, solder can be placed at the solder joint at functional circuit area A1, or solder can be placed at the solder joint of control chip 200, or solder can be placed at both the solder joint at functional circuit area A1 and the solder joint of control chip 200. Then, the solder joint at functional circuit area A1 and the solder joint of control chip 200 are aligned and welded to form the welding post 500. Alternatively, the solder joints at functional circuit area A1 and the solder joints at the control chip 200 can not only serve as a schematic soldering area, but also be substantially provided with solder. During soldering, the solder joints at functional circuit area A1 and the solder joints at the control chip 200 can be directly soldered to form a solder pillar 500. This application does not impose specific limitations on this. Optionally, the solder used for bonding can be In (indium). In is soft and can reduce damage to the chip during soldering. That is, the solder joints at functional circuit area A1 and the corresponding solder joints at the control chip 200 provided in this embodiment of the application are soldered to form indium solder pillars.

[0046] Understandably, the technical solution provided in this application forms a back electromagnetic shielding layer 330 on the superconducting quantum chip 100, facing away from the functional circuit region A1, to form an electromagnetic shielding structure for the functional circuit on the superconducting quantum chip 100, thus realizing the electromagnetic shielding function of the superconducting quantum chip 100. Furthermore, a sealed cavity 400 encapsulating the functional circuit region A1 is formed between the superconducting quantum chip 100, the sealing ring 310, and the control chip 200. This not only controls the welding spacing between the superconducting quantum chip 100 and the control chip 200 through the sealing ring 310, but also achieves hermetic encapsulation of the superconducting quantum chip 100. This prevents oxidation and chemical corrosion of the superconducting material of the superconducting quantum chip 100 in low-temperature environments, improves the long-term stability of the superconducting quantum chip 100 in the dilution refrigerator, enhances the low-temperature performance of the superconducting quantum chip 100, and improves the performance and reliability of the superconducting quantum chip 100.

[0047] Combination Figure 3 and Figure 4 As shown, Figure 3 A flowchart illustrating another packaging method for a superconducting quantum chip provided in this application embodiment. Figure 4This is a schematic diagram of another packaging structure for a superconducting quantum chip provided in this application embodiment. Wherein, when the sealing ring 310 is an electromagnetic shielding sealing ring 310 made of electromagnetic shielding material, step S2 provided in this application embodiment, which involves forming a back electromagnetic shielding layer 330 on the surface of the superconducting quantum chip 100 opposite to the functional circuit region A1, and forming a sealing ring 310 surrounding the functional circuit region A1 on the edge sealing region A2, includes:

[0048] S21. A back electromagnetic shielding layer 330 is formed on the surface of the superconducting quantum chip 100 on the side away from the functional circuit region A1, that is, a back electromagnetic shielding layer 330 is formed on the side of the superconducting quantum chip 100 away from the sealing ring 310.

[0049] S22, An electromagnetic shielding connection portion 320 is formed in the edge sealing region A2, penetrating the superconducting quantum chip 100.

[0050] S23. An electromagnetic shielding sealing ring 310 is formed on the edge sealing area A2, surrounding the functional circuit area A1. The electromagnetic shielding sealing ring 310 and the back electromagnetic shielding layer 330 are connected through the electromagnetic shielding connection part 320. When the sealing ring 310 is an electromagnetic shielding sealing ring 310, the welding of the superconducting quantum chip 100 and the control chip 200 involves welding and fixing the solder joints at the functional circuit area A1 of the superconducting quantum chip 100 to the corresponding solder joints of the control chip 200, placing them within the sealing cavity 400, and welding and fixing the electromagnetic shielding sealing ring 310 and the shielding part 210 of the control chip 200. Figure 4 The welding pillar 500 illustrates the welding relationship between the solder joint at functional circuit area A1 and the solder joint of the control chip 200. The welding pillar 500 is located within the sealed cavity 400, and the shielding portion 210 of the control chip 200 includes at least a portion of the ground electrode facing the superconducting quantum chip 100. This portion of the ground electrode is welded and fixed to the electromagnetic shielding sealing ring 310. Thus, a back electromagnetic shielding layer 330 and an electromagnetic shielding sealing ring 310 are formed around the superconducting quantum chip 100. The back electromagnetic shielding layer 330 and the electromagnetic shielding sealing ring 310 are connected by an electromagnetic shielding connection portion 320 penetrating the superconducting quantum chip 100, thereby forming an electromagnetic shielding structure around the functional circuit of the superconducting quantum chip 100, further improving the electromagnetic shielding function of the packaged superconducting quantum chip 100.

[0051] It should be noted that the electromagnetic shielding sealing ring 310, electromagnetic shielding connection 320, and back electromagnetic shielding layer 330 provided in this application embodiment are all made of electromagnetic shielding material, specifically superconducting material, metal material, or alloy material. The material type needs to be selected according to the actual application, and this application does not impose specific limitations. For ease of description of the technical solutions provided in this application embodiment, the materials of the electromagnetic shielding sealing ring 310, electromagnetic shielding connection 320, and back electromagnetic shielding layer 330 will be described below using indium as an example. Furthermore, some of the process parameter values ​​described below are only specific values ​​listed for ease of understanding, and this application does not impose specific limitations on them.

[0052] In some embodiments, the electromagnetic shielding connection portion 320 and the electromagnetic shielding sealing ring 310 provided in this application can be fabricated based on masking and other related processes. For example... Figure 5 The diagram shows a flowchart of another packaging method for a superconducting quantum chip provided in this application embodiment. In step S22 of this application embodiment, forming an electromagnetic shielding connection portion 320 penetrating the superconducting quantum chip 100 in the edge sealing region A2 includes:

[0053] S221. A first protective film is formed on the side of the back electromagnetic shielding layer 330 away from the superconducting quantum chip 100.

[0054] S222, A first mask layer is formed on the side of the superconducting quantum chip 100 away from the back electromagnetic shielding layer 330.

[0055] S223. The superconducting quantum chip 100 is etched based on the first mask layer to form a connection hole through the superconducting quantum chip 100 at the edge sealing area A2.

[0056] S224. An electromagnetic shielding connection portion 320 is deposited in the connection hole, and the electromagnetic shielding connection portion 320 is in contact with the back electromagnetic shielding layer 330.

[0057] S225. Remove the first protective film layer and the first mask layer.

[0058] like Figure 6 The diagram shows a flowchart of another packaging method for a superconducting quantum chip provided in this application embodiment. In step S23 of this application embodiment, forming an electromagnetic shielding sealing ring 310 surrounding the functional circuit region A1 on the edge sealing region A2 includes:

[0059] S231. A second protective film is formed on the side of the back electromagnetic shielding layer 330 away from the superconducting quantum chip 100.

[0060] S232, A second mask layer is formed on the side of the superconducting quantum chip 100 away from the back electromagnetic shielding layer 330.

[0061] S233. Based on the second mask layer depositing the electromagnetic shielding sealing ring 310 on the edge sealing area A2, the electromagnetic shielding sealing ring 310 is in contact with the electromagnetic shielding connection portion 320.

[0062] S234. Remove the second protective film layer and the second mask layer.

[0063] The following is in conjunction with the appendix Figures 7 to 15 The technical solutions provided in the embodiments of this application will be described in more detail. Figures 7 to 15 for Figure 6 A schematic diagram of the corresponding structure for some of the steps.

[0064] like Figure 7 As shown, corresponding to step S21, a back electromagnetic shielding layer 330 is formed on the surface of the superconducting quantum chip 100 on the side opposite to the functional circuit region A1, serving as a grounding reference plane for electromagnetic shielding. Taking indium as the material of the back electromagnetic shielding layer 330, the superconducting quantum chip 100 first needs to be pre-treated. Ion cleaning is used to remove surface oxides from the superconducting quantum chip 100. For example, Ar ions with an ion energy of 200 eV and a cleaning time of 5 min can be used to clean the superconducting quantum chip 100, while maintaining a vacuum level of ≤10. -6 Torr is used to avoid oxidation contamination. Then, an indium film evaporation process is used to form a back electromagnetic shielding layer 330 on the surface of the superconducting quantum chip 100 on the side opposite to the functional circuit region A1. The evaporation process parameters include a substrate heating temperature of 120°C, a deposition rate of 0.5 nm / s, and a thickness of 5-10 micrometers. Optionally, in this embodiment, a planetary rotating substrate stage can be used to deposit the back electromagnetic shielding layer 330, thereby improving the uniformity of the back electromagnetic shielding layer 330, such as a film uniformity requirement of ±3%.

[0065] like Figure 8 As shown, corresponding to step 221, a first protective film layer 610 is formed on the side of the back electromagnetic shielding layer 330 away from the superconducting quantum chip 100. The first protective film layer 610 can be a photoresist layer, and this application does not impose specific restrictions on it.

[0066] like Figure 9As shown, corresponding to step S222, a first mask layer 620 is formed on the side of the superconducting quantum chip 100 away from the back electromagnetic shielding layer 330. The first mask layer 620 can be formed using photolithography, wherein the photoresist can be a positive photoresist, such as AZ4620 photoresist, and this application does not impose specific limitations on this. First, a photoresist layer is spin-coated on the side of the superconducting quantum chip 100 away from the back electromagnetic shielding layer 330. The spin-coating speed can be 3000 rpm, and the spin-coating thickness can be 15 micrometers. Then, the photoresist layer is exposed. Specifically, the photoresist layer can be exposed based on a mask including an array of circular holes (the diameter of the holes can be 40 micrometers, and the spacing between the holes can be 200 micrometers) or including a ring. The exposure equipment can be an i-line lithography machine with a wavelength of 365 nm and an exposure dose of 180 mJ / cm². 2 Finally, the photoresist layer is developed using a 1:4 solution of AZ400K developer and DI water (deionized water) for 60 seconds to remove the exposed areas from the photoresist layer. The first mask layer 620 includes a cutout portion corresponding to the edge sealing area A2. The cutout portion may include multiple cutout holes distributed around the functional line area A1, or the cutout portion may be at least one cutout ring surrounding the functional line area A1.

[0067] like Figure 10 As shown, corresponding to step S223, the superconducting quantum chip 100 is etched based on the first mask layer 620 to form a through-hole 700 at the edge sealing area A2, thereby opening up the superconducting quantum chip 100 and providing a channel for the electromagnetic shielding connection part 320. The through-hole 700 can be formed by etching the superconducting quantum chip 100 using a low-temperature ICP (Inductively Coupled Plasma) etching process. A low-temperature ICP etching machine is used, and the etching gas can be selected based on the Bosch process, alternating between SF6 and C4F8, with a process temperature of -150°C to etch the superconducting quantum chip 100. The process parameters are: aspect ratio 10:1, aperture 40 micrometers, depth 400 micrometers, and sidewall roughness ≤0.3 nmRMS.

[0068] In some embodiments, the connection hole 700 provided in this application may include a plurality of holes distributed around the functional circuit area A1. For example... Figure 16The diagram shows a layout of a connection hole according to an embodiment of this application. The connection hole 700 includes a plurality of columnar holes 710 distributed around the functional circuit region A1. The diameter of the columnar holes 710 can be 40 micrometers, and the spacing between adjacent columnar holes 710 can be 200 micrometers. That is, forming a connection hole 700 penetrating the superconducting quantum chip 100 at the edge sealing region A2 includes: forming a plurality of columnar holes 710 penetrating the superconducting quantum chip 100 at the edge sealing region A2, wherein the plurality of columnar holes 710 are distributed around the functional circuit region A1, and the electromagnetic shielding connection portion 320 includes electromagnetic shielding connection pillars 3201 deposited in the columnar holes 710.

[0069] Alternatively, the connection hole 700 provided in this application embodiment may include at least one hole surrounding the functional circuit area A1. For example... Figure 17 The diagram shows another layout of a connection hole provided in an embodiment of this application. The connection hole 700 includes at least one annular hole 720 surrounding the functional circuit area A1. That is, at least one annular hole 720 is formed at the edge sealing area A2, penetrating the superconducting quantum chip 100, and the annular hole 720 surrounds the functional circuit area. The electromagnetic shielding connection portion 320 includes an electromagnetic shielding connection ring 3202 deposited in the annular hole 720.

[0070] like Figure 11 As shown, corresponding to steps S224 and S225, an electromagnetic shielding connection portion 320 is deposited in the connection hole 700. The electromagnetic shielding connection portion 320 is in contact with the back electromagnetic shielding layer 330, and then the first protective film layer 610 and the first mask layer 620 are removed. Taking the electromagnetic shielding connection portion 320 as indium material as an example, indium is filled into the connection hole 700 using an electron beam evaporation process. First, the target is loaded, and high-purity indium (99.999%) is placed in a water-cooled copper crucible to avoid copper contamination; then, pre-degassing is performed, and the electron beam is preheated (e.g., preheating current is 0.6A, preheating time is 5 minutes) to remove oxides on the indium surface; then, molten filling is performed, and the electron beam is focused to bombard the indium target, with the local temperature reaching 160-180℃ (slightly higher than the indium melting point). The vacuum pressure difference drives indium vapor into the connection hole 700, and the filling time is less than 10 seconds; finally, cooling and solidification are performed, and the vacuum is maintained for 10 minutes after the gun is stopped to prevent the filled indium column from shrinking and cracking. After the electromagnetic shielding connection part 320 is fabricated, the first protective film layer 610 and the first mask layer 620 are removed. Specifically, the first mask layer 620 can be removed using a lift-off process, but this application does not impose any specific restrictions on this.

[0071] Furthermore, before depositing the electromagnetic shielding connection 320 inside the connection hole 700, an insulating layer can be formed on the inner wall of the connection hole 700, such as by depositing SiO2 using PECVD (Plasma Enhanced Chemical Vapor Deposition) process. The thickness of the insulating layer can be 200nm, thereby preventing short circuits between the electromagnetic shielding connection 320 and the superconducting quantum chip 100.

[0072] like Figure 12 As shown, corresponding to step S231, a second protective film layer 630 is formed on the side of the back electromagnetic shielding layer 330 away from the superconducting quantum chip 100. The second protective film layer 630 can be a photoresist layer, and this application does not impose specific restrictions on it.

[0073] like Figure 13 As shown, corresponding to step S232, a second mask layer 640 is formed on the side of the superconducting quantum chip 100 away from the back electromagnetic shielding layer 330. The second mask layer 640 can be formed using photolithography. First, a photoresist layer is spin-coated on the side of the superconducting quantum chip 100 away from the back electromagnetic shielding layer 330. The photoresist layer can be a dual-layer photoresist layer of LOR3A and AZ5214 with a thickness of 8 micrometers. Then, the photoresist layer is exposed and developed to form the second mask layer 640. A ring-shaped mask (with a linewidth of 40 micrometers) is used, and the exposure dose can be 140 mJ / cm². 2 .

[0074] like Figure 14 As shown, corresponding to steps S233 and S234, the electromagnetic shielding sealing ring 310 is deposited on the edge sealing area A2 based on the second mask layer 640, so the electromagnetic shielding sealing ring 310 is in contact with the electromagnetic shielding connection part 320; then the second protective film layer 630 and the second mask layer 640 are removed. Taking the material of the electromagnetic shielding sealing ring 310 as indium as an example, the electromagnetic shielding sealing ring 310 can be deposited on the edge sealing area A2 by vapor deposition, the deposition thickness can be 10 micrometers, the deposition rate can be 0.3nm / s, and thermal deformation of the adhesive layer can be avoided; then the second protective film layer 630 and the second mask layer 640 are removed by a peeling process, such as soaking in acetone for 60 minutes and using ultrasonic assistance (power can be 100W) to remove excess indium material.

[0075] like Figure 15As shown, corresponding to step S3, the superconducting quantum chip 100 and the control chip 200 are welded and fixed relative to each other, forming a sealed cavity 400 between the superconducting quantum chip 100, the sealing ring 310, and the control chip 200. The welding of the superconducting quantum chip 100 and the control chip 200 can be performed using a flip-chip bonding machine. After placing the superconducting quantum chip 100 and the control chip 200 into the flip-chip bonding machine, a spectroscopic prism microscope can first be inserted between the chips. Then, relevant parameters are adjusted to align the solder joints at the functional circuit area A1 of the superconducting quantum chip 100 and the solder joints of the control chip 200. Then, under a temperature of 180°C and pressure (e.g., 50 MPa) and a process time of 10 minutes, the solder joints at the functional circuit area A1 and the solder joints of the control chip 200 are welded together. The electromagnetic shielding sealing ring 310 acts as a spacer control block, thus forming a sealed cavity 400 between the superconducting quantum chip 100, the electromagnetic shielding sealing ring 310, and the control chip 200. Optionally, the welding of the superconducting quantum chip 100 and the control chip 200 can be performed under vacuum conditions. Alternatively, the welding of the superconducting quantum chip 100 and the control chip 200 can be performed in an inert gas atmosphere, wherein the sealed cavity 400 is filled with an inert gas, which can suppress oxidation of functional circuitry during the preservation of the packaged structure. The inert gas may include at least one of nitrogen, helium, and argon, and may be a single-element gas or a mixture of multiple elements; this application does not impose specific limitations in this regard.

[0076] Based on the above steps, the packaging structure of the superconducting quantum chip 100 is fabricated. Experiments show that the electromagnetic shielding structure formed by the electromagnetic shielding sealing ring 310, electromagnetic shielding connection 320, and back electromagnetic shielding layer 330 provided in this application embodiment exhibits superior electromagnetic shielding effectiveness compared to existing copper foil shielding structures. For example, the electromagnetic shielding sealing ring 310, electromagnetic shielding connection 320, and back electromagnetic shielding layer 330 are made of indium material, and the electromagnetic shielding connection 320 is used as a Faraday cage structure formed by the electromagnetic shielding connection post 3201. This results in a shielding effectiveness greater than 80dB (1-10GHz), a grounding resistance less than 0.1Ω, and maintains ductility at 4K low temperature, avoiding interface cracking caused by thermal stress. Furthermore, during the welding of the superconducting quantum chip 100 and the control chip 200, the indium electromagnetic shielding sealing ring 310 melts and fills the micro-gap. Under helium mass spectrometry detection, the leakage rate of the sealed cavity 400 is less than 5×10⁻⁶. -8 Pa·m 3 Furthermore, the packaging method provided in this application embodiment is based on mature photolithography and deep hole etching processes to etch interconnect holes 700 on the superconducting quantum chip 100, resulting in a higher yield for the packaging method.

[0077] Based on the same inventive concept, this application also provides a packaging structure for a superconducting quantum chip, which can be fabricated using the packaging method provided in any of the above embodiments. Figure 2 As shown, the packaging structure provided in this application embodiment includes: a superconducting quantum chip 100, one side surface of the superconducting quantum chip 100 including a functional circuit region A1 and an edge sealing region A2 surrounding the functional circuit region A1; a control chip 200, the control chip 200 being welded and fixed to the superconducting quantum chip 100; a back electromagnetic shielding layer 330, the back electromagnetic shielding layer 330 being located on the side surface of the superconducting quantum chip 100 away from the control chip 200; and a sealing ring 310, the sealing ring 310 being located between the superconducting quantum chip 100 and the control chip 200, the sealing ring 310 being located on the edge sealing region A2 and surrounding the functional circuit region A1, wherein a sealing cavity 400 is formed between the superconducting quantum chip 100, the sealing ring 310, and the control chip 200. The welding of the superconducting quantum chip 100 and the control chip 200 involves welding and fixing the solder joint at the functional circuit region A1 of the superconducting quantum chip 100 to the corresponding solder joint of the control chip 200 within the sealed cavity 400. Figure 2 The diagram illustrates the welding relationship between the solder joint at functional circuit area A1 and the solder joint of control chip 200, with the solder joint 500 located within the sealed cavity 400. Optionally, in this embodiment, the solder joint at functional circuit area A1 and the corresponding solder joint of control chip 200 are welded to form an indium solder joint. Optionally, the thickness of the back electromagnetic shielding layer 330 provided in this embodiment ranges from 5 to 10 micrometers. Furthermore, in the direction from the superconducting quantum chip 100 to the control chip 200, the thickness of the sealing ring 310 provided in this embodiment ranges from 5 to 10 micrometers; this application does not impose specific limitations on this aspect.

[0078] like Figure 4 As shown in the embodiment of this application, the sealing ring 310 is an electromagnetic shielding sealing ring 310 made of electromagnetic shielding material; wherein, the packaging structure further includes: an electromagnetic shielding connection portion 320 located in the edge sealing region A2 and penetrating the superconducting quantum chip 100, the electromagnetic shielding sealing ring 310 and the back electromagnetic shielding layer 330 being connected through the electromagnetic shielding connection portion 320. Thus, a back electromagnetic shielding layer 330 and an electromagnetic shielding sealing ring 310 are formed around the superconducting quantum chip 100, and the back electromagnetic shielding layer 330 and the electromagnetic shielding sealing ring 310 are connected through the electromagnetic shielding connection portion 320 penetrating the superconducting quantum chip 100, thereby forming an electromagnetic shielding structure around the functional circuitry of the superconducting quantum chip 100, further improving the electromagnetic shielding function of the superconducting quantum chip 100 in the packaging structure.

[0079] In some embodiments, the electromagnetic shielding connection portion 320 provided in this application embodiment may include a plurality of connection posts distributed around the functional circuit area A1, that is, based on Figure 16 The schematic diagram shows a connecting post formed by a columnar hole 710. (Example) Figure 18 The diagram shown is a structural schematic of an electromagnetic shielding connection part provided in an embodiment of this application. The electromagnetic shielding connection part 320 includes a plurality of electromagnetic shielding connecting posts 3201, which are distributed around the functional circuit area A1. Alternatively, the electromagnetic shielding connection part 320 provided in this embodiment can be at least one connecting loop surrounding the functional circuit area A1, that is, based on... Figure 17 The connecting ring formed by the annular hole 720 is shown in the diagram. Figure 19 The diagram shown is a structural schematic of an electromagnetic shielding connection part provided in an embodiment of this application. The electromagnetic shielding connection part 320 includes at least one electromagnetic shielding connection ring 3202, which surrounds the functional circuit area A1.

[0080] refer to Figure 20 As shown, this application provides another packaging structure for a superconducting quantum chip. When the sealing ring 310 is an electromagnetic shielding sealing ring 310, an insulating layer 800 is further included between the sidewall of the electromagnetic shielding connection 320 and the superconducting quantum chip 100. The insulating layer 800 is used to isolate the electromagnetic shielding connection 320 and the superconducting quantum chip 100, thereby reducing the probability of a short circuit between them. The insulating layer 800 can be made of SiO2.

[0081] In some embodiments, the sealing cavity 400 provided in this application is used to fill an inert gas, or the sealing cavity 400 is a vacuum sealing cavity, wherein the sealing cavity 400 is filled with an inert gas, which can suppress oxidation of functional circuits during the preservation of the packaged structure and improve the reliability of the packaged structure. Optionally, the inert gas provided in this application may include at least one of nitrogen, helium and argon, which may be a single-element gas or a mixture of multiple elements, and this application does not impose specific limitations on this.

[0082] Based on the same inventive concept, embodiments of this application also provide an electronic device, which includes the packaging structure of the superconducting quantum chip of any of the above embodiments. Optionally, the electronic device can be a quantum computer, etc. Specifically, the packaging structure of the superconducting quantum chip provided in this application is used for superconducting qubits (such as Transmon), superconducting quantum interference devices (SQUIDs), etc., and is particularly significant for low-noise interconnection and high density of chips at the hundred-qubit level and above. Combined with three-dimensional stacking (such as silicon interposer) technology, it can be further extended to the packaging of kilobit-level quantum processors, providing a hardware foundation for general-purpose quantum computing. In summary, this application provides a packaging method, packaging structure, and electronic device for a superconducting quantum chip. The packaging structure includes: a superconducting quantum chip, one side surface of which includes a functional circuit region and an edge sealing region surrounding the functional circuit region; a control chip, which is welded and fixed to the superconducting quantum chip; a back electromagnetic shielding layer, which is located on the side surface of the superconducting quantum chip opposite to the control chip; and a sealing ring, which is located between the superconducting quantum chip and the control chip, on the edge sealing region, and surrounding the functional circuit region. A sealed cavity is formed between the superconducting quantum chip, the sealing ring, and the control chip. The solder joints at the functional circuit region are welded and fixed to the corresponding solder joints of the control chip and located within the sealed cavity.

[0083] As described above, the technical solution provided in this application forms a back electromagnetic shielding layer on the superconducting quantum chip, away from the functional circuit region, thereby creating an electromagnetic shielding structure for the functional circuits and achieving the electromagnetic shielding function of the superconducting quantum chip. Furthermore, a sealed cavity encapsulating the functional circuit region is formed between the superconducting quantum chip, the sealing ring, and the control chip. This not only controls the welding spacing between the superconducting quantum chip and the control chip through the sealing ring but also achieves hermetic encapsulation of the superconducting quantum chip. This prevents oxidation and chemical corrosion of the superconducting material in the superconducting quantum chip at low temperatures, improves the long-term stability of the superconducting quantum chip in the dilution refrigerator, enhances the low-temperature performance of the superconducting quantum chip, and improves its overall performance and reliability.

[0084] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0086] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0087] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0088] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0089] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A packaging structure for a superconducting quantum chip, characterized in that, include: A superconducting quantum chip, wherein one side surface of the superconducting quantum chip includes a functional circuit region and an edge sealing region surrounding the functional circuit region; A control chip is welded and fixed to the superconducting quantum chip. A back electromagnetic shielding layer is located on the surface of the superconducting quantum chip that is away from the control chip. A sealing ring is located between the superconducting quantum chip and the control chip. The sealing ring is located on the edge sealing area and surrounds the functional circuit area. A sealing cavity is formed between the superconducting quantum chip, the sealing ring, and the control chip. The solder joints at the functional circuit area are welded and fixed to the corresponding solder joints of the control chip and are located within the sealing cavity.

2. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The sealing ring is an electromagnetic shielding sealing ring; The packaging structure further includes an electromagnetic shielding connection portion located in the edge sealing area and penetrating the superconducting quantum chip, wherein the electromagnetic shielding sealing ring and the back electromagnetic shielding layer are connected through the electromagnetic shielding connection portion.

3. The packaging structure of the superconducting quantum chip according to claim 2, characterized in that, The electromagnetic shielding connection includes multiple electromagnetic shielding connection posts, which are distributed around the functional circuit area.

4. The packaging structure of the superconducting quantum chip according to claim 2, characterized in that, The electromagnetic shielding connection includes at least one electromagnetic shielding connection ring, which surrounds the functional circuit area.

5. The packaging structure of the superconducting quantum chip according to claim 2, characterized in that, An insulating layer is also included between the sidewall of the electromagnetic shielding connection and the superconducting quantum chip.

6. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The thickness of the back electromagnetic shielding layer ranges from 5 to 10 micrometers.

7. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, In the direction from the superconducting quantum chip to the control chip, the thickness of the sealing ring ranges from 5 to 10 micrometers.

8. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The solder joints in the functional circuit area are welded to the corresponding solder joints of the control chip to form indium solder pillars.

9. The packaging structure of the superconducting quantum chip according to claim 1, characterized in that, The sealed cavity is used to fill inert gas, or the sealed cavity is a vacuum sealed cavity.

10. An electronic device, characterized in that, The electronic device includes the packaging structure of the superconducting quantum chip according to any one of claims 1-9.

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