Chip package structure and radio frequency front end module

Abstract

The application is suitable for the chip packaging technical field, and discloses a chip packaging structure and a radio frequency front end module. The chip packaging structure comprises a substrate, a chip, a first solder resist layer and a plastic sealing film. The substrate has a first surface. The substrate comprises a packaging area, and the packaging area is provided with a plurality of pads. The chip is arranged on the packaging area and connected with the pads. The first solder resist layer is arranged on the first surface, and the first solder resist layer is arranged around the packaging area. The plastic sealing film, the chip, the first solder resist layer and the substrate form a cavity structure. The first solder resist layer and the pads form a first gap on the first surface. In the first direction, the thickness of the first solder resist layer is less than or equal to the thickness of the pads, and the first direction is the thickness direction of the substrate. The embodiment can improve the packaging effect of the chip.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging structure and a radio frequency front-end module. Background Technology

[0002] When packaging a chip, the chip is first placed on a substrate, and the chip's solder bumps are aligned with the pads on the substrate. Then, the solder bumps are pressed together with the pads, and a molding compound is applied to the chip surface to create a sealed cavity between the chip and the substrate. However, during the molding process, molding material can easily seep into the cavity through the gap between the chip and the substrate, contaminating the bottom of the chip and affecting the packaging effect. Utility Model Content

[0003] In view of the shortcomings of the prior art, the purpose of this application is to provide a chip packaging structure and a radio frequency front-end module, which aims to improve the chip packaging effect.

[0004] To address the aforementioned technical problems, embodiments of this application provide a chip packaging structure, comprising:

[0005] A substrate having a first side, the substrate including a packaging region having a plurality of pads;

[0006] A chip, wherein the chip is disposed in the packaging area and connected to the pad;

[0007] A first solder mask layer is disposed on the first surface and surrounds the encapsulation area.

[0008] A molding compound, wherein the molding compound, the chip, the first solder mask layer, and the substrate form a cavity structure;

[0009] Wherein, the first solder resist layer and the solder pad form a first gap on the first surface, and in a first direction, the thickness of the first solder resist layer is less than or equal to the thickness of the solder pad, and the first direction is the thickness direction of the substrate.

[0010] This application also provides an RF front-end module, including the chip packaging structure described above.

[0011] The chip packaging structure provided in this application has the following advantages:

[0012] The chip packaging structure of this application embodiment provides a first solder resist layer on the first surface of the substrate, and the first solder resist layer surrounds the packaging area of ​​the substrate. This ensures that the distance H1 between the chip and the first solder resist layer in the first direction, and the distance H2 between the chip and the first surface in the first direction, satisfy H1 < H2. Furthermore, the chip packaging structure also provides that the thickness of the first solder resist layer is less than or equal to the thickness of the pads. This reduces the distance between the chip and the substrate without affecting the connection between the chip and the pads. During the process of covering the chip, the first solder resist layer, and the substrate with a molding compound, the amount of semi-solid molding compound material flowing into the gap between the chip and the first solder resist layer under pressure is reduced. This effectively reduces the amount of molding compound material flowing into the gap between the chip and the substrate, making it difficult for the semi-solid molding compound material to reach the cavity structure and contaminate the bottom of the chip. This improves the problem of molding compound material flowing into the cavity structure during chip packaging, effectively preventing the molding compound material from contaminating the circuit layer at the bottom of the chip, leading to chip failure and unsatisfactory packaging results, and improving the chip packaging effect. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0015] Figure 2 yes Figure 1 A magnified view of a portion of point i;

[0016] Figure 3 This is another schematic diagram of the chip packaging structure provided in the embodiments of this application;

[0017] Figure 4 yes Figure 3 A magnified view of a portion of point ii;

[0018] Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure after the structure is covered with a plastic sealant film;

[0019] Figure 6 yes Figure 3 A magnified view of a portion of point iii;

[0020] Figure 7 yes Figure 6A schematic diagram of the cross-sectional structure after the structure is covered with a plastic sealant film;

[0021] Figure 8 This is another schematic diagram of the chip packaging structure provided in the embodiments of this application;

[0022] Figure 9 yes Figure 8 A magnified view of the portion at point iiii;

[0023] Figure 10 yes Figure 9 A schematic diagram of the cross-sectional structure after the structure is covered with a plastic sealant.

[0024] Explanation of icon numbers:

[0025] 100. Chip packaging structure; A. Packaging area; B. Cross area; 1. Substrate; 1a. First side; 1b. Second side; 2. Chip; 21. Solder bump; 22. First edge; 23. Edge; 23a. First edge; 23b. Second edge; 23c. Third edge; 24d. Fourth edge; 3. First solder mask layer; 31. Second edge; 4. Molding film; 41. First protrusion; 42. First locking part; 421. First part; 422. Second part; 43. Second locking part; 44. Second protrusion; 5. Pad; 5a. Ground pad; 5b. Signal pad; 51. Third edge; 6. Cavity structure; 7. First gap; 8. Second gap; 9. Second solder mask layer; 10. Trace. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0027] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0028] It should also be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on the other component or may be connected to an intermediary component. When a component is referred to as being "connected to" another component, it can be directly connected to the other component or indirectly connected to the other component through an intermediary component.

[0029] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0030] In related technologies, during the packaging process of chips such as filter chips, after the solder bumps on the bottom surface of the chip are pressed to the pads on the substrate through the packaging process, a plastic encapsulation film is then covered on the surface of the chip and the substrate to form a sealed cavity structure between the chip and the substrate. However, during the process of covering the plastic encapsulation film, under certain pressure, the semi-solid plastic encapsulation material can easily flow into the cavity through the gap between the chip and the substrate, contaminating the circuit layer on the bottom surface of the chip. This not only affects the packaging effect and performance of the chip, but also leads to a reduction in the chip's working performance and causes chip failure.

[0031] In view of this, such as Figure 1 and Figure 3 As shown, this application embodiment provides a chip packaging structure 100 and an RF front-end module. By providing a first solder resist layer 3 around the packaging area A of the substrate 1 on the first surface 1a of the substrate 1, the spacing between the chip 2 and the substrate 1 is reduced by the first solder resist layer 3. This reduces the amount of molding compound entering the gap between the chip 2 and the first solder resist layer 3 when the molding compound 4 is formed during the packaging process. It also reduces the amount of molding compound entering the gap between the chip 2 and the substrate, thereby increasing the difficulty for the semi-solid molding compound to reach the cavity structure 6. This improves the problem of molding compound flowing into the cavity during chip 2 packaging, effectively improving the packaging performance of the chip 2 and reducing the impact of the molding compound on the chip 2's operating performance. The first surface 1a is the packaging surface of the substrate 1 opposite to the chip 2.

[0032] The following is in conjunction with the appendix Figures 1 to 10 This application provides a detailed description of some embodiments. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] It should be noted that in the attached diagram, Figures 1 to 10 For illustrative purposes only, where, Figure 1 , Figure 3 and Figure 8 Each of the above examples illustrates a schematic diagram of one structure of the chip packaging structure 100 of this embodiment. Figure 2 Yes Figure 1A magnified view of a portion of the image is provided. Figure 4 Yes Figure 3 A magnified view of a portion at point ii is provided. Figure 5 Yes Figure 4 A cross-sectional view. Figure 6 Yes Figure 3 A magnified view of a portion at point iii is provided. Figure 7 Yes Figure 6 A cross-sectional view. Figure 9 Yes Figure 8 A magnified view of the area at point iiii is provided. Figure 10 Yes Figure 9 The above figures are schematic cross-sectional views. They do not limit the construction of the chip packaging structure 100 in this embodiment. The figures can be combined with each other without conflict.

[0034] like Figures 1 to 3 As shown, the chip packaging structure 100 provided in this application embodiment includes a substrate 1, a chip 2, a first solder resist layer 3, and a molding compound 4. The substrate 1 has a first surface 1a and includes a packaging area A, which is provided with a plurality of pads 5. The chip 2 is disposed in the packaging area A and connected to the pads 5. The first solder resist layer 3 is disposed on the first surface 1a and surrounds the packaging area A. The molding compound 4, the chip 2, the first solder resist layer 3, and the substrate 1 form a cavity structure 6. The first solder resist layer 3 and the pads 5 form a first gap 7 on the first surface 1a. In a first direction, the thickness of the first solder resist layer 3 is less than or equal to the thickness of the pads 5. The first direction is the thickness direction of the substrate 1.

[0035] In this embodiment, the chip packaging structure 100 provides a first solder resist layer 3 on the first surface 1a of the substrate 1. The first solder resist layer 3 protects the substrate 1 and reduces warping of the substrate 1. Furthermore, the first solder resist layer 3 is disposed around the packaging area A of the substrate 1, ensuring that the distance H1 between the chip 2 and the first solder resist layer 3 in the first direction, and the distance H2 between the chip 2 and the first surface 1a in the first direction, satisfy H1 < H2. Simultaneously, the chip packaging structure 100 also provides that the thickness of the first solder resist layer 3 is less than or equal to the thickness of the pad 5, thereby reducing the distance between the chip 2 and the substrate 1 without affecting the connection between the chip 2 and the pad 5. During the process of covering the first solder resist layer 3 and the substrate 1 with molding compound to form the molding film 4, the amount of semi-solid molding compound flowing into the gap between the chip 2 and the first solder resist layer 3 under pressure is reduced. At the same time, it can also effectively reduce the amount of molding compound flowing into the gap between the chip 2 and the substrate 1, making it difficult for the semi-solid molding compound to reach the cavity structure 6 and contaminate the bottom of the chip 2. This can improve or even avoid the problem of molding compound flowing into the cavity structure 6 during chip 2 packaging, thereby effectively avoiding the problem of molding compound contaminating the circuit layer (not shown) at the bottom of the chip 2, causing chip 2 failure and unsatisfactory packaging effect, and improving the packaging effect of chip 2.

[0036] Furthermore, the first solder resist layer 3 and the pad 5 are spaced apart on the first surface 1a. Compared to the method where the first solder resist layer 3 and the pad 5 are connected at their edges, this embodiment can effectively prevent the solder resist material from covering the upper surface of the pad 5 when the first solder resist layer 3 is formed. This avoids the phenomenon of the circuit layer at the bottom of the chip 2 contacting the solder resist material, thereby preventing the solder resist material from adversely affecting the working performance of the chip 2. At the same time, this embodiment also sets the thickness of the first solder resist layer 3 to be equal to the thickness of the pad 5. While ensuring the packaging performance of the chip 2, it also facilitates the packaging operation on the substrate 1, making processing easier.

[0037] It should be understood that the pressure used in this embodiment during the process of covering the molding compound 4 on the chip 2 can be the same as or greater than the pressure used in the related technology when covering the molding compound 4. In this way, this embodiment can still prevent the molding compound material from flowing into the cavity structure 6 under high pressure. The first surface 1a can be understood as the upper surface of the substrate 1 when the chip 2 and the substrate 1 are placed vertically or horizontally, and the chip 2 is disposed on the upper surface of the substrate 1 in a flip-chip manner. The first direction can also be understood as the arrangement direction of the chip 2 and the substrate 1 when the chip 2 and the substrate 1 are placed vertically or horizontally.

[0038] like Figure 3 , Figure 5 and Figure 8As shown, in some embodiments, in a first direction, the chip 2 at least covers a portion of the packaging area A, and a second gap 8 is provided between the bottom surface of the chip 2 and the first solder mask 3, the second gap 8 being used to accommodate a portion of the encapsulation film 4.

[0039] In this embodiment, chip 2 can cover the entire packaging area A or only a portion of it. When chip 2 completely covers packaging area A, from a top-view perspective (i.e., from chip 2 towards substrate 1), packaging area A is located within the projection area of ​​chip 2 on substrate 1. When chip 2 partially covers packaging area A, from a top-view perspective, a portion of packaging area A is located within the projection area of ​​chip 2 on substrate 1, while the other portion is located outside the projection area of ​​chip 2 on substrate 1. Both of these methods achieve the goal of chip 2 covering packaging area A while also partially covering the first solder mask layer 3, ensuring that H1 is less than H2. This reduces the amount of molding compound flowing into the gap between chip 2 and the first solder mask layer 3, and also effectively reduces the amount of molding compound entering the gap between chip 2 and substrate 1, making it difficult for molding compound to enter the cavity structure 6 and contaminate the bottom of chip 2.

[0040] In this embodiment of the application, when setting the encapsulation material, the encapsulation material can be selected as epoxy molding compound with epoxy resin as the base material, silicone material, or other materials with high heat resistance and low moisture absorption. Specifically, the moisture absorption of the material is less than 0.1%. At the same time, the encapsulation material also has good electrical insulation. Optionally, the material is an electrical insulating material with a dielectric constant of about 3 to 4.

[0041] like Figure 3 , Figure 4 and Figure 5 As shown, in some embodiments, the orthographic projection of the chip 2 in the first direction overlaps with the orthographic projection of the first solder mask 3 in the first direction to form an intersection region B; the length of the intersection region B in the second direction is L, the second direction intersects the first direction, and L satisfies: 15μm≤L≤20μm; wherein, the encapsulation film 4 includes a first protrusion 41 accommodated in the second gap 8, and the orthographic projection of the first protrusion 41 in the first direction is located on the first solder mask 3.

[0042] It is understood that, from a top-down view, i.e., from the direction of chip 2 toward substrate 1, a portion of the first solder resist layer 3 is located below chip 2, so that a portion of chip 2 and a portion of the first solder resist layer 3 overlap in the first direction. In the second direction, the length of the first solder resist layer 3 extending below chip 2 is L. The second direction can be the length direction of chip 2 or the width direction of chip 2. This embodiment does not specifically limit it. When L satisfies 15μm≤L≤20μm, as in the embodiment of this application, L is set to 15μm, 16μm, 17μm, 18μm, 19μm or 20μm. At this time, the semi-solid encapsulation material can enter the second gap 8 under pressure and form the first protrusion 41 in the second gap 8. In this case, since 15μm≤L≤20μm, semi-solid molding compound can be prevented from entering the first gap 7, reducing the amount of molding compound entering the gap between chip 2 and substrate 1. This effectively avoids the problem of molding compound flowing into cavity structure 6 during chip 2 packaging, and further effectively avoids the problem of molding compound contaminating the circuit layer at the bottom of chip 2, leading to chip 2 failure and unsatisfactory packaging effect, thus reducing the impact of molding compound on the working performance of chip 2.

[0043] like Figure 3 and Figure 5 As shown, in some embodiments, the chip 2 covers multiple pads 5, that is, in the first direction, multiple pads 5 are located in the projection area of ​​the chip 2 on the substrate 1. The bottom surface of the chip 2 is provided with multiple solder bumps 21, which are connected to the pads 5 to realize the connection between the chip 2 and the pads 5. Moreover, the thickness of the first solder resist layer 3 is equal to the thickness of the pads 5. The first protrusion 41 is spaced apart from the solder bumps 21, so that when the molding compound 4 is formed, it can prevent the semi-solid molding compound material from entering between the chip 2 and the pads 5 to a certain extent, thus avoiding the molding compound material from contaminating the circuit layer at the bottom of the chip 2.

[0044] like Figure 3 , Figure 6 and Figure 7 As shown, combined with Figure 2 In some embodiments, the orthographic projection of chip 2 in the first direction overlaps with the orthographic projection of first solder mask 3 in the first direction to form an intersection region B; the length of intersection region B in the second direction is L, the second direction intersects with the first direction, and L satisfies: L < 15 μm; wherein, the encapsulation film 4 includes a first locking part 42, a part of the first locking part 42 is located in the first gap 7, and the other part of the first locking part 42 is located in the second gap 8.

[0045] It is understood that, from a top-down view, i.e., from the direction of chip 2 toward substrate 1, a portion of the first solder resist layer 3 is located below chip 2, so that a portion of chip 2 and a portion of the first solder resist layer 3 overlap in the first direction. In the second direction, the length of the first solder resist layer 3 extending below chip 2 is L. The second direction can be the length direction of chip 2 or the width direction of chip 2, and this embodiment does not specifically limit it. When L satisfies L < 15μm, as in the embodiment of this application, L is set to 10μm, 11μm, 12μm, 13μm or 14μm. At this time, when the molding compound 4 is formed, the semi-solid molding compound material enters the second gap 8 and the first gap 7 in sequence under pressure to form the first locking part 42, thereby enhancing the bonding force between the molding compound 4 and the substrate 1, ensuring good sealing of the cavity structure 6 formed by the substrate 1, the molding compound 4, the chip 2 and the first solder resist layer 3, and improving the packaging effect of chip 2.

[0046] like Figure 2 and Figure 7 As shown, in some embodiments, the first locking part 42 includes a first part 421 extending in a second direction and a second part 422 extending in a first direction. The first part 421 is accommodated in a second gap 8, and the second part 422 is accommodated in a first gap 7. The bottom of the second part 422 is connected to the first surface 1a, which can enhance the bonding force between the molding film 4 and the substrate 1.

[0047] like Figure 3 and Figure 7 As shown, in some embodiments, the top surface of the first part 421 is bonded to the chip 2, the bottom surface of the first part 421 is bonded to the first solder mask layer 3, and the upper surface of the second part 422 can be connected to the chip 2 or not in contact with the bottom surface of the chip 2, that is, the upper surface of the second part 422 can be spaced apart from the bottom surface of the chip 2. At the same time, the second part 422 can also contact the pad 5 or not in contact with the pad 5, that is, the second part 422 can also be spaced apart from the pad 5. The specific settings are set according to the actual situation. The above settings can enhance the bonding force between the molding film 4 and the substrate 1 and ensure the good sealing performance of the cavity structure 6. Furthermore, in the first direction, multiple pads 5 are located within the projection area of ​​the chip 2 on the substrate 1. Multiple solder bumps 21 are provided on the bottom surface of the chip 2. The solder bumps 21 are connected to the pads 5 to achieve the connection between the chip 2 and the pads 5. Moreover, the thickness of the first solder resist layer 3 is equal to the thickness of the pads 5. The second part 422 is spaced apart from the solder bumps 21. Thus, when forming the molding compound 4, it can prevent the semi-solid molding compound material from filling between the chip 2 and the pads 5 to a certain extent, thereby avoiding contamination of the circuit layer at the bottom of the chip 2 by the molding compound material.

[0048] like Figure 8 , Figure 9 and Figure 10As shown, in some embodiments, the chip 2 includes a first edge 22, and the first solder mask layer 3 includes a second edge 31. In a first direction, a portion of the first edge 22 is located within the packaging region A, and a portion of the second edge 31 is located outside the projection area of ​​the chip 2 on the substrate 1. The encapsulation film 4 also includes a second locking portion 43, at least a portion of which is located within the first gap 7.

[0049] It can be understood that, in the second direction, the edge of the encapsulation area A extends out of the projection area of ​​the chip 2 onto the substrate 1 in the first direction, and part of the second edge 31 is located below the chip 2, and part of the second edge 31 is located in the area outside the encapsulation area A of the chip 2. Thus, after encapsulation, the molding film 4 not only completely covers the chip 2 and at least part of the first solder resist layer 3, but also covers the part of the encapsulation area A that extends out of the chip 2, and forms part or all of the second locking part 43 in the first gap 7, so that the second locking part 43 is connected to the substrate 1, thereby enhancing the bonding force between the molding film 4 and the substrate 1.

[0050] like Figure 8 , Figure 9 and Figure 10 As shown, in some embodiments, the chip 2 has a plurality of solder bumps 21 on the side facing the substrate 1. The solder bumps 21 correspond to the pads 5 and are connected to the pads 5. The encapsulation film 4 also includes a second protrusion 44, which is connected to a second locking part 43. The second protrusion 44 covers the edge of the pads 5 and is spaced apart from the solder bumps 21.

[0051] In this embodiment, multiple solder bumps 21 on the bottom surface of chip 2 correspond one-to-one with multiple pads 5 on substrate 1. The arrangement of multiple pads 5 in the packaging area A can be set as needed, and this embodiment does not have specific limitations. Part of the molding compound 4 extends from the second locking part 43 to the pad 5 to form a second protrusion 44. There is a gap between the second protrusion 44 and the solder bumps 21, so that the amount of semi-solid molding compound material entering between chip 2 and pad 5 can be reduced during the formation of molding compound 4, thereby reducing the phenomenon of molding compound material entering the cavity structure 6 and contaminating the circuit layer at the bottom of chip 2, and thus reducing the impact of molding compound material on chip 2.

[0052] like Figure 9 and Figure 10 As shown, in some embodiments, a portion of the second locking portion 43 is housed in the first gap 7 and connected to the substrate 1, while another portion of the second locking portion 43 fills the space between the first edge 22 and the second edge 31 and is connected to the second protrusion 44. This can enhance the bonding force between the molding compound 4 and the substrate 1, as well as the bonding force between the molding compound 4 and the chip 2 and the first solder resist layer 3, respectively, so as to ensure good sealing of the cavity structure 6 formed by the substrate 1, the molding compound 4, the chip 2 and the first solder resist layer 3, and improve the packaging effect of the chip 2.

[0053] like Figure 1 As shown, in some embodiments, the thickness of the solder bump 21 in the first direction is 10μm to 15μm. For example, in the embodiments of this application, the thickness of the solder bump 21 is set to 10μm, 11μm, 12μm, 13μm, 14μm or 15μm, so that there is a reasonable distance between the chip 2 and the pad 5, so as to avoid the pad 5 touching the circuit layer at the bottom of the chip 2 and avoid contaminating the circuit layer at the bottom of the chip 2.

[0054] like Figure 3 and Figure 8 As shown, in some embodiments, the chip 2 at least covers a portion of the pads 5, and multiple pads 5 are spaced apart within the package area A. For example, multiple pads 5 are spaced apart around the projection center of the chip 2, which can ensure good electrical performance of each pad 5.

[0055] like Figure 3 , Figure 4 and Figure 5 As shown, combined with Figure 7 In one implementation, viewed from above, the packaging area A is located within the projection area of ​​the chip 2 on the substrate 1. The area of ​​the projection area of ​​the chip 2 on the substrate 1 is larger than the area of ​​the packaging area A, so that multiple pads 5 are all located within the projection area of ​​the chip 2 on the substrate 1, and the orthographic projection of the chip 2 in the first direction is rectangular. In this case, the four edges of the chip 2 are all located above the first solder resist layer 3 and form an intersection area B with the first solder resist layer 3. The distance between the chip 2 and the first solder resist layer 3 is smaller than the distance between the chip 2 and the substrate 1, thereby reducing the amount of molding compound entering the gap between the chip 2 and the first solder resist layer 3. Specifically, when forming the molding film 4 during the packaging process, the semi-solid molding compound can only enter the second gap 8, or the semi-solid molding compound can enter the second gap 8 and the first gap 7 in sequence. This can reduce the amount of molding compound entering the gap between the chip 2 and the substrate 1, thereby improving the problem of molding compound flowing into the cavity structure 6 during chip 2 packaging. At the same time, the semi-solid molding compound entering the second gap 8 and the first gap 7 in sequence can also enhance the bonding force between the molding film 4 and the substrate 1.

[0056] like Figure 8 , Figure 9 and Figure 10As shown, in another embodiment, viewed from the top, a portion of the packaging area A is located within the projection area of ​​the chip 2 on the substrate 1, and another portion of the packaging area A is located outside the projection area of ​​the chip 2 on the substrate 1. At least one of the multiple pads 5 is located outside the projection area of ​​the chip 2 on the substrate 1, and the orthographic projection of the chip 2 in the first direction is rectangular. The first edge 22 can be one of the four sides 23 of the chip 2. At least one first edge 22 is located above the first solder resist layer 3 and forms an intersection area B with the first solder resist layer 3. A portion of at least one first edge 22 is located above the first solder resist layer 3 and forms an intersection area B with the first solder resist layer 3. Another portion of at least one first edge 22 is located within the packaging area A. This can also achieve a spacing between the chip 2 and the first solder resist layer 3 that is smaller than the spacing between the chip 2 and the substrate 1. This reduces the amount of semi-solid molding compound entering the first gap 7 when forming the molding film 4, and also reduces the amount of molding compound entering the gap between the chip 2 and the substrate 1, improving the problem of molding compound flowing into the cavity structure 6. It can also enhance the bonding force between the molding film 4 and the substrate 1.

[0057] Combination Figure 3 In some embodiments, the spacing between two adjacent pads 5 is 25μm to 50μm. For example, in the embodiments of this application, the spacing between two adjacent pads 5 is 28μm, 33μm, 38μm, 43μm or 48μm, which can ensure good electrical performance of each pad 5.

[0058] like Figure 3 As shown, in some embodiments, the plurality of pads 5 include ground pads 5a and signal pads 5b; wherein the area of ​​the ground pad 5a is larger than the area of ​​the signal pad 5b, which can ensure good electrical performance. In some embodiments, the plurality of pads 5 include a plurality of ground pads 5a and a plurality of signal pads 5b, for example, the plurality of pads 5 include two ground pads 5a and three signal pads 5b, wherein the area of ​​a single ground pad 5a is larger than the area of ​​a single signal pad 5b, in order to ensure good electrical performance.

[0059] Preferably, some grounding pads 5a extend beyond the package area A, while signal pads 5b do not extend beyond the package area A. That is, some grounding pads 5a are located outside the package area A, while other grounding pads 5a are located inside the package area A, and signal pads 5b are located inside the package area A, which can ensure the quality of signal transmission.

[0060] like Figure 3As shown, in a specific embodiment, the packaging area A includes a first area (not shown) and a second area (not shown) arranged side by side. It can be understood that the first area is the upper half of the packaging area A, and the second area is the lower half of the packaging area A. The ground pad 5a is located in the first area, and the signal pad 5b is located in the second area, which helps to ensure good electrical performance of the pad 5.

[0061] Combination Figure 1 In some embodiments, the spacing between the chip 2 and the first solder resist layer 3 in the first direction is 10μm to 20μm. For example, in the embodiments of this application, the spacing between the chip 2 and the first solder resist layer 3 is set to 10μm, 12μm, 14μm, 16μm, 18μm or 20μm, which can make the spacing between the chip 2 and the first solder resist layer 3 smaller. In the embodiments of this application, by controlling the spacing between the chip 2 and the first solder resist layer 3, the amount of molding compound entering the gap between the chip 2 and the first solder resist layer 3 is reduced when the molding compound film 4 is formed during the packaging process, thereby reducing the amount of molding compound entering the gap between the chip 2 and the substrate 1, thereby improving the problem of molding compound flowing into the cavity structure 6.

[0062] Combination Figure 1 In some embodiments, the thickness of the first solder mask layer 3 in the first direction is 15μm to 22μm, as in the embodiments of this application, the thickness of the first solder mask layer 3 is set to 15μm, 17μm, 19μm, 20μm or 22μm; and / or, in the first direction, the thickness of the pad 5 is 18μm to 22μm, as in the embodiments of this application, the thickness of the pad 5 is set to 18μm, 19μm, 20μm, 21μm or 22μm. The above-mentioned thickness design of the pad 5 and the first solder mask layer 3 in this embodiment is beneficial to reduce the amount of molding compound entering the gap between the chip 2 and the substrate 1 when the molding compound film 4 is formed during the packaging process, thereby improving the problem of molding compound flowing into the cavity structure 6.

[0063] Combination Figure 1 In some embodiments, the spacing between the first solder resist layer 3 and the pad 5 is 28μm to 35μm. For example, in the embodiments of this application, the spacing between the first solder resist layer 3 and the pad 5 is set to 29μm, 31μm, 33μm, or 34μm. Preferably, the spacing between the first solder resist layer 3 and the pad 5 is set to 30μm. In this embodiment, the distance between the edge of the first solder resist layer 3 and the edge of the pad 5 is set to 28μm to 35μm. This can prevent the solder resist material from covering the upper surface of the pad 5 when the first solder resist layer 3 is formed, thereby avoiding the phenomenon of the circuit layer at the bottom of the chip 2 contacting the solder resist material. This avoids the solder resist material from adversely affecting the working performance of the chip 2, and indirectly improves the working performance of the chip 2.

[0064] like Figure 8 , Figure 9 and Figure 10 As shown, in some embodiments, the first solder mask layer 3 includes a second edge 31, the solder pad 5 includes a third edge 51, the third edge 51 faces the second edge 31, and the shape of the third edge 51 and / or the shape of the second edge 31 is arc-shaped.

[0065] In this embodiment, the shape of the second edge 31 or the third edge 51 is set to an arc shape, which can increase the perimeter of the gap between the third edge 51 and the second edge 31. This allows the first gap 7 between the first solder mask layer 3 and the pad 5 to accommodate more molding compound, improving the bonding effect between the molding compound film 4 and the substrate 1, thereby enhancing the packaging performance. In this embodiment, both the shape of the second edge 31 and the third edge 51 are set to an arc shape. On the one hand, the shapes of the third edge 51 and the second edge 31 match each other; on the other hand, it can reduce the gap in the area surrounding the pad 5 facing the first solder mask layer 3. Furthermore, when setting the shape of the second edge 31 or the third edge 51, other shapes can also be used, such as both being straight lines, or, according to design requirements, the second edge 31 being a straight line and the third edge 51 being a straight line or an arc, or other broken line structures. All of the above-mentioned different shape designs are within the scope of protection of this application and will not be elaborated further here.

[0066] like Figure 8 , Figure 9 and Figure 10 As shown, in some embodiments, in the first direction, the orthographic projection of the chip 2 at the arc position is located within the packaging area A. It can be understood that, from the top view, the area of ​​the chip 2 at the arc position is located directly above the packaging area A, and the area of ​​the chip 2 at the arc position is not covered by the first solder mask layer 3. Thus, when the molding compound 4 is covered, the molding compound material can enter the arc gap between the second edge 31 and the third edge 51, thereby enhancing the bonding force between the molding compound 4 and the substrate 1.

[0067] like Figure 8 , Figure 9 and Figure 10 As shown, in some embodiments, viewed from the top direction (i.e., from chip 2 towards substrate 1), the orthographic projection of chip 2 at the arc-shaped position is tangent to the orthographic projection of the third edge 51. In other embodiments, viewed from the top direction, the orthographic projection of chip 2 at the arc-shaped position overlaps with the orthographic projection of the third edge 51. In still other embodiments, the orthographic projection of the third edge 51 is connected to the orthographic projection of chip 2 at the arc-shaped position. All of these configurations allow the molding compound to enter the arc-shaped gap between the second edge 31 and the third edge 51 when the molding compound 4 is applied, thereby enhancing the adhesion between the molding compound 4 and the substrate 1.

[0068] like Figure 8 , Figure 9 and Figure 10 As shown, in one specific embodiment, the orthographic projection of chip 2 in the first direction is rectangular. Chip 2 also includes a first side 23a, a second side 23b, a third side 23c, and a fourth side 23d. The first side 23a and the third side 23c are arranged opposite each other, and the second side 23b and the fourth side 23d are arranged opposite each other. The second edge 31 of the first solder mask layer 3 and the third edge 51 of the pad 5 are both set as arcs. The plurality of pads 5 include two ground pads 5a arranged at an angle and three along the length direction of chip 2 (i.e., ...). Figure 8 The signal pads 5b are arranged in a left-right direction. From a top view, the connection between the first side 23a and the second side 23b covers the third edge 51 of one of the ground pads 5a. The third edge 51 of the other ground pad 5a is located outside the orthogonal projection of the chip 2. At least one signal pad 5b's third edge 51 is covered by the third side 23c, and the fourth side 23d is located above the first solder mask layer 3. Simultaneously, of the two left-right arranged ground pads 5a, the arc-shaped edge (i.e., the third edge 51) of the left ground pad 5a is close to the connection between the first side 23a and the second side 23b (i.e., the connection between the left and right sides 23a). Figure 8 The corner position on the left side of chip 2), the arc-shaped edge (i.e., the third edge 51) of the grounding pad 5a on the right side is close to the connection point of the first edge 23a and the fourth edge 23d (i.e., the corner position on the left side of chip 2). Figure 8 (The corner position on the right side of the chip 2). The above arrangement allows the molding material to enter the arc-shaped gap between the second edge 31 and the third edge 51 when the molding film 4 is covered, thereby enhancing the bonding force between the molding film 4 and the substrate 1.

[0069] like Figure 1 As shown, in some embodiments, the chip package structure 100 further includes a second solder mask layer 9, and the substrate 1 also has a second surface 1b. The second surface 1b is provided with traces 10, which are used to realize electrical connections of multiple pads 5. The second surface 1b and the first surface 1a are disposed opposite to each other along a first direction. The second solder mask layer 9 is disposed on the second surface 1b and covers part of the traces 10. The second solder mask layer 9 can protect the traces 10 and the second surface 1b of the substrate 1, and can also reduce the warping of the substrate 1.

[0070] Combination Figure 1 In some embodiments, the first solder resist layer 3 and the second solder resist layer 9 are both made of ink or insulating resin, which have an insulating effect and can also protect the substrate.

[0071] Combination Figure 1This application also provides a radio frequency (RF) front-end module, including the chip packaging structure 100 in any of the above embodiments. By using the chip packaging structure 100 in any of the above embodiments, the RF front-end module of this embodiment can effectively improve the packaging effect and performance of the chip 2, and reduce the impact of the molding compound on the working performance of the chip 2.

[0072] The above description is merely a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the content of this application's specification and drawings under the concept of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A chip packaging structure, characterized in that, include: A substrate having a first side, the substrate including a packaging region having a plurality of pads; A chip, wherein the chip is disposed in the packaging area and connected to the pad; A first solder mask layer is disposed on the first surface and surrounds the encapsulation area. A molding compound, wherein the molding compound, the chip, the first solder mask layer, and the substrate form a cavity structure; Wherein, the first solder resist layer and the solder pad form a first gap on the first surface, and in a first direction, the thickness of the first solder resist layer is less than or equal to the thickness of the solder pad, and the first direction is the thickness direction of the substrate.

2. The chip packaging structure as described in claim 1, characterized in that, In the first direction, the chip at least covers a portion of the packaged area, and a second gap exists between the bottom surface of the chip and the first solder mask layer.

3. The chip packaging structure as described in claim 2, characterized in that, The orthographic projection of the chip in the first direction and the orthographic projection of the first solder mask layer in the first direction overlap to form an intersection area; The length of the intersection region in the second direction is L, and the second direction intersects the first direction, wherein L satisfies: 15μm≤L≤20μm; The molding film includes a first protrusion housed within the second gap, and the orthographic projection of the first protrusion in the first direction is located on the first solder mask layer.

4. The chip packaging structure as described in claim 2, characterized in that, The orthographic projection of the chip in the first direction and the orthographic projection of the first solder mask in the first direction overlap to form an intersection area; The length of the intersection region in the second direction is L, and the second direction intersects the first direction, wherein L satisfies: L < 15 μm; The plastic sealing film includes a first locking portion, a part of which is located in the first gap, and another part of which is located in the second gap.

5. The chip packaging structure as described in claim 4, characterized in that, The first locking portion includes a first portion extending along the second direction and a second portion extending along the first direction, the first portion being accommodated in the second gap, the second portion being accommodated in the first gap, and the bottom of the second portion being connected to the first surface.

6. The chip packaging structure as described in claim 1, characterized in that, The chip includes a first edge, the first solder mask layer includes a second edge, and in the first direction, a portion of the first edge is located within the packaging area, and a portion of the second edge is located outside the projection area of ​​the chip on the substrate; The plastic sealing film further includes a second locking portion, at least a portion of which is located within the first gap.

7. The chip packaging structure as described in claim 6, characterized in that, The chip has a plurality of solder bumps on the side facing the substrate. The solder bumps correspond to the pads and are connected to the pads. The encapsulation film also includes a second protrusion, which is connected to the second locking part. The second protrusion covers the edge of the pads and is spaced apart from the solder bumps.

8. The chip packaging structure as described in claim 7, characterized in that, In the first direction, the thickness of the welding bump is 10μm~15μm.

9. The chip packaging structure as described in claim 1, characterized in that, The chip at least covers a portion of the pads, and the plurality of pads are spaced apart within the package area.

10. The chip packaging structure as described in claim 9, characterized in that, The spacing between two adjacent pads is 25μm to 50μm.

11. The chip packaging structure as described in claim 1, characterized in that, The plurality of pads includes ground pads and signal pads; The area of ​​the grounding pad is larger than the area of ​​the signal pad.

12. The chip packaging structure according to any one of claims 1-11, characterized in that, In the first direction, the spacing between the chip and the first solder mask layer is 10μm~20μm; and / or, In the first direction, the thickness of the first solder mask layer is 15μm~22μm; And / or, in the first direction, the thickness of the pad is 18μm~22μm.

13. The chip packaging structure according to any one of claims 1-11, characterized in that, The spacing between the first solder mask layer and the solder pad is 28μm~35μm.

14. The chip packaging structure according to any one of claims 1-11, characterized in that, The first solder mask layer includes a second edge, and the solder pad includes a third edge, the third edge facing the second edge, and the shape of the third edge and / or the shape of the second edge is arc-shaped or straight.

15. The chip packaging structure as described in claim 14, characterized in that, In the first direction, the orthographic projection of the chip at the arc-shaped position lies within the packaging area.

16. The chip packaging structure according to any one of claims 1-11, characterized in that, The chip packaging structure further includes a second solder resist layer, and the substrate also has a second surface with traces. The second surface and the first surface are disposed opposite to each other along the first direction. The second solder resist layer is disposed on the second surface and covers a portion of the traces.

17. A radio frequency front-end module, characterized in that, Includes the chip packaging structure as described in any one of claims 1-16.

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