Chip packaging structure, chip and electronic device

Abstract

The present disclosure provides a chip packaging structure, a chip and an electronic device, and relates to the technical field of semiconductors. The chip packaging structure comprises a first substrate, a first chip, a second chip and a heat sink. The first substrate comprises opposite first and second surfaces. The first chip is located on the first surface, and the second chip is located on the second surface. The second chip is electrically connected to the first chip. The heat sink is located on the second surface. The present disclosure provides a heat sink on the first substrate, which is conducive to improving the heat conduction performance of the chip packaging structure, improving the heat dissipation capacity of the chip packaging structure, and thus improving the performance of the chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a chip packaging structure, a chip, and an electronic device. Background Technology

[0002] With the continuous advancement of chip manufacturing processes and the increase in power density, heat dissipation has become a crucial aspect that urgently needs improvement in package-on-package (POP) technology. In a POP package structure, the chip at the bottom layer is the primary heat source, and its power density is typically high. However, the structure with the chip packaged on top has low thermal conductivity, resulting in high thermal resistance along the upward path of heat dissipation. Therefore, the overall heat dissipation capacity of the package is limited, which in turn affects the chip's performance. Utility Model Content

[0003] This disclosure provides a chip packaging structure, a chip, and an electronic device.

[0004] According to a first aspect of the present disclosure, a chip packaging structure is provided, comprising: a first substrate, the first substrate including opposing first and second surfaces;

[0005] The first chip is located on the first surface;

[0006] The second chip is located on the second surface and is electrically connected to the first chip.

[0007] A heat sink, which is located on the second surface.

[0008] In some embodiments of this disclosure, the projection of the first chip on the first substrate and the projection of the heat sink on the first substrate at least partially overlap.

[0009] In some embodiments of this disclosure, the first chip includes a first region and a second region;

[0010] The projection of the first region onto the first substrate overlaps with the projection of the heat sink onto the first substrate;

[0011] The projection of the second region onto the first substrate overlaps with the projection of the second chip onto the first substrate.

[0012] In some embodiments of this disclosure, the power consumption of components located in the first region of the first chip is greater than the power consumption of components located in the second region.

[0013] In some embodiments of this disclosure, the area of ​​the overlapping region between the projection of the first chip on the first substrate and the projection of the heat sink on the first substrate accounts for 25%-100% of the area of ​​the first chip, including endpoint values.

[0014] In some embodiments of this disclosure, the chip packaging structure further includes:

[0015] Second substrate;

[0016] The first chip is disposed between the first substrate and the second substrate; a molding compound is filled between the first substrate and the second substrate.

[0017] In some embodiments of this disclosure, the first substrate and / or the second substrate are ceramic substrates.

[0018] In some embodiments of this disclosure, the first substrate is provided with a plurality of heat dissipation holes.

[0019] In some embodiments of this disclosure, the first chip is flip-chip bonded to the first substrate.

[0020] In some embodiments of this disclosure, the heat sink includes a wafer that is reflow soldered onto the first substrate.

[0021] In some embodiments of this disclosure, the heat sink includes a metal sheet that is mounted on the first substrate.

[0022] In some embodiments of this disclosure, the first chip is a logic chip and the second chip is a memory chip.

[0023] According to a second aspect of the present disclosure, a chip is provided, the chip employing the chip packaging structure described above.

[0024] According to a third aspect of the present disclosure, an electronic device is provided, including the chip described above.

[0025] In this embodiment, the chip packaging structure includes a first substrate, a first chip, a second chip, and a heat sink. The first substrate includes a first side and a second side facing each other. The first chip is located on the first side, and the second chip is located on the second side, and the second chip is electrically connected to the first chip. The heat sink is located on the second side. Providing a heat sink on the first substrate in this disclosure improves the thermal conductivity and heat dissipation capacity of the chip packaging structure, thereby improving the chip's performance.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0028] Figure 1 This is a structural diagram illustrating a chip packaging structure according to an exemplary embodiment of the present disclosure.

[0029] Figure 2 This is a schematic diagram illustrating the overlapping relationship between a first substrate, a first chip, a second chip, and a heat sink according to an exemplary embodiment of the present disclosure.

[0030] Figure 3 This is a structural diagram illustrating a chip packaging structure according to another exemplary embodiment of the present disclosure.

[0031] Figure 4 This is a structural diagram illustrating a chip packaging structure according to another exemplary embodiment of the present disclosure.

[0032] Figure 5 This is a structural diagram illustrating a chip packaging structure according to yet another exemplary embodiment of the present disclosure.

[0033] Figure 6 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure.

[0034] The reference numerals in the attached figures are explained as follows:

[0035] 10. Chip packaging structure; 11. First substrate; 12. First chip; 13. Second chip; 14. Heat sink; 15. Second substrate; 16. Molding compound; 17. Bonding member; 18. Copper bump; 19. Solder ball; 602. Processing component; 604. Memory; 606. Power supply component; 608. Multimedia component; 610. Audio component; 612. Input / output interface; 614. Sensor component; 616. Communication component. Detailed Implementation

[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0037] Unless otherwise specified or stated, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “a,” “an,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “comprising” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to those listed; the terms “first” and “second” are used only as illustrative marks and are not intended to limit the number, importance, or order of the objects.

[0038] In mobile portable electronic devices such as mobile phones, tablets, and smartwatches, there is a demand for internal semiconductor devices to simultaneously possess high performance and small size. Therefore, stacked packaging technology has become a widely used packaging method. POP (Package-on-Package) achieves high-density chip integration by vertically stacking multiple package units within the same structure. While this packaging method effectively saves space, the upper package structure has low thermal conductivity, resulting in high thermal resistance along the upward heat dissipation path. Therefore, the overall heat dissipation capacity of the package is limited, thus affecting chip performance.

[0039] Based on this, this disclosure provides a chip packaging structure applicable to chip packaging scenarios. The chip can be, but is not limited to, a System-on-Chip (SoC) chip or a System-in-Package (SIP) chip. For example, it can be used for packaging logic chips and memory chips. Another example is its use in packaging logic chips and integrated other functional modules (such as sensors or RF chips), but this disclosure is not limited to these. This disclosure can improve the heat dissipation capability of the chip packaging structure, thereby improving chip performance.

[0040] The specific implementation methods of the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0041] According to one aspect of this disclosure, Figure 1 This is a structural diagram illustrating a chip packaging structure according to an exemplary embodiment of the present disclosure. For example... Figure 1 As shown, the chip package structure 10 includes: a first substrate 11, a first chip 12, a second chip 13, and a heat sink 14. The first substrate 11 includes a first side and a second side facing each other. The first chip 12 is located on the first side, the second chip 13 is located on the second side, the second chip 13 is electrically connected to the first chip 12, and the heat sink 14 is located on the second side.

[0042] The present invention provides a heat sink 14 on the first substrate 11, which is beneficial to improve the thermal conductivity of the chip packaging structure, improve the heat dissipation capacity of the chip packaging structure, and thus improve the performance of the chip.

[0043] In this embodiment, the heat sink 14 is used to help dissipate heat from the chip package structure and prevent the chip package structure from overheating. This embodiment does not specifically limit the type of heat dissipation element that the heat sink 14 is.

[0044] In this embodiment, the height of the heat sink 14 relative to the second chip 13 is not specifically limited. For example, the height of the heat sink 14 may be the same as the height of the second chip 13, thereby improving packaging efficiency. Alternatively, to further protect the second chip 13, the height of the heat sink 14 may be greater than the height of the second chip 13.

[0045] In this embodiment of the disclosure, the heat sink 14 is located on the second side of the first substrate 11. The connection relationship between the heat sink 14 and the first substrate 11 is not specifically limited in this embodiment of the disclosure.

[0046] In some embodiments of this disclosure, the heat sink 14 may include a wafer that is reflow soldered onto the first substrate 11.

[0047] In this embodiment of the disclosure, the chip may be a die with or without electrical functions (such as a dummy die), a bumped die, or a wafer-level chip-scale package (WLCSP) die, and this embodiment of the disclosure is not limited thereto.

[0048] In this embodiment of the disclosure, the material of the wafer is not specifically limited. For example, the wafer may be made of one of gallium arsenide, gallium nitride, silicon carbide, germanium, indium phosphide, silicon carbide, and molybdenum disulfide. As another example, the wafer may be made of silicon.

[0049] In this embodiment of the disclosure, the wafer is reflow soldered onto the first substrate 11. No new process technology is introduced during the chip packaging process, thereby saving production costs while improving the heat dissipation capacity of the chip packaging structure.

[0050] In some embodiments of this disclosure, the heat sink 14 may include a metal sheet that is mounted on the first substrate 11.

[0051] In this embodiment of the disclosure, the material of the metal sheet is not specifically limited. For example, the metal sheet can be made of one or a combination of silver, copper, gold, aluminum, and steel. For instance, the metal sheet can be a copper heat sink.

[0052] The metal sheet of this embodiment is mounted on the first substrate 11, and the metal heat sink 14 can further improve the heat dissipation capability of the chip packaging structure.

[0053] In some embodiments of this disclosure, the heat sink 14 may include grains with a deposited metal layer, which are reflow soldered onto the first substrate 11. The embodiments of this disclosure do not specifically limit the material of the metal layer. For example, the metal layer may be made of silver, copper, gold, aluminum, or steel.

[0054] In this embodiment, the grains with deposited metal layers are reflow soldered onto the first substrate 11 without introducing new processes, and the heat dissipation capacity can be further increased, thereby saving production costs while increasing the heat dissipation capacity.

[0055] In some embodiments of this disclosure, such as Figure 2 As shown, the projection of the first chip 12 on the first substrate 11 and the projection of the heat sink 14 on the first substrate 11 at least partially overlap.

[0056] In this embodiment of the present disclosure, the projection of the first chip 12 on the first substrate 11 and the projection of the heat sink 14 on the first substrate 11 overlap at least partially. That is, the first chip 12 and the heat sink 14 are offset in the vertical direction. In the setting of the offset structure, the ratio of the width of the overlapping area to the width of the entire first chip 12 (i.e., w / W) can be adjusted. The larger the overlap ratio, the better the heat dissipation effect.

[0057] In this embodiment of the disclosure, the overlap ratio w / W is not specifically limited and can be set according to the actual application scenario and specific application experience. For example, the area of ​​the overlapping region between the projection of the first chip 12 on the first substrate 11 and the projection of the heat sink 14 on the first substrate 11 accounts for 25%-100% of the area of ​​the first chip 12, including the endpoint values.

[0058] For example, the overlap ratio w / W can be any value among 25%, 30%, 45%, 50%, 55%, 60%, 75%, 85%, and 100%.

[0059] For example, such as Figure 3 As shown, the overlap ratio w / W is 100%. The larger the overlap ratio, the better the heat dissipation effect.

[0060] This embodiment of the invention adjusts the overlap ratio to maximize the heat dissipation capacity of the chip packaging structure while ensuring the overall structural area meets requirements, thereby improving chip performance.

[0061] It should be noted that, in order to better represent the overlapping relationship, Figure 2 The heat sink 14 located on the lower layer of the first substrate 11 is moved to the position on the upper layer of the second chip 13.

[0062] In some embodiments of this disclosure, the first chip 12 includes a first region and a second region; the projection of the first region on the first substrate 11 overlaps with the projection of the heat sink 14 on the first substrate 11; the projection of the second region on the first substrate 11 overlaps with the projection of the second chip 13 on the first substrate 11.

[0063] In this embodiment of the present disclosure, the first chip 12 and the second chip 13 are stacked and biased, so the first chip 12 can obtain an upward heat dissipation channel with low thermal resistance. That is, an upward heat dissipation channel with low thermal resistance can be obtained in the first region, thereby improving the heat dissipation capacity of the chip package structure and thus improving the performance of the chip.

[0064] According to the embodiments of this disclosure, the first chip 12 can be partitioned according to the total power consumption of the components or the total power consumption of the components per unit area.

[0065] For example, the power consumption of components located in the first region of the first chip 12 is greater than that of components located in the second region.

[0066] In this embodiment of the disclosure, the power consumption of the components in the first region can be the total power consumption of all components in the first region. The power consumption of the components in the second region can be the total power consumption of all components in the second region.

[0067] For example, the first region is a high-power region. That is, in the floorplan, components with high power consumption are placed in the first region, which is a high-power region. The high-power region is placed close to the heat sink 14, that is, the projection of the first region on the first substrate 11 overlaps with the projection of the heat sink 14 on the first substrate 11, and the overlap area is as large as possible, which can further improve the heat dissipation capacity of the chip package structure, thereby improving the performance of the chip.

[0068] like Figure 1 In the stacked package structure shown, the first chip 12 and the second chip 13 are offset in the vertical direction, so that the first region (high power consumption region) of the first chip 12 avoids the projection area of ​​the second chip 13, which has a poor heat dissipation path, and is instead placed below the heat sink 14. Since the thermal conductivity of the heat sink 14 material is better than that of the second chip 13, the first chip 12 can obtain an upward heat dissipation channel with low thermal resistance, that is, the vertical overlap region between the first chip 12 and the heat sink 14.

[0069] According to another aspect of this disclosure, Figure 4 This is a structural diagram illustrating a chip packaging structure according to another exemplary embodiment of the present disclosure. For example... Figure 4 As shown, the chip packaging structure 10 may further include a second substrate 15. The first chip 12 is disposed between the first substrate 11 and the second substrate 15; a molding compound 16 is filled between the first substrate 11 and the second substrate 15.

[0070] In this embodiment of the present disclosure, the first chip 12 can be electrically connected to the first substrate 11, and the first substrate 11 is electrically connected to the second chip 13. That is, the first chip 12 is electrically connected to the second chip 13 through the first substrate 11. The first chip 12 can also be electrically connected to the second chip 13 through a through-silicon via (TSV).

[0071] The first chip 12 is electrically connected to the second substrate 15, and the second substrate 15 can provide power or signals to the first chip 12.

[0072] The materials of the first substrate 11 and the second substrate 15 are not specifically limited and can be set according to the actual application scenario and specific application experience. For example, in order to further improve the heat dissipation capability of the chip package structure 10, the first substrate 11 and / or the second substrate 15 may be ceramic substrates.

[0073] In order to improve the heat dissipation capability in the vertical direction of the stacked package, the first substrate 11 and / or the second substrate 15 in the structure can be replaced from organic materials with ceramic substrates with higher thermal conductivity, thereby further improving the heat dissipation capability of the chip package structure and improving the chip performance.

[0074] Regarding the material of the molding compound 16, this embodiment does not limit the specific materials used. To further improve heat dissipation, a molding compound 16 with high thermal conductivity can be used. For example, the molding compound 16 may be made of silicone resin, epoxy resin, or polyimide. As another example, the molding compound 16 may be made of thermally conductive silicone or thermally conductive plastic.

[0075] In some embodiments of this disclosure, a plurality of heat dissipation holes are provided on the first substrate 11.

[0076] The distribution of the heat dissipation holes is not limited in the embodiments disclosed herein. For example, multiple heat dissipation holes may be evenly distributed on the first substrate 11. Alternatively, multiple heat dissipation holes may be distributed on the first substrate 11 corresponding to the first region; that is, multiple heat dissipation holes may be distributed in the projection area of ​​the first region on the first substrate 11, thereby enhancing heat dissipation capacity.

[0077] The embodiments disclosed herein can further increase the heat dissipation capacity of the chip packaging structure 10 by providing multiple heat dissipation holes on the first substrate 11, thereby improving the chip performance.

[0078] In this embodiment of the present disclosure, a molding compound 16 with high thermal conductivity is used on the vertical heat dissipation channel of the first chip 12, and heat dissipation holes are provided in the first substrate 11 to enhance heat dissipation capacity, reduce the thermal resistance of the upward heat dissipation path of the high power consumption area of ​​the first chip 12, improve the heat dissipation capacity of the overall stacked packaging structure, and help enhance chip performance.

[0079] In some embodiments of this disclosure, the first chip 12 is flip-chip bonded to the first substrate 11.

[0080] In this embodiment, flip-chip bonding of the first chip 12 to the first substrate 11 has several advantages. First, flip-chip bonding enables a direct electrical connection between the first chip 12 and the first substrate 11, which helps reduce signal transmission delay and improve data transmission rate. Second, this connection method can effectively improve thermal management performance because the solder joint is in direct contact with the first substrate 11, which helps dissipate heat and avoids the thermal resistance that may be caused by traditional wire bonding. In addition, flip-chip bonding can also reduce package size, improve overall integration, and enhance system reliability and shock resistance, making it particularly suitable for high-frequency, high-power, and compact design applications.

[0081] In this embodiment, the first chip 12 is flip-chip bonded to the first substrate 11, which facilitates further heat dissipation, improves the heat dissipation capacity of the chip packaging structure, and enhances the chip performance.

[0082] In some embodiments of this disclosure, the first chip 12 can be a high-performance logic chip (such as an application processor) responsible for core computing tasks. The second chip 13 can be a memory chip (such as DRAM (Dynamic Random Access Memory) or NAND Flash (Non-Volatile Memory)) used to expand memory or storage capacity. The second chip 13 can also integrate other functional modules (such as sensors or radio frequency chips). The second chip 13 can also be an integration of a memory chip with other functional modules. This disclosure does not specifically limit the type of chip the second chip 13 can be, and it can be configured according to actual applications.

[0083] For example, the first chip 12 is a logic chip, and the second chip 13 is a memory chip.

[0084] In this embodiment, the memory chip is a complete package that can be soldered onto the first substrate 11 via reflow soldering. The logic chip is flip-chip soldered onto the first substrate 11 and can be interconnected with the memory chip on the first substrate 11 via copper core balls or copper pillars, and is protected by molding compound 16.

[0085] It should be noted that this disclosure involves layering logic chips (such as CPUs (Central Processing Units) and APs (Application Processors) with memory chips (such as DRAM and NAND Flash), thereby expanding storage capacity or functional modules within a limited motherboard space. This packaging method not only effectively saves space but also improves the overall functionality and performance of the system.

[0086] In some embodiments of this disclosure, such as Figure 5As shown, the chip package structure 10 may further include a bonding member 17 located between the first substrate 11 and the second substrate 15, through which the first substrate 11 can be electrically connected to the second substrate 15. The specific type of bonding member 17 is not specifically limited in this embodiment. For example, the bonding member 17 may be a metal pillar. Exemplarily, the metal pillar may be a copper pillar, an aluminum pillar, or a silver pillar. As another example, the bonding member 17 may be a copper ball.

[0087] For example, the first substrate 11 is the upper substrate, and the second substrate 15 is the lower substrate. Electrical interconnection and signal transmission are achieved through metal pillars on both sides between the upper and lower substrates, which has the advantages of high bandwidth and short signal transmission path.

[0088] For example, the chip package structure 10 may include a plurality of copper core balls distributed around the first chip 12. That is, the plurality of copper core balls distributed around the first chip 12 can protect the first chip 12. A molding compound 16 is disposed between the first substrate 11 and the second substrate 15 to cover the bonding member 17 and the first chip 12.

[0089] In some embodiments of this disclosure, such as Figure 5 As shown, the chip package structure 10 may also include at least one copper bump 18. The copper bump 18 is used to connect the first chip 12 and the second substrate 15. The function of the copper bump 18 is to provide electrical connection and mechanical support, so that a strong connection is formed between the first chip 12 and the second substrate 15. The copper bump 18 replaces lead connections (such as lead wire frames), enabling smaller and higher performance packages.

[0090] In some embodiments of this disclosure, such as Figure 5 As shown, the chip package structure 10 may further include at least one solder ball 19, which is electrically connected to the second substrate 15 via a pad (POD). The second substrate 15 / chip package structure 10 is electrically connected to an external circuit board via the solder ball 19. In other words, the solder ball 19 provides electrical connection, heat conduction, and mechanical support between the chip and the circuit board. The solder joint formed by melting the solder ball 19 ensures signal transmission and stability between the chip and the circuit board.

[0091] In summary, in the scenario where the first chip 12 is a logic chip and the second chip 13 is a memory chip, by biasing the logic chip and adding a heatsink 14 on top of it, and setting the overlap ratio between the heatsink 14 and the logic chip to 25%-100%, the increase in structural area and the overall heat dissipation benefits are balanced. This reduces the thermal resistance of the upward heat dissipation path of the logic chip, especially in high-power areas, and improves the heat dissipation capability of the overall stacked package structure, thus helping to enhance chip performance. Furthermore, this structure can be manufactured using traditional stacked packaging processes, and no other complex processing steps are introduced except for the mounting of the heatsink 14. It should be noted that if the heatsink 14 is a wafer, and the wafer is reflow soldered onto the first substrate 11, no other complex processing steps are introduced.

[0092] It should be noted that the logic chip and the memory chip are offset in the vertical direction. A heat sink 14 is added above their high-power area to form an upward heat dissipation channel with low thermal resistance in the vertical direction. At the same time, considering the increase in the overall structural area caused by the offset, the parameter of the overlap ratio between the heat sink 14 and the logic chip is introduced. Taking into account the heat dissipation benefits and the overall package area, this ratio is adjusted according to the specific design of the logic chip to improve the heat dissipation capability of the overall structure.

[0093] This disclosure retains the advantages of traditional stacked packaging, such as high bandwidth and flexible integration of different functional modules, and can be manufactured using existing stacked packaging processes.

[0094] According to another aspect of this disclosure, a chip is provided that employs the chip packaging structure described above. The chip (Integrated Circuit, IC) can be, but is not limited to, a System-on-Chip (SoC) chip or a System-in-Package (SIP) chip. Since the chip of this disclosure possesses the chip packaging structure of the above embodiments, it has all the beneficial effects of the chip packaging structure described above, which will not be repeated here.

[0095] For example, the chip is a SOC chip, and the chip adopts the above-described chip packaging structure. The chip packaging structure 10 may include:

[0096] A first substrate 11, the first substrate 11 includes a first surface and a second surface that are opposite to each other;

[0097] First chip 12, first chip 12 is located on the first surface;

[0098] The second chip 13 is located on the second side and is electrically connected to the first chip 12.

[0099] Heat sink 14 is located on the second side.

[0100] In some embodiments of this disclosure, the projection of the first chip 12 on the first substrate 11 at least partially overlaps with the projection of the heat sink 14 on the first substrate 11.

[0101] In some embodiments of this disclosure, the first chip 12 includes a first region and a second region;

[0102] The projection of the first region on the first substrate 11 overlaps with the projection of the heat sink 14 on the first substrate 11;

[0103] The projection of the second region onto the first substrate 11 overlaps with the projection of the second chip 13 onto the first substrate 11.

[0104] In some embodiments of this disclosure, the power consumption of components located in the first region of the first chip 12 is greater than that of components located in the second region.

[0105] In some embodiments of this disclosure, the area of ​​the overlapping region between the projection of the first chip 12 on the first substrate 11 and the projection of the heat sink 14 on the first substrate 11 accounts for 25%-100% of the area of ​​the first chip 12, including the endpoint value.

[0106] In some embodiments of this disclosure, the chip package structure 10 further includes:

[0107] Second substrate 15;

[0108] The first chip 12 is disposed between the first substrate 11 and the second substrate 15; the space between the first substrate 11 and the second substrate 15 is filled with molding compound 16.

[0109] In some embodiments of this disclosure, the first substrate 11 and / or the second substrate 15 are ceramic substrates.

[0110] In some embodiments of this disclosure, a plurality of heat dissipation holes are provided on the first substrate 11.

[0111] In some embodiments of this disclosure, the first chip 12 is flip-chip bonded to the first substrate 11.

[0112] In some embodiments of this disclosure, the heat sink 14 includes a wafer that is reflow soldered onto the first substrate 11.

[0113] In some embodiments of this disclosure, the heat sink 14 includes a metal sheet that is mounted on the first substrate 11.

[0114] In some embodiments of this disclosure, the first chip 12 is a logic chip and the second chip 13 is a memory chip.

[0115] According to another aspect of this disclosure, Figure 6This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure. For example, electronic device 600 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc. Electronic device 600 may also be a mobile device such as a mobile phone, tablet, or smartwatch.

[0116] Reference Figure 6 The electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0117] Processing component 602 typically controls the overall operation of electronic device 600, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 602 may include one or more processors 620 to execute instructions; processors 620 may include the aforementioned chip. Furthermore, processing component 602 may include one or more modules to facilitate interaction between processing component 602 and other components. For example, processing component 602 may include a multimedia module to facilitate interaction between multimedia component 608 and processing component 602.

[0118] Memory 604 is configured to store various types of data to support the operation of electronic device 600. Examples of such data include any application or instruction used for operation on electronic device 600, contact data, phonebook data, messages, pictures, videos, etc. Memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0119] Power supply component 606 provides power to various components of electronic device 600. Power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 600.

[0120] Multimedia component 608 includes a screen that provides an output interface between electronic device 600 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 608 includes a front-facing camera and / or a rear-facing camera. When electronic device 600 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0121] Audio component 610 is configured to output and / or input audio signals. For example, audio component 610 includes a microphone (MIC) configured to receive external audio signals when electronic device 600 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 604 or transmitted via communication component 616. In some embodiments, audio component 610 also includes a speaker for outputting audio signals.

[0122] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0123] Sensor assembly 614 includes one or more sensors for providing state assessments of various aspects of electronic device 600. For example, sensor assembly 614 may detect the on / off state of electronic device 600, the relative positioning of components such as the display and keypad of electronic device 600, changes in position of electronic device 600 or a component of electronic device 600, the presence or absence of user contact with electronic device 600, orientation or acceleration / deceleration of electronic device 600, and temperature changes of electronic device 600. Sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 614 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0124] Communication component 616 is configured to facilitate wired or wireless communication between electronic device 600 and other devices. Electronic device 600 can access wireless networks based on communication standards, such as Wi-Fi, 3G, 4G, 5G, 6G, or combinations thereof. In some embodiments of this disclosure, communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In some embodiments of this disclosure, communication component 616 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0125] In some embodiments of this disclosure, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for executing programs or instructions.

[0126] Of course, in practical applications, the position of the chip packaging structure can be flexibly adjusted according to factors such as the specific shape, size, internal structure and heat dissipation performance requirements of the electronic device, and the embodiments disclosed herein do not limit this.

[0127] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the utility models disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0128] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A chip packaging structure, characterized in that, include: A first substrate, the first substrate including opposing first and second surfaces; The first chip is located on the first surface; The second chip is located on the second surface and is electrically connected to the first chip. A heat sink is located on the second surface; The projection of the first chip on the first substrate and the projection of the heat sink on the first substrate at least partially overlap, and the area of ​​the overlapping region of the projection of the first chip on the first substrate and the projection of the heat sink on the first substrate accounts for 25%-100% of the area of ​​the first chip, including the endpoint value.

2. The chip packaging structure according to claim 1, characterized in that, The first chip includes a first region and a second region; The projection of the first region onto the first substrate overlaps with the projection of the heat sink onto the first substrate; The projection of the second region onto the first substrate overlaps with the projection of the second chip onto the first substrate.

3. The chip packaging structure according to claim 2, characterized in that, In the first chip, the power consumption of the component located in the first region is greater than that of the component located in the second region.

4. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes: Second substrate; The first chip is disposed between the first substrate and the second substrate; a molding compound is filled between the first substrate and the second substrate.

5. The chip packaging structure according to claim 4, characterized in that, The first substrate and / or the second substrate are ceramic substrates.

6. The chip packaging structure according to claim 1, characterized in that, The first substrate has multiple heat dissipation holes.

7. The chip packaging structure according to claim 1, characterized in that, The first chip is flip-chip bonded onto the first substrate.

8. The chip packaging structure according to claim 1, characterized in that, The heat sink includes a chip, which is reflow soldered onto the first substrate.

9. The chip packaging structure according to claim 1, characterized in that, The heat sink includes a metal sheet, which is mounted on the first substrate.

10. The chip packaging structure according to claim 1, characterized in that, The first chip is a logic chip, and the second chip is a memory chip.

11. A chip, characterized in that, The chip adopts the chip packaging structure according to any one of claims 1 to 10.

12. An electronic device, characterized in that, The electronic device includes the chip of claim 11.

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