MOSFET device
By placing a passivation layer inside the opening of the metal conductive layer in the MOSFET device, and adding a protective layer at the connection corner between the side and top surfaces of the metal conductive layer, the problem of passivation layer cracking caused by the mismatch of the material layer expansion coefficient is solved, thereby improving the reliability and moisture resistance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HUNAN SANAN SEMICON CO LTD
- Filing Date
- 2025-03-31
- Publication Date
- 2026-06-16
Smart Images
Figure CN224368216U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a MOSFET device. Background Technology
[0002] Power semiconductor devices, as core components of power electronic systems, have always been indispensable electronic components in modern life, and are widely used in consumer electronics, automotive electronic systems, smart grids, as well as various industrial equipment, locomotives, aerospace, and marine systems.
[0003] Taking SiC MOSFET (silicon carbide metal oxide semiconductor field-effect transistor) devices as an example, SiC MOSFET devices have become the mainstream devices in the field of high voltage and high frequency development due to their advantages such as high input impedance, good temperature stability, excellent high frequency and high voltage performance, and large safe operating area.
[0004] The fabrication process of SiC MOSFET devices involves device fabrication and packaging. At the end of the fabrication process, a passivation layer is placed over the dielectric and metal layers to prevent external moisture intrusion and improve device stability. The packaging process involves filling with molding compound and a housing to form the packaged device.
[0005] However, during the packaging process of silicon carbide power devices, the packaged devices need to undergo reliability tests such as TCT (temperature cycling) / TS (thermal shock). Due to the mismatch of linear expansion coefficients between different material layers, such as the mismatch between the linear expansion coefficients of the molding compound / dielectric layer / metal layer, excessive stress can cause cracks or deformation in the passivation layer structure, thereby affecting the long-term reliability of the device. Utility Model Content
[0006] To address the aforementioned problems, this application provides a MOSFET device that can solve the problem of cracks or deformation in the passivation layer structure.
[0007] To address the aforementioned problems, the first technical solution provided in this application is: to provide a MOSFET device, comprising:
[0008] Substrate;
[0009] An epitaxial layer is disposed on one side of the substrate, the epitaxial layer including an active region and a terminal region surrounding the active region;
[0010] A plurality of semiconductor cells are disposed within the active region and extend from the first surface of the epitaxial layer toward the substrate; wherein the first surface of the epitaxial layer is the surface of the epitaxial layer facing away from the substrate;
[0011] A dielectric layer is disposed between two adjacent semiconductor cells and on a portion of the semiconductor cells, and extends from the portion of the semiconductor cells closest to the terminal region to cover the terminal region;
[0012] A metal conductive layer is disposed above the dielectric layer; wherein the metal conductive layer has an opening; the metal conductive layer has a top surface facing away from the epitaxial layer and a first side surface surrounding the opening;
[0013] A protective layer covers the top surface of the metal conductive layer; wherein the protective layer further extends to a first side surface of the metal conductive layer to cover the corner where the first side surface of the metal conductive layer connects to the top surface of the metal conductive layer.
[0014] A passivation layer is located within the opening and between the dielectric layer and the protective layer.
[0015] To address the aforementioned problems, the second technical solution provided in this application is: to provide a MOSFET device, comprising:
[0016] Substrate;
[0017] An epitaxial layer is disposed on one side of the substrate, the epitaxial layer including an active region and a terminal region surrounding the active region; both the epitaxial layer and the substrate have a first conductivity type;
[0018] A plurality of first doped regions are spaced apart and disposed within the active region, extending from the first surface of the epitaxial layer toward the substrate; wherein the first surface of the epitaxial layer is the surface of the epitaxial layer facing away from the substrate; the first doped regions have a second conductivity type;
[0019] A plurality of second doped regions are disposed one-to-one with a plurality of first doped regions and extend from the first surface of the epitaxial layer toward the substrate; the second doped regions have a first conductivity type;
[0020] A plurality of third doped regions are disposed one-to-one with a plurality of first doped regions and are connected to the second doped regions, and extend from the first surface of the epitaxial layer toward the substrate; the third doped regions have a second conductivity type;
[0021] A dielectric layer is disposed between two adjacent first doped regions and on the second doped region, and extends from the portion of the first doped region closest to the terminal region to cover the terminal region;
[0022] A conductive metal layer is disposed above the dielectric layer; wherein the conductive metal layer includes a source metal pad and a gate metal pad, and there is a gap between the source metal pad and the gate metal pad;
[0023] A protective layer covers the top surface of the source metal pad and the top surface of the gate metal pad; wherein the protective layer also extends to the side surface of the source metal pad and the side surface of the gate metal pad.
[0024] A passivation layer is disposed within the gap, located between the dielectric layer and the protective layer.
[0025] The beneficial effect of this application is that, unlike the prior art, the MOSFET device provided in this application includes a substrate, an epitaxial layer, a plurality of semiconductor cells, a dielectric layer, a metal conductive layer, a protective layer, and a passivation layer. The epitaxial layer is disposed on one side of the substrate and includes an active region and a terminal region surrounding the active region. A plurality of semiconductor cells are disposed within the active region and extend from a first surface of the epitaxial layer toward the substrate; wherein the first surface of the epitaxial layer is the surface of the epitaxial layer facing away from the substrate. The dielectric layer is disposed between two adjacent semiconductor cells and on a portion of the semiconductor cells, extending from the portion of semiconductor cells closest to the terminal region to cover the terminal region. The metal conductive layer is disposed above the dielectric layer; wherein the metal conductive layer has an opening; and the metal conductive layer has a top surface facing away from the epitaxial layer and a first side surface surrounding the opening. The protective layer covers the top surface of the metal conductive layer; wherein the protective layer also extends toward the first side surface of the metal conductive layer to cover the corner where the first side surface of the metal conductive layer connects to the top surface of the metal conductive layer. The passivation layer is located within the opening and between the dielectric layer and the protective layer. Specifically, compared to the existing passivation layer covering the entire surface, this application sets the passivation layer inside the opening of the metal conductive layer. This effectively reduces the stress between the passivation layer and the metal layer. This structure greatly reduces the risk of passivation dielectric cracking after subsequent packaging and reliability testing. Furthermore, the protective layer extends to the first side of the opening formed by the metal conductive layer to cover the corner where the first side of the metal conductive layer connects to the top surface of the metal conductive layer. This increases the contact area between the metal conductive layer and the protective layer, ensuring the device's moisture resistance and improving its reliability. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:
[0027] Figure 1 This is a top view of the structure of a MOSFET device after removing the protective layer and passivation layer according to an embodiment of this application;
[0028] Figure 2 The MOSFET device provided in one embodiment of this application follows the... Figure 1 A sectional view of the BB line in the middle;
[0029] Figure 3 The MOSFET device provided in another embodiment of this application follows the example shown below. Figure 1 A sectional view of the BB line in the middle;
[0030] Figure 4 The MOSFET device provided in another embodiment of this application follows the... Figure 1 A sectional view of the BB line in the middle;
[0031] Figure 5 This is a top view of the MOSFET device after the protective layer and passivation layer have been removed, according to another embodiment of this application.
[0032] Label Explanation:
[0033] Substrate-10; Epitaxial layer-20; Semiconductor cells-30; First doped region-31; Second doped region-32; Third doped region-33; Dielectric layer-40; Exposed portion-41; Conductive metal layer-50; Source metal pad-51; Gate metal pad-52; Passivation layer-60; First portion-61; Second portion-62; Field oxide layer-70; Gate layer-80; Gate 81; Gate bus 82; Protective layer-90; Back metal layer-100;
[0034] Opening - A; Gap - A1; Notch - A2. Detailed Implementation
[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0036] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0037] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0038] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0039] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).
[0040] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.
[0041] See Figure 1 and Figure 2 , Figure 1 This is a top view of the structure of a MOSFET device after removing the protective layer and passivation layer according to an embodiment of this application; Figure 2 The MOSFET device provided in one embodiment of this application follows the... Figure 1 A cross-sectional view of the BB line.
[0042] This application provides a MOSFET device, including a substrate 10, an epitaxial layer 20, a plurality of semiconductor cells 30, a dielectric layer 40, a metal conductive layer 50, a passivation layer 60, and a protective layer 90.
[0043] The substrate 10 and the epitaxial layer 20 have a first conductivity type. One of the first conductivity type and the second conductivity type (described below) is P-type, and the other is N-type. For example, in this application, the first conductivity type is N-type, and the second conductivity type is P-type.
[0044] The epitaxial layer 20 is disposed on one side of the substrate 10, and the epitaxial layer 20 includes an active region and a termination region. The active region and termination region of this application can have the same structure and function as the active region and termination region of a MOSFET device in the prior art, and will not be described in detail here. In this embodiment, the termination region surrounds the active region.
[0045] In this configuration, a plurality of semiconductor cells 30 are disposed within the active region and extend from the first surface of the epitaxial layer 20 toward the substrate 10; wherein the first surface of the epitaxial layer 20 is the surface of the epitaxial layer 20 facing away from the substrate 10. The shape of the semiconductor cells 30 is not limited and can be elongated, square, or hexagonal. Multiple semiconductor cells 30 can be arranged into a one-dimensional array or a two-dimensional array.
[0046] In one embodiment, such as Figure 2 As shown, each semiconductor cell 30 includes a first doped region 31, a second doped region 32, and a third doped region 33. Specifically, the first doped region 31 is disposed within the active region and extends from the first surface of the epitaxial layer 20 toward the substrate 10; the second doped region 32 is disposed within the first doped region 31 and extends from the first surface of the epitaxial layer 20 toward the substrate 10; the second doped region 32 has a first conductivity type; the third doped region 33 is disposed within the first doped region 31 and is connected to the second doped region 32, and the third doped region 33 extends from the first surface of the epitaxial layer 20 toward the substrate 10.
[0047] In other words, the plurality of semiconductor cells 30 include a plurality of first doped regions 31, a plurality of second doped regions 32, and a plurality of third doped regions 33. The plurality of second doped regions 32 are disposed one-to-one with the plurality of first doped regions 31, and the plurality of third doped regions 33 are disposed one-to-one with the plurality of first doped regions 31 and are connected to the second doped regions 32.
[0048] The first doped region 31 and the third doped region 33 have a second conductivity type; the second doped region 32 has a first conductivity type.
[0049] The dielectric layer 40 is located above the epitaxial layer 20, and is disposed between two adjacent semiconductor cells 30 and on a portion of the semiconductor cells 30, extending from the portion of the semiconductor cells 30 closest to the terminal region to cover the terminal region.
[0050] In one embodiment, the dielectric layer 40 is disposed between two adjacent first doped regions 31 and on the second doped region 32, and extends from the portion of the first doped region 31 closest to the terminal region to cover the terminal region.
[0051] Specifically, the dielectric layer 40 provides electrical insulation, electric field modulation, and physical protection for the internal components of the device. In some embodiments, the material of the dielectric layer 40 includes, but is not limited to, silicon dioxide, silicon nitride, aluminum oxide, and polyimide.
[0052] In this application, "above" refers to the direction from the substrate 10 to the epitaxial layer 20.
[0053] The conductive metal layer 50 is disposed above the dielectric layer 40, and the conductive metal layer 50 forms a pad structure for electrical connection with external circuits.
[0054] In this embodiment, the metal conductive layer 50 has an opening A, the bottom of which is an exposed portion 41 of the dielectric layer 40 exposed from the opening A. The metal conductive layer 50 has a top surface facing away from the epitaxial layer 20 and a first side surface surrounding the opening A. The side surface of the metal conductive layer 50 that is independent of the opening A can be a second side surface of the metal conductive layer 50.
[0055] The protective layer 90 covers the top surface of the metal conductive layer 50; the protective layer 90 also extends to the first side surface of the metal conductive layer 50 to cover the corner where the first side surface of the metal conductive layer 50 connects to the top surface of the metal conductive layer 50, and contacts the metal conductive layer 50. The protective layer 90 can improve the insulation, dust and dirt protection, and mechanical protection performance of the device.
[0056] The passivation layer 60 is located within opening A and between the dielectric layer 40 and the protective layer 90. The passivation layer 60 covers the exposed portion 41 to prevent external moisture intrusion and improve device stability. The exposed portion 41 is exposed through opening A relative to the metal conductive layer 50 completely covering the dielectric layer 40. For example, after the metal conductive layer 50 completely covers the dielectric layer 40, removing a portion of the metal conductive layer 50 will form opening A. Opening A may include through-holes inside the metal conductive layer 50, notches (grooves) at the edges of the metal conductive layer 50, or missing portions between the edges of the metal conductive layer 50 and the dielectric layer 40.
[0057] The passivation layer 60 being located within opening A means that the passivation layer 60 is located on the area of the dielectric layer 40 exposed through opening A, and / or on the first sidewall of the metal conductive layer 50 (hereinafter referred to as the sidewall of opening A). Specifically, the surface of the metal conductive layer 50 away from the substrate 10 does not have the passivation layer 60, and the thickness of the passivation layer 60 is less than the depth of opening A (the thickness of the metal conductive layer 50). The passivation layer 60 covering the exposed portion 41 means that the passivation layer 60 at least covers the area of the dielectric layer 40 exposed through opening A.
[0058] Specifically, compared to the existing passivation layer covering the entire surface, this application sets the passivation layer 60 within the opening A, thus effectively reducing the stress between the passivation layer 60 and the metal conductive layer 50. This significantly reduces the risk of passivation medium cracking after subsequent packaging and reliability testing, and also reduces the deformation of the metal conductive layer 50 caused by stress. Furthermore, the protective layer 90 covers the top surface of the metal conductive layer 50 and extends towards the first side surface of the metal conductive layer 50 to cover the corner where the first side surface of the metal conductive layer 50 connects to the top surface of the metal conductive layer 50. This increases the contact area between the metal conductive layer 50 and the protective layer 90, ensuring the device's moisture resistance and improving its reliability.
[0059] In addition, compared with the existing passivation layer covering the entire layer, the structure of the passivation layer 60 in this application only requires an additional etching process to pattern the passivation layer 60, resulting in a small design change and not affecting the reliability of other items.
[0060] It should be noted that in this embodiment, the top surface of the metal conductive layer 50 away from the substrate 10 does not have a passivation layer 60, and only the passivation layer 60 inside the opening A is retained.
[0061] Specifically, the passivation layer 60 covers the entire surface. By adding an etching process, the passivation layer 60 on the surface of the metal conductive layer 50 away from the substrate 10 is removed. This reduces the risk of passivation medium cracking due to the mismatch of linear expansion coefficients between different material layers after subsequent packaging and reliability testing, and also reduces the deformation of the metal conductive layer 50 caused by stress, thereby improving the reliability of the device.
[0062] In one embodiment, the protective layer 90 covers all portions of the first side of the metal conductive layer 50 that are not covered by the passivation layer 60.
[0063] That is, on the first side, the portion of the protective layer 90 extending to the first side is in contact with the passivation layer 60, thereby preventing moisture and other substances from entering the device, ensuring the device's moisture resistance, and improving the device's reliability.
[0064] In this application, the conductive metal layer 50 includes an insulated source metal pad 51 and a gate metal pad 52.
[0065] In one embodiment, opening A includes a gap A1 between source metal pad 51 and gate metal pad 52, which insulatingly separates the source metal pad 51 and gate metal pad 52. The source metal pad 51 has a side surface forming gap A1 and a top surface facing away from the substrate 10, and the side surface and top surface of the source metal pad 51 are connected. The gate metal pad 52 has a side surface forming gap A1 and a top surface facing away from the substrate 10, and the side surface and top surface of the gate metal pad 52 are connected. The first side surface of the conductive metal layer 50 includes the side surface of the source metal pad 51 forming gap A1 and the side surface of the gate metal pad 52 forming gap A1.
[0066] The protective layer 90 covers the top surface of the source metal pad 51 and the top surface of the gate metal pad 52; the protective layer 90 also extends to the side surface of the source metal pad 51 and the side surface of the gate metal pad 52; the passivation layer 60 is disposed in the gap A1 and is located between the dielectric layer 40 and the protective layer 90, and covers the area of the dielectric layer 40 exposed from the gap A1.
[0067] Specifically, this application sets the passivation layer 60 within the gap A1 between the source metal pad 51 and the gate metal pad 52, thus effectively reducing the stress between the passivation layer 60 and the source metal pad 51 and the gate metal pad 52. This significantly reduces the risk of passivation dielectric cracking after subsequent packaging and reliability testing, and also reduces the deformation of the metal conductive layer 50 caused by stress. Furthermore, the protective layer 90 covers the corner of the connection between the side surface and the top surface of the metal pad, increasing the contact area between the metal pad and the protective layer 90, ensuring the device's moisture resistance, and improving the device's reliability.
[0068] Furthermore, the protective layer 90 also has a first cutout portion that exposes the source metal pad 51 and a second cutout portion that exposes the gate metal pad 52. The first cutout portion facilitates the connection of the source metal pad 51 to an external circuit, and the second cutout portion facilitates the connection of the gate metal pad 52 to an external circuit.
[0069] In one embodiment, a protective layer 90 is disposed in the terminal region, thereby exposing the source metal pad 51 of the active region.
[0070] In another embodiment, the opening A includes a notch A2 between the edge of the metal conductive layer 50 and the edge of the terminal region, and the passivation layer 60 is also disposed within the notch A2 and covers the area of the dielectric layer 40 exposed from the notch A2.
[0071] In another embodiment, the opening A includes a gap A1 between the source metal pad 51 and the gate metal pad 52, and a notch A2 between the edge of the metal conductive layer 50 and the edge of the terminal region. The passivation layer 60 is disposed in the gap A1 and the notch A2 and covers the area of the dielectric layer 40 exposed from the gap A1 and the notch A2.
[0072] Specifically, by placing the passivation layer 60 only within the gap A1 and / or the notch A2, the stress between the passivation layer 60 and the metal conductive layer 50 can be effectively reduced, as well as the deformation of the metal conductive layer 50 caused by stress. This greatly reduces the risk of passivation medium cracking after subsequent packaging and reliability testing, ensures the device's moisture resistance, and improves the device's reliability.
[0073] In one embodiment, combined with Figure 1 and Figure 2 The passivation layer 60 covers the exposed portion 41 but does not extend to cover the sidewall of the opening A. That is, the passivation layer 60 covers the bottom of the opening A but does not extend to cover the first side of the metal conductive layer 50.
[0074] However, it should be noted that when the passivation layer 60 is only provided in the exposed part 41, the side of the passivation layer 60 can contact the side of the metal conductive layer 50, but it does not extend to the sidewall of the opening A to form a passivation layer 60 of a certain area.
[0075] Specifically, by setting the passivation layer 60 only on the exposed part 41, the contact between the passivation layer 60 and the metal conductive layer 50 is reduced, which can effectively reduce the stress between the passivation layer 60 and the metal conductive layer 50. This greatly reduces the risk of passivation medium cracking after subsequent packaging and reliability testing, and reduces the deformation of the metal conductive layer 50 caused by stress, ensuring the device's moisture resistance and improving the device's reliability.
[0076] In another embodiment, combined Figure 1 and Figure 3 , Figure 3 The MOSFET device provided in another embodiment of this application follows the example shown below. Figure 1 The cross-sectional view along line BB shows that the passivation layer 60 includes a first portion 61 disposed on the surface of the exposed portion 41 and a second portion 62 extending to the sidewall of the opening A.
[0077] That is, within the opening A, the passivation layer 60 also extends from the surface of the exposed portion 41 along the sidewall of the opening A toward the top surface of the metal conductive layer 50.
[0078] Specifically, the passivation layer 60 includes a first portion 61 and a second portion 62, which can increase the coverage of the passivation layer 60, ensure the device's moisture resistance, and improve the device's reliability. It can also reduce the complexity of the manufacturing process. Understandably, due to the limitations of patterning processes, retaining only the passivation layer 60 on the surface of the exposed portion 41 requires high mask precision and etching progress, leading to higher costs.
[0079] Furthermore, the sidewall of opening A, which is also the first side of the metal conductive layer 50, includes the side of the source metal pad 51 and / or the side of the gate metal pad 52. The second portion 62 covers 5-50% of the height of the sidewall of opening A. For example, the second portion 62 can cover 5% of the height of the sidewall of opening A. Another example is that the second portion 62 can cover 15% of the height of the sidewall of opening A. Yet another example is that the second portion 62 can cover 30% of the height of the sidewall of opening A. Yet another example is that the second portion 62 can cover 50% of the height of the sidewall of opening A. The specific design can be tailored to the actual situation and is not limited here. It can be understood that the second portion 62 covering 5-50% of the height of the sidewall of opening A reduces the difficulty of the patterning process for fabricating the passivation layer 60 and minimizes the amount of passivation layer 60 retained on the sidewall of opening A. This significantly reduces the risk of passivation dielectric cracking after subsequent packaging and reliability testing, ensuring the device's moisture resistance and improving device reliability.
[0080] Furthermore, since the protective layer 90 covers the portion of the sidewall of opening A not covered by the passivation layer 60, or the protective layer 90 covers all portions of the sidewall of opening A not covered by the passivation layer 60, the protective layer 90 covers 50-95% of the height of the sidewall of opening A. For example, the protective layer 90 covers 50% of the height of the sidewall of opening A; another example, the protective layer 90 covers 65% of the height of the sidewall of opening A; yet another example, the protective layer 90 covers 80% of the height of the sidewall of opening A; yet another example, the protective layer 90 covers 95% of the height of the sidewall of opening A; the specific design can be tailored to the actual situation and is not limited here.
[0081] Specifically, setting the protective layer 90 to cover 50-95% of the height of the sidewall of opening A can reduce the difficulty of the patterning process for preparing the protective layer 90, increase the contact area between the sidewall of opening A and the protective layer 90, ensure the device's moisture resistance, and improve the device's reliability.
[0082] The height direction refers to the direction from the substrate 10 to the epitaxial layer 20.
[0083] It should be noted that, see Figure 3 The sidewall of opening A can be inclined relative to the surface of substrate 10, which reduces the mask accuracy requirements for forming opening A. Alternatively, see... Figure 4 , Figure 4 The MOSFET device provided in another embodiment of this application follows the... Figure 1 In the cross-sectional view along line BB, the sidewall of opening A can be perpendicular to the surface where substrate 10 is located.
[0084] In this embodiment of the application, the angle between the sidewall of the opening A and the substrate 10 is greater than or equal to 90° and less than or equal to 150°.
[0085] For example, the angle between the sidewall of opening A and the substrate 10 is 90°. That is, the sidewall of opening A is perpendicular to the substrate 10.
[0086] For example, the angle between the sidewall of opening A and the substrate 10 can also be 110°, 120°, 140° or 150°. That is, the sidewall of opening A is inclined relative to the substrate 10.
[0087] Among them, such as Figure 3 As shown, the sidewall of the opening A is inclined relative to the substrate 10, and the passivation layer 60 includes a first part 61 and a second part 62. The first part 61 ensures the integrity of the passivation layer 60 at the bottom of the opening A (i.e., completely covers the exposed part 41), and the second part 62 can provide process margin, reduce the difficulty of aligning the patterned mask, and thus improve the product yield.
[0088] In some embodiments, the thickness of the passivation layer 60 is less than the thickness of the metal conductive layer 50, as long as it meets the device's water vapor protection requirements. Furthermore, a relatively small passivation layer thickness is beneficial for device miniaturization.
[0089] The thickness of the passivation layer 60 can be 0.1-0.5 times the thickness of the metal conductive layer 50. For example, the thickness of the passivation layer 60 can be 0.1 times, 0.3 times, or 0.5 times the thickness of the metal conductive layer 50, etc., and is not limited here.
[0090] In some embodiments, the thickness of the passivation layer 60 is 2000 Å to 2 μm. For example, the thickness of the passivation layer 60 can be 2000 Å, 6000 Å, 1 μm, 1.4 μm, 1.8 μm or 2 μm, etc., and is not limited here.
[0091] In some embodiments, the material of the passivation layer 60 includes, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.
[0092] In some embodiments, the passivation layer 60 may be a single-layer structure or a multi-layer stacked structure.
[0093] Specifically, the single-layer passivation layer 60 has a simple manufacturing process and good uniformity; the multi-layer stacked passivation layer 60 can provide better water vapor erosion resistance and stress management capabilities.
[0094] In some embodiments, the terminal area may be arranged around the active area; alternatively, the terminal area may be arranged on one side of the active area. No limitation is imposed here; the specific design depends on the actual situation.
[0095] like Figure 1 As shown, the terminal area is arranged around the active area, and opening A is only located in the terminal area.
[0096] And such Figure 5 As shown, Figure 5 This is a top view of the MOSFET device after removing the protective layer and passivation layer according to another embodiment of this application. The terminal region is arranged around the active region, and the gap A1 in the opening A is arranged in the active region.
[0097] Of course, in other embodiments, depending on the structural design requirements of the metal conductive layer 50, the opening A can also be located in the active region, and this is not a limitation.
[0098] In some embodiments, see Figure 2 The MOSFET device also includes a field oxide layer 70, a gate electrode layer 80, and a back metal layer 100.
[0099] The field oxide layer 70 is disposed between the gate electrode layer 80 and the epitaxial layer 20, and is used to adjust the electric field distribution and achieve device isolation.
[0100] The gate electrode layer 80 is disposed on the semiconductor cell 30 and surrounded by the dielectric layer 40. The gate electrode layer 80 includes a plurality of gates 81 disposed in the active region and a gate bus 82 extending from the termination region to the active region. Specifically, the gate metal pad 52 penetrates the dielectric layer 40 and is connected to the gate bus 82, thereby connecting the plurality of gates 81 through the gate bus 82. The gate electrode layer 80 may be a doped polysilicon layer.
[0101] The opening A is located on part of the gate electrode layer 80 (i.e., gate bus 82) and part of the dielectric layer 40 in the terminal region.
[0102] Specifically, by placing the passivation layer 60 within the opening A, this application prevents the passivation layer 60 from breaking or cracking at the corner where it connects to the first side and top surface of the metal conductive layer 50. This avoids the cracks in the passivation layer 60 extending towards the bottom epitaxial layer 20, allowing the passivation layer 60 to isolate the conductive path between the source metal pad 51 and the gate electrode layer 80 below the exposed portion 41. This prevents leakage caused by contact between the source metal pad 51 and the gate electrode layer 80 through cracks in the passivation layer 60. Furthermore, the protective layer 90 covers the top surface of the metal conductive layer 50 and extends to the first side of the metal conductive layer 50 where the opening A is formed, covering the corner where the first side and top surface of the metal conductive layer 50 connect. This increases the contact area between the metal conductive layer 50 and the protective layer 90, ensuring the device's moisture resistance and improving its reliability.
[0103] The back metal layer 100 is disposed on the side of the substrate 10 away from the epitaxial layer 20 and is used as the drain of the device.
[0104] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.
Claims
1. A MOSFET device, characterized by, Comprising: a substrate; an epitaxial layer disposed on a side of the substrate, the epitaxial layer comprising an active region and a termination region surrounding the active region; a plurality of semiconductor cells disposed within the active region and extending from a first surface of the epitaxial layer toward the substrate; wherein the first surface of the epitaxial layer is a surface of the epitaxial layer facing away from the substrate; a dielectric layer disposed between adjacent two of the semiconductor cells and on part of the semiconductor cells, and extending from part of the semiconductor cells closest to the termination region to cover on the termination region; a metal conductive layer disposed above the dielectric layer; wherein the metal conductive layer has an opening; and the metal conductive layer has a top surface facing away from the epitaxial layer and a first side surface surrounding the opening; a protective layer covering the top surface of the metal conductive layer; wherein the protective layer also extends to the first side surface of the metal conductive layer to cover a connecting corner between the first side surface of the metal conductive layer and the top surface of the metal conductive layer; a passivation layer located in the opening and between the dielectric layer and the protective layer.
2. The MOSFET device of claim 1, wherein: the protective layer covers 50-95% of the height of the first side surface of the metal conductive layer.
3. The MOSFET device of claim 1, wherein: the protective layer covers all parts of the first side surface of the metal conductive layer not covered by the passivation layer.
4. The MOSFET device of claim 1, wherein, the passivation layer covers the bottom of the opening and does not extend to cover the first side surface of the metal conductive layer.
5. The MOSFET device of claim 1, wherein, the passivation layer comprises a first part disposed at the bottom of the opening and a second part extending to the first side surface of the metal conductive layer.
6. The MOSFET device of claim 5, wherein: the second part covers 5-50% of the height of the first side surface of the metal conductive layer.
7. The MOSFET device of any of claims 1-6, wherein, an included angle between the first side surface of the metal conductive layer and the substrate is greater than or equal to 90° and less than or equal to 150°.
8. The MOSFET device of any of claims 1-6, wherein, the metal conductive layer comprises a source metal pad and a gate metal pad; the protective layer has a first hollow part exposing the source metal pad and a second hollow part exposing the gate metal pad; and the opening is disposed in the termination region; the opening comprises a gap between the source metal pad and the gate metal pad; and / or the opening comprises a notch between an edge of the metal conductive layer and an edge of the termination region.
9. The MOSFET device of any of claims 1-6, wherein, a thickness of the passivation layer is less than a thickness of the metal conductive layer; and the thickness of the passivation layer is 0.1-0.5 times the thickness of the metal conductive layer; the passivation layer is a single film layer structure; or the passivation layer is a multi-film layer stack structure.
10. The MOSFET device of any of claims 1-6, wherein, The MOSFET device further comprises: a gate electrode layer disposed on the semiconductor cells and surrounded by the dielectric layer; the opening is located on part of the gate electrode layer and part of the dielectric layer in the termination region.
11. A MOSFET device, characterized by, Comprising: a substrate; an epitaxial layer disposed on a side of the substrate, the epitaxial layer comprising an active region and a termination region surrounding the active region; The epitaxial layer and the substrate both have a first conductivity type; a plurality of first doped regions arranged at intervals, arranged in the active region, and extending from a first surface of the epitaxial layer towards the substrate; wherein the first surface of the epitaxial layer is a surface of the epitaxial layer facing away from the substrate; the first doped regions have a second conductivity type; a plurality of second doped regions, each arranged in a corresponding first doped region and extending from the first surface of the epitaxial layer towards the substrate; the second doped regions have the first conductivity type; a plurality of third doped regions, each arranged in a corresponding first doped region and in contact with the second doped region, and extending from the first surface of the epitaxial layer towards the substrate; the third doped regions have the second conductivity type; a dielectric layer arranged between adjacent first doped regions and on the second doped regions, and extending from a portion of the first doped region closest to the termination region to cover the termination region; a metal conductive layer arranged above the dielectric layer; wherein the metal conductive layer includes a source metal pad and a gate metal pad, and the source metal pad and the gate metal pad have a gap therebetween; a protective layer covering a top surface of the source metal pad and a top surface of the gate metal pad; wherein the protective layer also extends to a side surface of the source metal pad and a side surface of the gate metal pad; a passivation layer arranged in the gap, between the dielectric layer and the protective layer, and covering an area of the dielectric layer exposed from the gap.
12. The MOSFET device of claim 11, wherein, The passivation layer does not extend to cover the side surface of the source metal pad and the side surface of the gate metal pad.
13. The MOSFET device of claim 11, wherein, The passivation layer includes a first portion arranged on a surface of the exposed area of the dielectric layer from the gap, and a second portion extending to the side surface of the source metal pad and the side surface of the gate metal pad.
14. The MOSFET device of claim 13, wherein: the protective layer covers 50-95% of a height of the side surface of the source metal pad; and / or the protective layer covers 50-95% of a height of the side surface of the gate metal pad.