metal oxide semiconductor field effect transistor
By incorporating a semiconductor layer in a metal-oxide-semiconductor field-effect transistor, the problems of large gate-source capacitance and electric field concentration effect are solved, improving the reliability of the dielectric layer, increasing electron mobility, and reducing on-resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN SILAN ADVANCED COMPOUND SEMICON CO LTD
- Filing Date
- 2025-05-06
- Publication Date
- 2026-06-16
AI Technical Summary
Existing metal-oxide-semiconductor field-effect transistors suffer from gate-source electric field accumulation under high voltage, which affects the reliability of the gate dielectric and results in large gate-source capacitance, leading to degradation of switching characteristics.
A semiconductor layer is disposed between the first insulating dielectric layer and the drift region to form a current path of source electrode, source region, channel, drift region, substrate, and drain, thereby avoiding charge accumulation and increasing the distance between the gate polycrystalline layer and the epitaxial layer. The thickness of the semiconductor layer, the first insulating dielectric layer, and the gate polycrystalline stacked region is 1.5 to 10 times the thickness of the first insulating dielectric layer.
It improves the reliability of the first insulating dielectric layer, reduces the gate-source capacitance, increases electron mobility, and reduces on-resistance.
Smart Images
Figure CN224368217U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuits, specifically to a metal-oxide-semiconductor field-effect transistor. Background Technology
[0002] Power electronic systems are widely used in electric vehicles, photovoltaic inverters, and charging piles. The development of power electronic systems has placed higher demands on the performance of power devices in areas such as high temperature, high frequency, radiation resistance, and high voltage. Compared to silicon-based devices, silicon carbide (SiC) power devices have advantages such as higher thermal conductivity, a wider bandgap, and a higher critical breakdown electric field strength. Among them, silicon carbide power metal-oxide-semiconductor field-effect transistors (MOSFETs) are increasingly being used in systems due to their high power density, fast switching speed, and high thermal conductivity.
[0003] Metal-oxide-semiconductor (MOS) field-effect transistors (FETs) are further classified into planar gate and trench gate structures. Planar MOS FETs present two challenges: First, the electric field accumulation between the gate and source under high voltage can affect the reliability of the gate dielectric. Second, the relatively large gate-source capacitance degrades the switching characteristics of the MOS FET. Utility Model Content
[0004] This application provides a metal-oxide-semiconductor field-effect transistor (MOSFET) that improves the electron mobility of the MOSFET.
[0005] According to this application, a metal-oxide-semiconductor field-effect transistor is provided, comprising at least one cell, wherein the cell includes:
[0006] The substrate includes a first surface and a second surface disposed opposite to each other, and the substrate is of a first doping type;
[0007] An epitaxial layer is formed on the first surface of the substrate, and the epitaxial layer is of the first doping type;
[0008] The drift region extends from the first surface of the epitaxial layer into the epitaxial layer. The drift region is of the first doping type, and the doping concentration of the drift region is higher than that of the epitaxial layer.
[0009] The body region extends from the surface of the drift region into the drift region. The body region is located on both sides of the cell and is the second type of doping.
[0010] The source region extends from the surface of the bulk region into the bulk region. A channel is formed between the source region and the drift region within the bulk region. The source region is of the first doping type.
[0011] The body contact region has a higher doping concentration than the drift region. The body contact region extends from the surface of the body region into the body region. The body contact region is a second doping type. The body contact region is located on both sides of the cell within the body region. The source region and the body contact region are in contact with each other.
[0012] The semiconductor layer is located on the drift region between the body regions of two adjacent cells and the bottom of the semiconductor layer extends into the drift region. The semiconductor layer and the body region do not overlap.
[0013] A first insulating dielectric layer covers the semiconductor layer, the channel between two adjacent cells, and a portion of the source region of two adjacent cells;
[0014] The gate is polycrystalline, and the gate polycrystalline layer is covered on the first insulating dielectric layer.
[0015] Preferably, the metal-oxide-semiconductor field-effect transistor further includes:
[0016] Drain electrode, located on the second surface of the substrate;
[0017] The source electrode is led out through the second through-hole of the second insulating dielectric layer, and the second metal is connected to a portion of the source region and the body.
[0018] The gate is led out through the first through-hole of the first insulating dielectric layer, and the first metal is polycrystalline connected to the gate.
[0019] Preferably, in the direction parallel to the substrate, the width of the semiconductor layer is 10% to 100% of the width of the drift region between the bulk regions of two adjacent cells.
[0020] Preferably, in the direction parallel to the substrate, if the width of the semiconductor layer is less than the width of the drift region between the body regions of two adjacent cells, the gate polycrystalline material also covers the drift region between the body regions of two adjacent cells that are not covered by the semiconductor layer.
[0021] Preferably, the first insulating dielectric layer is a thermally oxidized layer.
[0022] Preferably, the epitaxial layer is one of silicon epitaxy, silicon carbide epitaxy, gallium nitride epitaxy, gallium oxide epitaxy, carbon epitaxy, and gallium arsenide epitaxy.
[0023] Preferably, the substrate is one of silicon substrate, silicon carbide substrate, gallium nitride substrate, gallium oxide substrate, carbon substrate, aluminum nitride substrate, gallium arsenide substrate, and sapphire substrate.
[0024] Preferably, the semiconductor layer is of the first doping type.
[0025] Preferably, the semiconductor layer comprises, from bottom to top, a first semiconductor layer of a first doping type and a second semiconductor layer of a second doping type along the direction perpendicular to the substrate.
[0026] Preferably, the semiconductor layer is a silicon carbide layer.
[0027] Preferably, in the direction perpendicular to the substrate, the thickness of the semiconductor layer, the first insulating dielectric layer, and the gate polycrystalline stack region is 1.5 to 10 times the thickness of the first insulating dielectric layer.
[0028] Preferably, in the direction perpendicular to the substrate, the thickness of the semiconductor layer, the first insulating dielectric layer, and the gate polycrystalline stack region is 2 to 4 times the thickness of the first insulating dielectric layer.
[0029] Preferably, the first insulating dielectric layer is a gate dielectric layer.
[0030] Preferably, the thickness of the semiconductor layer is 0–10 μm.
[0031] Preferably, the bottom of the semiconductor layer extends into the drift region.
[0032] When the metal-oxide-semiconductor field-effect transistor (MOSFET) of this application is turned on, the current path is sequentially: source electrode, source region, channel, drift region, substrate, and drain. In this MOSFET, the first insulating dielectric layer and the drift region are separated by a semiconductor layer, preventing charge accumulation between them and improving the reliability of the first insulating dielectric layer. The semiconductor layer increases the distance between the gate polycrystalline layer and the epitaxial layer. The thickness of the semiconductor layer, the first insulating dielectric layer, and the gate polycrystalline stacked region is 1.5 to 10 times the thickness of the first insulating dielectric layer. Preferably, in the direction perpendicular to the substrate, the thickness of the semiconductor layer, the first insulating dielectric layer, and the gate polycrystalline stacked region is 2 to 4 times the thickness of the first insulating dielectric layer. The semiconductor layer does not introduce carbon clusters, thereby reducing the transistor's on-resistance.
[0033] By avoiding direct contact between the drift region between the bulk regions and the first insulating dielectric layer through the semiconductor layer, carrier scattering caused by epitaxial surface roughness is reduced, thereby improving the electron mobility of the transistor. Attached Figure Description
[0034] The above and other objects, features, and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0035] Figure 1 A cross-sectional view of a metal-oxide-semiconductor field-effect transistor according to an embodiment of this application is shown;
[0036] Figure 2-11 A method for fabricating a metal-oxide-semiconductor field-effect transistor according to an embodiment of this application is shown. Detailed Implementation
[0037] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0038] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0039] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0040] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0041] In existing metal-oxide-semiconductor (MOSFETs), charge accumulation occurs between the first insulating dielectric layer and the drift region, affecting the MOSFET's performance. Furthermore, a shorter distance between the gate polycrystalline region and the source region leads to a larger gate-source capacitance.
[0042] In view of this, this application proposes a metal-oxide-semiconductor field-effect transistor, wherein a semiconductor layer is disposed between the drift region and the first insulating dielectric layer. During the process of forming the first insulating dielectric layer, the semiconductor layer protects the drift region.
[0043] Figure 1 The exemplary metal-oxide-semiconductor field-effect transistor provided in this application includes at least one cell, the cell comprising:
[0044] Substrate 101 includes a first surface and a second surface disposed opposite to each other, and substrate 101 is of a first doping type;
[0045] Epitaxial layer 102 is formed on the first surface of substrate 101, and epitaxial layer 102 is of the first doping type;
[0046] Drift region 103, the doping concentration of drift region 103 is higher than the doping concentration of epitaxial layer 102, drift region 103 is formed in epitaxial layer 102, and drift region 103 is the first doping type;
[0047] Body region 104 extends from the surface of drift region 103 into drift region 103. Body region 104 is located on both sides of the cell. Body region 104 is a second doping type.
[0048] Source region 105 extends from the surface of body region 104 into body region 104. A channel is formed in body region 104 between source region 105 and drift region 103. Source region 105 is of the first doping type.
[0049] The body contact region 106 has a higher doping concentration than the drift region 103. The body contact region 106 extends from the surface of the body region 104 into the body region 104. The body contact region 106 is of the second doping type. The body contact region 106 is located on both sides of the cell in the body region 104. The source region 105 and the body contact region 106 are in contact with each other.
[0050] Semiconductor layer 107 is located on drift region 103 between body regions 104 of two adjacent cells, and semiconductor layer 107 and body region 104 do not overlap;
[0051] The first insulating dielectric layer 108 covers the semiconductor layer 107, the channel of two adjacent cells, and a portion of the source region 105 of two adjacent cells.
[0052] A gate polycrystalline 109 is applied over a first insulating dielectric layer 108.
[0053] Metal-oxide-semiconductor field-effect transistors also include:
[0054] Drain 113, which is located on the second surface of substrate 101;
[0055] Source 112 is connected to the second metal source region 105 via the second through hole of the second insulating dielectric layer. Source 112 is insulated from the gate and the gate polycrystalline 109.
[0056] The gate (not shown in the figure) is connected to the gate polysilicon 109 via the first metal of the first through-hole of the first insulating dielectric layer 108.
[0057] In the direction parallel to the substrate 101, the width of the semiconductor layer 107 is 10% to 100% of the width of the drift region 103 between the body regions 104 of two adjacent cells.
[0058] In the direction parallel to the substrate 101, if the width of the semiconductor layer 107 is less than the width of the drift region between the body regions 104 of two adjacent cells, the gate polysilicon 109 also covers the drift region between the body regions 104 of two adjacent cells that are not covered by the semiconductor layer 107.
[0059] The first insulating dielectric layer 108 is a thermally oxidized layer.
[0060] The epitaxial layer is one of silicon epitaxy, silicon carbide epitaxy, gallium nitride epitaxy, gallium oxide epitaxy, carbon epitaxy, and gallium arsenide epitaxy.
[0061] The substrate 101 is one of the following: silicon substrate, silicon carbide substrate, gallium nitride substrate, gallium oxide substrate, carbon substrate, aluminum nitride substrate, gallium arsenide substrate, and sapphire substrate.
[0062] Semiconductor layer 107 is of the first doping type.
[0063] The semiconductor layer 107 includes, from bottom to top, a first semiconductor layer of a first doping type and a second semiconductor layer of a second doping type along the direction perpendicular to the substrate 101.
[0064] Semiconductor layer 107 is a silicon carbide layer.
[0065] In the direction perpendicular to the substrate 101, the thickness of the stacked region of semiconductor layer 107, first insulating dielectric layer 108 and gate polycrystalline 109 is 1.5 to 10 times the thickness of the first insulating dielectric layer.
[0066] In the direction perpendicular to the substrate 101, the thickness of the stacked region of semiconductor layer 107, first insulating dielectric layer 108 and gate polycrystalline 109 is 2 to 4 times the thickness of the first insulating dielectric layer 108.
[0067] The first insulating dielectric layer 108 is a gate dielectric layer.
[0068] Drift region 103 is formed in the epitaxial layer by ion implantation. Body region 104 is formed in drift region 103 by ion implantation. Source region 105 is formed in body region 104 by ion implantation. Body contact region 106 is formed in body region 104 by ion implantation.
[0069] In some embodiments, the thickness of the semiconductor layer 107 is 0–10 μm.
[0070] When a metal-oxide-semiconductor (MOSFET) field-effect transistor is turned on, the current path is sequentially: source electrode 112 - source region 105 - channel - drift region 103 - substrate 101 - drain 113. In the MOSFET of this application, the first insulating dielectric layer 108 and the drift region 103 are separated by a semiconductor layer 107, preventing charge accumulation between them and improving the reliability of the first insulating dielectric layer 108. The semiconductor layer 107 increases the distance between the gate polycrystalline layer 109 and the epitaxial layer. The thickness of the stacked region of semiconductor layer 107, first insulating dielectric layer 108, and gate polycrystalline layer 109 is 1.5 to 10 times the thickness of the first insulating dielectric layer. Preferably, in the direction perpendicular to the substrate, the thickness of the stacked region of semiconductor layer 107, first insulating dielectric layer 108, and gate polycrystalline layer 109 is 2 to 4 times the thickness of the first insulating dielectric layer. The semiconductor layer does not introduce carbon clusters, thereby reducing the transistor's on-resistance.
[0071] The semiconductor layer avoids direct contact between the drift region between the bulk regions and the first insulating dielectric layer 108, thereby reducing carrier scattering caused by epitaxial surface roughness and improving the electron mobility of the transistor.
[0072] The doping concentration of substrate 101 is greater than that of epitaxial layer 102. In one embodiment, substrate 101 is a silicon substrate and epitaxial layer 102 is a silicon carbide epitaxial layer. In another embodiment, substrate 101 is a silicon substrate and epitaxial layer 102 is a silicon carbide epitaxial layer.
[0073] like Figure 2 As shown:
[0074] A substrate 101 is formed, the substrate including a first surface and a second surface disposed opposite to each other, and the substrate is of a first doping type;
[0075] An epitaxial layer 102 is formed on the first surface of the substrate 101, and the epitaxial layer 102 is of the first doping type.
[0076] A drift region 103 is formed in the epitaxial layer 102. The drift region 103 extends from the first surface of the epitaxial layer 102 into the epitaxial layer 102. The drift region 103 is of the first doping type, and the doping concentration of the drift region 103 is higher than that of the epitaxial layer.
[0077] For example, a first type of doped impurity is implanted into the epitaxial layer 102 and activated at high temperature to form a drift region 103.
[0078] like Figure 3As shown, a body region 104 is formed. The body region 104 extends from the surface of the drift region 103 into the drift region 103, and is located on both sides of the cell. The body region 104 is of a second doping type. For example, a second doping type impurity is implanted into the drift region 103 and activated at high temperature to form the body region 104. The body region 104 extends from the upper surface of the drift region 103 into the interior of the drift region 103, and the bottom of the body region 104 is located within the drift region 103.
[0079] like Figure 4 As shown, a semiconductor layer 107 is formed in the drift region 103, and the semiconductor layer 107 is of the second doping type. The semiconductor layer 107 is located on the drift region 103 between the body regions 104 of two adjacent cells, and the semiconductor layer 107 and the body region 104 do not overlap. For example, the semiconductor layer 107 is formed by implanting a second doping type impurity into the drift region 103 and activating it at high temperature. The semiconductor layer 107 extends from the upper surface of the drift region 103 into the interior of the drift region 103, and the bottom of the semiconductor layer 107 is located within the drift region 103. The junction depth of the semiconductor layer 107 is smaller than the junction depth of the body region 104. In some embodiments, in Figure 3 The entire upper surface of the structure shown is ion implanted to form a semiconductor layer 107, and the ion implantation window is as follows: Figure 4 As shown in range B. In other embodiments, as shown in... Figure 4 Ion implantation is performed through the ion implantation window shown in range A to form a semiconductor layer 107.
[0080] like Figure 7 , Figure 8 A first insulating dielectric layer 108 is formed, which covers the semiconductor layer 107, the channel of two adjacent cells, and part of the source region 105 of two adjacent cells.
[0081] like Figure 9 A gate polycrystalline 109 is formed, which covers the first insulating dielectric layer 108.
[0082] like Figure 10 , Figure 11 A drain electrode 113 is formed, and the drain electrode 113 is located on the second surface of the substrate;
[0083] A source electrode 112 is formed, a second insulating dielectric layer 111 is formed, and a via corresponding to the body contact region 106 is formed by etching the second insulating dielectric layer 111. The material of the second insulating dielectric layer 111 is, for example, silicon oxide or silicon nitride. The via exposes the upper surface of the body contact region 106 and part of the upper surface of the source region 105, that is, the width of the via is greater than the width of the body contact region 106. A second metal is led out from the second via of the source electrode second insulating dielectric layer 111, and the second metal is connected to a portion of the source region 105 and the body contact region 106;
[0084] The gate is led out through the first through-hole of the first insulating dielectric layer, and the first metal is polycrystalline connected to the gate.
[0085] In some embodiments, the semiconductor layer 107 is relatively thin, and the thermal oxidation process that forms the gate dielectric material layer 1080 consumes most of the semiconductor layer 107.
[0086] exist Figures 2-11 In the manufacturing method shown, the upper surface portion of the drift region 103 is converted into a semiconductor layer 107 by ion implantation. In some embodiments, in Figure 5 Based on the structure shown, a semiconductor layer 107 is formed on the upper surface of the drift region 103 using processes such as CVD, PVD, and epitaxy. The semiconductor layer 107 and the bulk region 104 do not overlap. Subsequently, a bulk contact region 106 and a source region 105 are formed in the bulk region 104, thereby obtaining... Figure 1 The structure shown.
[0087] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A metal-oxide-semiconductor field-effect transistor, comprising at least one cell, characterized in that, The cells include: A substrate, the substrate including a first surface and a second surface disposed opposite to each other, the substrate being of a first doping type; An epitaxial layer is formed on a first surface of the substrate, and the epitaxial layer is of a first doping type; A drift region extends from the first surface of the epitaxial layer into the epitaxial layer, the drift region being of a first doping type, and the doping concentration of the drift region being higher than the doping concentration of the epitaxial layer; A body region extending from the surface of the drift region into the drift region, the body region being located on both sides of the cell, and the body region being a second doping type; A source region extends from the surface of the body region into the body region, and a channel is formed in the body region between the source region and the drift region. The source region is of a first doping type. The body contact region has a higher doping concentration than the drift region. The body contact region extends from the surface of the body region into the body region. The body contact region is of the second doping type. The body contact region is located on both sides of the cell within the body region. The source region and the body contact region are in contact with each other. A semiconductor layer is located on a drift region between two adjacent cell bodies, and the semiconductor layer and the body regions do not overlap. A first insulating dielectric layer covers the semiconductor layer, the channel of the two adjacent cells, and a portion of the source region of the two adjacent cells; A gate polycrystalline structure is formed on the first insulating dielectric layer.
2. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, Also includes: Drain electrode, the drain electrode being located on the second surface of the substrate; The source electrode has a second metal led out from a second through-hole in the second insulating dielectric layer, and the second metal is connected to a portion of the source region and the body contact region. The gate is led out through a first through-hole in the first insulating dielectric layer, and the first metal is polycrystalline connected to the gate.
3. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, In the direction parallel to the substrate, the width of the semiconductor layer is 10% to 100% of the width of the drift region between the bulk regions of two adjacent cells.
4. The metal-oxide-semiconductor field-effect transistor according to claim 3, characterized in that, In the direction parallel to the substrate, if the width of the semiconductor layer is less than the width of the drift region between the body regions of two adjacent cells, the gate polycrystalline material also covers the drift region between the body regions of two adjacent cells that are not covered by the semiconductor layer.
5. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The first insulating dielectric layer is a thermally oxidized layer.
6. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The epitaxial layer is one of silicon epitaxy, silicon carbide epitaxy, gallium nitride epitaxy, gallium oxide epitaxy, carbon epitaxy, and gallium arsenide epitaxy.
7. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The substrate is one of the following: silicon substrate, silicon carbide substrate, gallium nitride substrate, gallium oxide substrate, carbon substrate, aluminum nitride substrate, gallium arsenide substrate, and sapphire substrate.
8. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The semiconductor layer is of the first doping type.
9. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The semiconductor layer comprises, from bottom to top, a first semiconductor layer of a first doping type and a second semiconductor layer of a second doping type along the direction perpendicular to the substrate.
10. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The semiconductor layer is a silicon carbide layer.
11. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, In the direction perpendicular to the substrate, the thickness of the semiconductor layer, the first insulating dielectric layer, and the gate polycrystalline stack region is 1.5 to 10 times the thickness of the first insulating dielectric layer.
12. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, In the direction perpendicular to the substrate, the thickness of the semiconductor layer, the first insulating dielectric layer, and the gate polycrystalline stack region is 2 to 4 times the thickness of the first insulating dielectric layer.
13. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The first insulating dielectric layer is a gate dielectric layer.
14. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The thickness of the semiconductor layer is 0–10 μm.
15. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The bottom of the semiconductor layer extends into the drift region.