Packaging structure

Abstract

The utility model provides a kind of packaging structure, comprising: first chip module, including the first integrated chip group with first main core particle and first sub core particle;Second chip module, including the second integrated chip group with second main core particle and second sub core particle, and first and second chip module are connected by the first and second module interconnecting area of first and second main core particle;First and second module interconnecting area are respectively arranged in the first sub edge area of first and second main core particle, first main core particle and second main core particle are arranged along first direction, and in the second direction perpendicular to first direction, partial offset is made, so that the first sub edge area of first and second main core particle faces each other in first direction, and in first direction, the second sub edge area of first main core particle faces one of first and second sub core particle, and the second sub edge area of second main core particle faces another of first and second sub core particle.The utility model can improve packaging warping, reduce interconnection distance.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of semiconductor packaging technology, and in particular to a packaging structure. Background Technology

[0002] With the development of semiconductor technology, Moore's Law is progressing at an increasingly slower pace, the number of transistors that can be integrated onto a chip is multiplying, and chip manufacturing is becoming increasingly difficult. The development of semiconductor technology has two directions: one is to continue Moore's Law (More Moore), and the other is to extend Moore's Law (More than Moore). The technological route of extending Moore's Law can use semiconductor packaging technology to integrate multiple functional chips into a single package. How to achieve high performance, multifunctionality, and miniaturization of large-scale complex chip systems is an important research topic in the industry. Utility Model Content

[0003] A packaging structure is provided according to at least one embodiment of the present disclosure, comprising: a first chip module, including: a first integrated chipset, the first integrated chipset including a first main chip and a first sub-chip connected to each other, the first main chip including a first inter-module connection area and a first set of internal connection areas configured to be connected to the first sub-chip; and a second chip module, including: a second integrated chipset, the second integrated chipset including a second main chip and a second sub-chip connected to each other, the second main chip including a second inter-module connection area and a second set of internal connection areas configured to be connected to the second sub-chip, the first chip module and the second chip module being connected to each other via transceiver interfaces respectively located in the first inter-module connection area and the second inter-module connection area; wherein the first main chip and the second chip module are connected to each other via transceiver interfaces located in the first inter-module connection area and the second inter-module connection area respectively; wherein the first main chip and the second chip module are connected to each other via transceiver interfaces respectively located in the first inter-module connection area and the second inter-module connection area; Each of the second main core particles has a first edge including a first sub-edge region and a second sub-edge region. The first inter-module connection region and the second inter-module connection region are respectively disposed in the first sub-edge region of the first main core particle and the first sub-edge region of the second main core particle. The first main core particle and the second main core particle are arranged along a first direction and partially offset in a second direction perpendicular to the first direction, such that the first sub-edge region of the first main core particle and the first sub-edge region of the second main core particle face each other in the first direction, and the second sub-edge region of the first main core particle faces one of the first sub-core particle and the second main core particle in the first direction, and the second sub-edge region of the second main core particle faces the other of the first sub-core particle and the second main core particle in the first direction.

[0004] In the packaging structure provided according to at least one embodiment of the present disclosure, the first main chip and the second main chip are each logic chips, and the first sub-chip and the second sub-chip are each input / output chips.

[0005] In the packaging structure provided by at least one embodiment of the present disclosure, the first chip module further includes a first additional chip electrically connected to the first integrated chipset, and the first main chip further includes a first set of external connection areas configured to be connected to the first additional chip, wherein the first set of external connection areas and the first module connection area are disposed at different edges of the first main chip; the second chip module further includes a second additional chip electrically connected to the second integrated chipset, and the second main chip further includes a second set of external connection areas configured to be connected to the second additional chip, wherein the second set of external connection areas and the second module connection area are disposed at different edges of the second main chip.

[0006] In the packaging structure provided by at least one embodiment of the present disclosure, the first main chip and the second main chip each further include a second edge opposite to the first edge in the first direction, and the first set of external connection areas and the second set of external connection areas are respectively disposed on the second edge of the first main chip and the second edge of the second main chip; the first additional chip is disposed on the side of the first main chip away from the second main chip and facing the second edge of the first main chip, and the second additional chip is disposed on the side of the second main chip away from the first main chip and facing the second edge of the second main chip.

[0007] In the packaging structure provided according to at least one embodiment of this disclosure, the first additional chip and the second additional chip are memory chips.

[0008] In a packaging structure provided according to at least one embodiment of the present disclosure, the first group of internal connection regions is disposed in the second sub-edge region of the first edge of the first main core, and the first sub-core is disposed on one side of the second main core in the second direction and faces the second sub-edge region of the first main core in the first direction. The side edge of the first sub-core facing the first main core is provided with a first sub-connection region configured to be connected to the first group of internal connection regions; the second group of internal connection regions is disposed in the second sub-edge region of the first edge of the second main core, and the second sub-core is disposed on one side of the first main core in the second direction and faces the second sub-edge region of the second main core in the first direction. The side edge of the second sub-core facing the second main core is provided with a second sub-connection region configured to be connected to the second group of internal connection regions.

[0009] In the packaging structure provided according to at least one embodiment of the present disclosure, the first group of internal connection areas and the first inter-module connection areas of the first main chip are arranged along the second direction at the first edge of the first main chip; the second group of internal connection areas and the second inter-module connection areas of the second main chip are arranged along the second direction at the first edge of the second main chip; the first inter-module connection areas and the second inter-module connection areas are at least partially aligned in the first direction; the first group of internal connection areas and the first sub-connection areas are at least partially aligned in the first direction, and the second group of internal connection areas and the second sub-connection areas are at least partially aligned in the first direction.

[0010] In a packaging structure provided according to at least one embodiment of the present disclosure, the first sub-core is disposed on one side of the first main core in the second direction and faces the second sub-edge region of the second main core in the first direction; the first group of internal connection regions is disposed on the side edge of the first main core near the first sub-core, and the first sub-core has a first sub-connection region configured to be connected to the first group of internal connection regions on the side edge near the first main core; the second sub-core is disposed on one side of the second main core in the second direction and faces the second sub-edge region of the first main core in the first direction; the second group of internal connection regions is disposed on the side edge of the second main core near the second sub-core, and the second sub-core has a second sub-connection region configured to be connected to the second group of internal connection regions on the side edge near the second main core.

[0011] In the packaging structure provided according to at least one embodiment of the present disclosure, the first inter-module connection area of ​​the first main chip and the second inter-module connection area of ​​the second main chip are at least partially aligned in the first direction; the first group connection area of ​​the first main chip and the first sub-connection area of ​​the first sub-chip are at least partially aligned in the second direction; and the second group connection area of ​​the second main chip and the second sub-connection area of ​​the second sub-chip are at least partially aligned in the second direction.

[0012] In the encapsulation structure provided by at least one embodiment of this disclosure, the first inter-module connection area and the second inter-module connection area, the first group intra-connection area and the first sub-connection area, and the second group intra-connection area and the second sub-connection area each constitute a connection area group. The first inter-module connection area, the first group intra-connection area, and the second group intra-connection area are the first connection areas of the corresponding connection area groups, and the second inter-module connection area, the first sub-connection area, and the second sub-connection area are the second connection areas of the corresponding connection area groups. Each connection area group includes one or more transceiver interface groups, and each transceiver interface group includes a first transmitting interface and a first receiving interface located in the first connection area, and a second transmitting interface and a second receiving interface located in the second connection area. The first transmitting interface is electrically connected to the second receiving interface, and the first receiving interface is electrically connected to the second transmitting interface.

[0013] In the packaging structure provided according to at least one embodiment of the present disclosure, the first transmitting interface and the second receiving interface are at least partially aligned in the arrangement direction of the core in which the first connection area is located and the core in which the second connection area is located, and the first receiving interface and the second transmitting interface are at least partially aligned in the arrangement direction; or the first transmitting interface and the second receiving interface are offset but adjacent in a direction perpendicular to the arrangement direction, and the first receiving interface and the second transmitting interface are offset but adjacent in a direction perpendicular to the arrangement direction.

[0014] The packaging structure provided according to at least one embodiment of the present disclosure further includes at least one of the following: a first dummy chip disposed on one side of the first additional chip in the second direction and spaced apart from one of the first sub-chip and the second sub-chip in the first direction, the first dummy chip and the first additional chip having edges aligned in the second direction, and the first dummy chip having edges aligned in the first direction with one of the first sub-chip and the second sub-chip; a second dummy chip disposed on one side of the second additional chip in the second direction and spaced apart from the other of the first sub-chip and the second sub-chip in the first direction, the second dummy chip and the second additional chip having edges aligned in the second direction, and the second dummy chip having edges aligned in the first direction with the other of the first sub-chip and the second sub-chip.

[0015] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a connecting member disposed on one side of the first chip module and the second chip module in a third direction perpendicular to the first direction and the second direction, and providing electrical connection between a plurality of chips of the first chip module and the second chip module.

[0016] In the packaging structure provided according to at least one embodiment of the present disclosure, the connecting member includes an adapter board, and the adapter board provides electrical connections between multiple chips in the first chip module, between multiple chips in the second chip module, and between the first chip module and the second chip module.

[0017] According to at least one embodiment of the packaging structure provided in this disclosure, the connecting member includes: a first adapter plate and a second adapter plate, which are spaced apart on one side of the first chip module and the second chip module in a direction parallel to the main surfaces of the first chip module and the second chip module, the first adapter plate providing electrical connection between a plurality of chips in the first chip module, and the second adapter plate providing electrical connection between a plurality of chips in the second chip module; and a packaging substrate disposed on the side of the first adapter plate and the second adapter plate away from the first chip module and the second chip module, and providing electrical connection between the first chip module and the second chip module.

[0018] In the packaging structure provided according to at least one embodiment of the present disclosure, the first chip module and the second chip module are rotationally symmetrical to each other.

[0019] In the packaging structure provided by at least one embodiment of this disclosure, the orientation of each chip in the first chip module is the same as the orientation of each chip after the second chip module is rotated 180 degrees.

[0020] The packaging structure according to embodiments of this disclosure can improve package warpage and reduce interconnect distance. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1 A schematic plan view of a packaging structure according to some embodiments of the present disclosure is shown.

[0023] Figure 2 A schematic plan view of a packaging structure according to other embodiments of the present disclosure is shown.

[0024] Figures 3A to 3D A schematic plan view of a group of connection areas in an encapsulation structure according to some embodiments of the present disclosure is shown.

[0025] Figure 4 A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0026] Figure 5A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0027] Figure 6 A schematic plan view of a packaging structure according to some embodiments of the present disclosure is shown. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0030] Semiconductor packaging integrates multiple chips together using packaging technology. For some complex chips (e.g., system-on-a-chip), the chip occupies a large area, which can be referred to as a very large chip. Such very large chips can cause warping problems in the packaging structure to some extent. When integrating multiple chips into a single packaging structure, it is desirable to minimize the interconnection distance between the chips, thereby optimizing chip performance.

[0031] This disclosure provides a packaging structure, including: a first chip module, comprising: a first integrated chipset, the first integrated chipset including a first main chip and a first sub-chip connected to each other, the first main chip including a first inter-module connection area and a first set of internal connection areas configured to be connected to the first sub-chip; and a second chip module, comprising: a second integrated chipset, the second integrated chipset including a second main chip and a second sub-chip connected to each other, the second main chip including a second inter-module connection area and a second set of internal connection areas configured to be connected to the second sub-chip, the first chip module and the second chip module being connected to each other through transceiver interfaces respectively located in the first inter-module connection area and the second inter-module connection area; wherein the first chip module and the second chip module are connected to each other through transceiver interfaces located in the first inter-module connection area and the second inter-module connection area respectively; wherein the first chip module is connected to each other through transceiver interfaces located in the first inter-module connection area and the second inter-module connection area respectively. A primary core and a secondary core each have a first edge including a first sub-edge region and a second sub-edge region. A first inter-module connection region and a second inter-module connection region are respectively disposed in the first sub-edge region of the primary core and the first sub-edge region of the secondary core. The primary core and the secondary core are arranged along a first direction and partially offset in a second direction perpendicular to the first direction, such that the first sub-edge regions of the primary core and the secondary core face each other in the first direction, and the second sub-edge region of the primary core faces one of the primary core and the secondary core in the first direction, and the second sub-edge region of the secondary core faces the other of the primary core and the secondary core in the first direction.

[0032] In this embodiment, the integrated chips of each chip module are divided into main chips and sub-chips, and the main chips and sub-chips are interconnected and integrated in the package structure. Simultaneously, the connection areas between modules are all located at the first edge of each main chip, and the integrated chip groups of multiple chip modules adopt the above arrangement, thereby improving the warpage problem of the package and minimizing the connection paths between corresponding chips, i.e., shortening the interconnect length and increasing functional density. Furthermore, it optimizes the occupied area of ​​the chip modules, making the packaged device optimal in terms of performance, power consumption, and area. Moreover, the integrated chips... The chip is divided into main chips and sub-chips, and integrated into the package structure. This avoids the warpage problem caused by using a large-area single chip in the integrated chipset, thus further improving package warpage. The main chips and sub-chips can each select appropriate manufacturing processes based on their functional modules, optimizing process selection and improving process yield. Furthermore, the corresponding chips in each chip module (e.g., the first main chip and the second main chip) can be formed using approximately the same semiconductor process, thereby simplifying the manufacturing process while improving warpage and shortening interconnect lengths. In other words, this application, while further improving package warpage and optimizing process selection to reduce manufacturing costs by dividing the integrated chipset into main chips and sub-chips, optimizes the area occupied by each chip and chip module through appropriate arrangement. Even when the integrated chipset is divided into multiple chips, there is still a small interconnect length between the main chips and sub-chips, as well as between different chip modules, thereby increasing functional density and further optimizing the package structure in terms of performance, power consumption, and area.

[0033] Figure 1 A schematic plan view of a packaging structure according to some embodiments of the present disclosure is shown; Figure 2 A schematic plan view of a packaging structure according to other embodiments of the present disclosure is shown.

[0034] refer to Figure 1 and Figure 2 In some embodiments, the package structure 500 includes a first chip module M1 and a second chip module M2, each having multiple chips. For example, the first chip module M1 includes a first integrated chipset IC1, which includes a first main chip 100 and a first sub-chip 101 connected to each other. The second chip module M2 includes a second integrated chipset IC2, which includes a second main chip 200 and a second sub-chip 201 connected to each other. In some embodiments, a chip may also be referred to as a small chip.

[0035] The number and type of chips in each chip module can be selected according to product requirements; for example, multiple chips in a chip module may include one or more of the following: System on Chip (SoC), Digital Signal Processor (DSP) chip, Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC) chip, High Bandwidth Memory (HBM) and other memory chips, Central Processing Unit (CPU), Tensor Processing Unit (TPU), Neural Network Processing Unit (NPU), Deep Learning Processing Unit (DPU), Accelerated Processing Unit (APU), General-Purpose Computing on Graphics Processing Unit (GPGPU), chip modules, intelligent inference chips, intelligent training chips, edge computing GPU chips, general-purpose CPU chips, and specific CPU chips.

[0036] For example, an integrated chipset is a complex chip comprising multiple functional modules. This complex chip can be broken down into multiple chips (i.e., small chips), each with its own functional modules to perform a specific function. These chips are then interconnected using packaging technology to form a complete chip, achieving full chip functionality. For instance, integrated chipsets can be system-on-a-chip (SoC), high-performance computing (HPC) chips, or similar devices. In some examples, using a single chip might result in a large area of ​​the complex chip, potentially causing warpage in the package structure. Compared to using a single chip, breaking down the integrated chip into multiple chips can improve package warpage. Furthermore, each chip can select an appropriate manufacturing process based on its own functional modules, thus optimizing process selection, improving process yield, and reducing manufacturing costs to some extent.

[0037] For example, the logic functions and input / output functions of each integrated chipset can be separated and implemented by individual chips. For example, the main chip in each integrated chipset can be a logic chip that includes logic circuits; the sub-chips can be input / output chips that include input / output (I / O) circuits. For example, the first main chip 100 and the second main chip 200 can each be logic chips, and the first sub-chip 101 and the second sub-chip 201 can each be input / output chips.

[0038] In some embodiments, the main chip of each integrated chipset includes an intra-group connection area for electrical connections between chips within the group, and an inter-module connection area for electrical connections between modules. Herein, a connection area refers to a connector (e.g., a transceiver interface) configured to electrically connect to other components (e.g., other chips or components); a connection area configured to connect to other chips or components means that the corresponding connector in the connection area is configured to connect to other chips or components.

[0039] For example, in the first integrated chipset IC1 of the first chip module M1, the first main chip 100 includes a first set of internal connection areas 11 and a first inter-module connection area 13. The first set of internal connection areas 11 is configured to connect with the first sub-chip 101. The first inter-module connection area 13 is configured to connect with other chip modules (e.g., the second chip module M2).

[0040] For example, in the second integrated chipset IC2 of the second chip module M2, the second main chip 200 includes a second set of internal connection areas 21 and a second inter-module connection area 23. The second set of internal connection areas 21 is configured to connect with the second sub-chip 201. The second inter-module connection area 23 is configured to connect with other chip modules (e.g., the first chip module M1).

[0041] In some embodiments, the first chip module M1 and the second chip module M2 are connected to each other through transceiver interfaces located in the first inter-module connection area 13 and the second inter-module connection area 23, respectively.

[0042] Continue to refer to Figure 1 and Figure 2For example, the first main chip 100 and the second main chip 200 each have a first edge S1, a second edge S2, a third edge S3, and a fourth edge S4, each including a first sub-edge region S1a and a second sub-edge region S1b. A first inter-module connection region 13 is disposed in the first sub-edge region S1a of the first main chip 100, and a second inter-module connection region 23 is disposed in the first sub-edge region S1a of the second main chip 200. For example, in each main chip, the second edge S2 and the first edge S1 are opposite each other in a first direction D1 and each extends along a second direction D2; the third edge S3 and the fourth edge S4 are opposite each other in the second direction D2 and each extends along the first direction D1. In some examples, the first and second main chips have a square planar shape, and the third edge S3 and the fourth edge S4 are each connected to the first edge S1 and the second edge S2. It should be understood that the edge of a chip or chip includes the sidewall of the chip or chip and the region adjacent to that sidewall.

[0043] In some embodiments, multiple chips and dies in multiple chip modules are arranged side-by-side at intervals in a direction parallel to the main surface of the chip module (i.e., the main surface of each chip and / or die). For example, a first main die 100 and a second main die 200 are arranged along a first direction D1 and partially offset in a second direction D2 perpendicular to the first direction D1, such that a first sub-edge region S1a of the first main die 100 and a first sub-edge region S1a of the second main die 200 face each other in the first direction D1, while a second sub-edge region S1b of the first main die 100 and a second sub-edge region S1b of the second main die 200 are offset from each other in the second direction D2. The first direction D1 and the second direction D2 may both be directions parallel to the main surface of each chip (e.g., horizontal directions).

[0044] For example, the second sub-edge region S1b of the first main core 100 extends beyond the third edge S3 of the second main core 200 in the second direction D2, and faces one of the first sub-core 101 and the second sub-core 201 in the first direction D1. The second sub-edge region S1b of the second main core 200 extends beyond the third edge S3 of the first main core 100 in the second direction D2, and faces the other of the first sub-core 101 and the second sub-core 201 in the first direction D1.

[0045] For example, such as Figure 1As shown, in some examples, a first main core 100 and a first sub-core 101 are arranged along a first direction D1, and the second sub-edge region S1b of the first main core 100 faces the first sub-core 101 in the first direction D1; a second main core 200 and a second sub-core 201 are arranged along the first direction D1, and the second sub-edge region S1b of the second main core 200 faces the second sub-core 201 in the first direction D1. In this example, the first sub-core 101 overlaps with the second main core 200 in the second direction D2; the second sub-core 201 overlaps with the first main core 100 in the second direction D2. In this document, the overlap of multiple components in a certain direction means the overlap of the orthographic projections of the multiple components on a reference plane perpendicular to that direction. In other words, the orthographic projections of the first sub-core 101 and the second main core 200 onto a reference plane perpendicular to the second direction D2 (e.g., the extension plane of the fourth edge S4 of the second main core) overlap each other; the orthographic projections of the second sub-core 201 and the first main core 100 onto a reference plane perpendicular to the second direction D2 (e.g., the extension plane of the fourth edge S4 of the first main core) overlap each other.

[0046] For example, such as Figure 2 As shown, in some other examples, the first main core 100 and the first sub-core 101 are arranged along the second direction D2. For example, the first sub-core 101 is arranged on the side near the third edge S3 of the first main core 100. The second main core 200 and the second sub-core 201 are arranged along the second direction D2. For example, the second sub-core 201 is arranged on the side near the third edge S3 of the second main core 200. In this example, the second sub-edge region S1b of the first main core 100 faces the second sub-core 201 in the first direction D1; the second sub-edge region S1b of the second main core 200 faces the first sub-core 101 in the first direction D1.

[0047] In some embodiments, the first chip module further includes a first additional chip electrically connected to the first integrated chipset, and the first main chip further includes a first set of external connection areas configured to be connected to the first additional chip, the first set of external connection areas and the first module connection area being disposed at different edges of the first main chip; the second chip module further includes a second additional chip electrically connected to the second integrated chipset, and the second main chip further includes a second set of external connection areas configured to be connected to the second additional chip, the second set of external connection areas and the second module connection area being disposed at different edges of the second main chip.

[0048] For example, a first auxiliary chip is disposed on the side of the first main chip away from the second main chip and facing the second edge of the first main chip, and a second auxiliary chip is disposed on the side of the second main chip away from the first main chip and facing the second edge of the second main chip. For example, the first and second auxiliary chips are memory chips, such as HBM chips.

[0049] refer to Figure 1 and Figure 2 For example, the first chip module M1 further includes one or more first auxiliary chips 102 electrically connected to the first integrated chipset IC1, and the first main chip 100 further includes a first set of external connection areas 12 configured to connect to the first auxiliary chips 102. For example, the first set of external connection areas 12 and the first inter-module connection area 13 may be located at different edges of the first main chip 100, and the first set of external connection areas 12 and the first set of internal connection areas 11 may also be located at different edges of the first main chip 100.

[0050] For example, the first set of external connection areas 12 may be disposed on the second edge S2 of the first main chip 100 opposite to the first edge S1. Correspondingly, the first auxiliary chip 102 is disposed on the side of the first main chip 100 away from the second main chip 200 and facing the second edge S2 of the first main chip 100. For example, the first set of external connection areas 12 may be or include a physical layer (PHY) that is communicatively connected to the first auxiliary chip 102, and may include functional circuitry for transmitting signals / data.

[0051] In some embodiments, a plurality of first additional chips 102 are disposed on one side of the first main chip 100, and the plurality of first additional chips 102 may be arranged along a second direction D2.

[0052] In some embodiments, the second chip module M2 further includes one or more second additional chips 202 electrically connected to the second integrated chipset IC2, and the second main chip 200 further includes a second set of external connection regions 22 configured to connect to the second additional chips 202. For example, the second set of external connection regions 22 and the inter-module connection region 23 are disposed at different edges of the second main chip 200, and the second set of external connection regions 22 and the second set of internal connection regions 21 may also be disposed at different edges of the second main chip 200.

[0053] For example, the second set of external connection areas 22 may be disposed on the second edge S2 of the second main chip 200 opposite to the first edge S1. Correspondingly, the second additional chip 202 is disposed on the side of the second main chip 200 away from the first main chip 100 and facing the second edge S2 of the second main chip 200. In some embodiments, a plurality of second additional chips 202 are disposed on one side of the second main chip 200, and the plurality of second additional chips 202 may be arranged along the second direction D2. For example, the second set of external connection areas 22 may be or include a physical layer (PHY) that is communicatively connected to the second additional chips 202, and may include functional circuitry for transmitting signals / data. For example, each additional chip may also have a connection area (not shown) connected to the main chip on one edge near the main chip.

[0054] In some embodiments, the first additional chip 102 and the second additional chip 202 may be memory chips such as high-bandwidth memory (HBM) chips.

[0055] In some embodiments, the number of first additional chips and the number of second additional chips may be equal. It should be understood that the number of first additional chips and second additional chips shown in the figures are merely illustrative and are not intended to limit the scope of this disclosure.

[0056] In some embodiments, a first set of internal connection regions is disposed in a second sub-edge region of a first edge of a first main core, and a first sub-core is disposed on one side of a second main core in a second direction and faces the second sub-edge region of the first main core in the first direction. The side edge of the first sub-core facing the first main core is provided with a first sub-connection region configured to be connected to the first set of internal connection regions. A second set of internal connection regions is disposed in a second sub-edge region of a first edge of a second main core, and a second sub-core is disposed on one side of a first main core in a second direction and faces the second sub-edge region of the second main core in the first direction. The side edge of the second sub-core facing the second main core is provided with a second sub-connection region configured to be connected to the second set of internal connection regions.

[0057] For example, the first set of internal connection regions and the first inter-module connection region of the first main core are arranged along the second direction at the first edge of the first main core; the second set of internal connection regions and the second inter-module connection region of the second main core are arranged along the second direction at the first edge of the second main core; the first inter-module connection region and the second inter-module connection region are at least partially aligned in the first direction; the first set of internal connection regions and the first sub-connection region are at least partially aligned in the first direction, and the second set of internal connection regions and the second sub-connection region are at least partially aligned in the first direction.

[0058] For example, refer to Figure 1The first sub-core 101 is disposed on one side of the second main core 200 in the second direction D2, for example, near the third edge S3 of the second main core 200, and the first sub-core 101 faces the second sub-edge region S1b of the first main core 100 in the first direction D1. For example, the first group of inner connection regions 11 of the first main core 100 is disposed in its second sub-edge region S1b, and the side edge of the first sub-core 101 facing the first main core 100 is provided with a first sub-connection region 11', which is configured to be connected to the first group of inner connection regions 11. That is, the first main core 100 and the first sub-core 101 are interconnected through the first group of inner connection regions 11 and the first sub-connection region 11'. For example, based on product design requirements, the interconnection of the first main core 100 and the first sub-core 101 can be achieved through a SerDes PHY, a UCIE PHY, or an interface circuit with the same or similar functions.

[0059] In some embodiments, the second sub-core 201 is disposed on one side of the first main core 100 in the second direction D2, for example, near the third edge S3 of the first main core 100, and the second sub-core 201 faces the second sub-edge region S1b of the second main core 200 in the first direction D1. For example, the second group of inner connection regions 21 of the second main core 200 is disposed in its second sub-edge region S1b, and a second sub-connection region 21' is disposed on the side edge of the second sub-core 201 facing the second main core 200, and the second sub-connection region 21' is configured to be connected to the second group of inner connection regions 21. That is, the second main core 200 and the second sub-core 201 are interconnected through the second group of inner connection regions 21 and the second sub-connection region 21'. For example, based on product design requirements, the interconnection of the second main core 200 and the second sub-core 201 can be achieved through a SerDes PHY, a UCIE PHY, or an interface circuit with the same or similar functions.

[0060] The above settings minimize the interconnection distance between the main chip and the sub-chip in each integrated chipset.

[0061] In some embodiments, the first group of internal connection regions 11 and the first inter-module connection region 13 of the first main core 100 are arranged along the second direction D2 at the first edge of the first main core 100; the second group of internal connection regions 21 and the second inter-module connection region 23 of the second main core 200 are arranged along the second direction D2 at the second edge of the second main core 200. The first inter-module connection region 13 of the first main core 100 may be substantially aligned with the second inter-module connection region 23 of the second main core 200 in the first direction D1; the first group of internal connection regions 11 of the first main core 100 may be substantially aligned with the first sub-connection region 11' of the first sub-core 101 in the first direction D1; the second group of internal connection regions 21 of the second main core 200 may be substantially aligned with the second sub-connection region 21' of the second sub-core 201 in the first direction D1. In this document, the substantial alignment of multiple components or regions in a certain direction includes at least partial alignment of the multiple components or regions in that direction, i.e., including cases of complete or partial alignment, i.e., the orthographic projections of these components or regions onto a reference plane perpendicular to that direction may completely or partially overlap.

[0062] In this embodiment, the intra-group connection area and inter-module connection area of ​​each main core are set on the same edge of the main core, which can optimize the arrangement of the connection area to a certain extent. In addition, the corresponding connection areas are respectively set on the edges of each core facing each other and are roughly aligned with each other in the core arrangement direction, which can reduce (e.g., minimize) the interconnection distance between cores.

[0063] In other embodiments, a first sub-core is disposed on one side of a first main core in a second direction and faces a second sub-edge region of a second main core in a first direction. A first set of internal connection regions is disposed on the side edge of the first main core near the first sub-core, and the first sub-core has a first sub-connection region configured to be connected to the first set of internal connection regions on the side edge near the first main core. A second sub-core is disposed on one side of a second main core in a second direction and faces a second sub-edge region of the first main core in a first direction. A second set of internal connection regions is disposed on the side edge of the second main core near the second sub-core, and the second sub-core has a second sub-connection region configured to be connected to the second set of internal connection regions on the side edge near the second main core.

[0064] For example, the first inter-module connection area of ​​the first main core is substantially aligned with the second inter-module connection area of ​​the second main core in a first direction; the first group of internal connection areas of the first main core is at least partially aligned with the first sub-connection area of ​​the first sub-core in a second direction; and the second group of internal connection areas of the second main core is at least partially aligned with the second sub-connection area of ​​the second sub-core in a second direction.

[0065] For example, refer to Figure 2In other embodiments, the first sub-core 101 is disposed on one side of the first main core 100 in the second direction D2, for example near the third edge S3 of the first main core 100, and faces the second sub-edge region S1b of the second main core 200 in the first direction D1. The first group of inner connection regions 11 of the first main core 100 may be disposed on one side edge of the first main core 100 near the first sub-core (e.g., the third edge S3), and the first sub-core 101 has a first sub-connection region 11' configured to be connected to the first group of inner connection regions 11 on one side edge near the first main core 100.

[0066] The second sub-core 201 is disposed on one side of the second main core 200 in the second direction D2, for example, near the third edge S3 of the second main core 200, and faces the second sub-edge region S1b of the first main core 100 in the first direction D1. The second group of inner connection regions 21 of the second main core 200 may be disposed on one side edge of the second main core 200 near the second sub-core (e.g., the third edge S3), and the second sub-core 201 has a second sub-connection region 21' configured to be connected to the second group of inner connection regions 21 on one side edge near the second main core 200.

[0067] In this embodiment, the first inter-module connection area 13 of the first main core 100 and the second inter-module connection area 23 of the second main core 200 are also substantially aligned in the first direction D1. The first group of internal connection areas 11 of the first main core 100 and the first sub-connection area 11' of the first sub-core 101 are substantially aligned in the second direction D2. The second group of internal connection areas 21 of the second main core 200 and the second sub-connection area 21' of the second sub-core 201 are substantially aligned in the second direction D2.

[0068] In this embodiment of the disclosure, the interconnection distance between the corresponding interconnection areas is minimized by aligning the interconnection areas that are configured to be connected to each other in their arrangement direction.

[0069] In some embodiments, the first inter-module connection area and the second inter-module connection area, the first group intra-connection area and the first sub-connection area, the second group intra-connection area and the second sub-connection area each constitute a connection area group. The first inter-module connection area, the first group intra-connection area and the second group intra-connection area are the first connection areas of the corresponding connection area groups, and the second inter-module connection area, the first sub-connection area and the second sub-connection area are the second connection areas of the corresponding connection area groups. Each connection area group includes one or more transceiver interface groups. Each transceiver interface group includes a first transmitting interface and a first receiving interface located in the first connection area, and a second transmitting interface and a second receiving interface located in the second connection area. The first transmitting interface is electrically connected to the second receiving interface, and the first receiving interface is electrically connected to the second transmitting interface.

[0070] For example, the first transmitting interface and the second receiving interface are at least partially aligned in the arrangement direction of the core where the first connection area is located and the core where the second connection area is located, and the first receiving interface and the second transmitting interface are at least partially aligned in the arrangement direction; or the first transmitting interface and the second receiving interface are offset but adjacent in a direction perpendicular to the arrangement direction, and the first receiving interface and the second transmitting interface are offset but adjacent in a direction perpendicular to the arrangement direction.

[0071] For example, refer to Figure 1 and Figure 2 In some embodiments, interconnected connection areas form connection area groups, and each connection area group includes a first connection area and a second connection area. For example, a first inter-module connection area 13 and a second inter-module connection area 23 form a connection area group, wherein the first inter-module connection area 13 and the second inter-module connection area 23 are respectively the first connection area and the second connection area of ​​the connection area group. A first group of connection areas 11 and a first sub-connection area 11' form a connection area group, wherein the first group of connection areas 11 and the first sub-connection area 11' are respectively the first connection area and the second connection area of ​​the connection area group. A second group of connection areas 21 and a second sub-connection area 21' form a connection area group, wherein the second group of connection areas 21 and the second sub-connection area 21' are respectively the first connection area and the second connection area of ​​the connection area group.

[0072] In some embodiments, each connection area group includes one or more transceiver interface groups 30, and each transceiver interface group 30 includes a first transceiver interface located in a first connection area and a second transceiver interface located in a second connection area. For example, the first transceiver interface includes a first transmit interface 1 and a first receive interface 2, and the second transceiver interface includes a second transmit interface 1' and a second receive interface 2'. In this embodiment, each transceiver interface includes a separate transmit interface and a receive interface, the transmit interface being used to transmit signals and the receive interface being used to receive signals, but this disclosure is not limited thereto. In other embodiments, each transceiver interface may also be a single transceiver interface that integrates transmit and receive functions, and may have the functions of transmitting and receiving signals simultaneously. This disclosure does not limit the specific type of transceiver interface. The following description uses the example of each transceiver interface including a separate transmit interface and a receive interface to illustrate the connection between the first connection area and the second connection area in the connection area group.

[0073] Figures 3A to 3D A schematic enlarged plan view of a transceiver interface group in a connection area group according to some embodiments of the present disclosure is shown. It should be noted that... Figures 3A to 3D The orientation of the corresponding connecting area shown in the figure is... Figure 1 and Figure 2 The diagrams shown may be the same or different, but the relative positions of the first and second connecting regions in the connecting region group are the same in all diagrams.

[0074] refer to Figure 1 , Figure 2 and Figures 3A to 3D In each transceiver interface group, a first transmitting interface 1 is electrically connected to a second receiving interface 2', and a first receiving interface 2 is electrically connected to a second transmitting interface 1'. In the interconnected transmitting and receiving interfaces, the transmitting interface is configured to transmit signals from its own chip, for example, to the chip containing the receiving interface, and the receiving interface is configured to receive signals from other chips, for example, signals from the transmitting interface.

[0075] For example, the first connection region and the second connection region in the connection region group can be referred to as the first connection region CR1 and the second connection region CR2, respectively. The arrangement direction of the chip (e.g., the die) where the first connection region CR1 is located and the chip (e.g., the die) where the second connection region CR2 is located in the connection region group is referred to as the arrangement direction AD1, and the direction perpendicular to the arrangement direction AD1 is referred to as the reference direction AD2.

[0076] For example, in Figure 1 In the illustrated embodiment, the arrangement direction AD1 of the multiple connection groups is all the first direction D1, and the corresponding reference direction AD2 is the second direction D2. Figure 2 In the illustrated embodiment, for the connection area group consisting of the first inter-module connection area 13 and the second inter-module connection area 23, the arrangement direction AD1 is the first direction D1, and the reference direction AD2 is the second direction D2; while for the connection area group consisting of the first group inner connection area 11 and the first sub-connection area 11' or the connection area consisting of the second group inner connection area 21 and the second sub-connection area 21', the arrangement direction AD1 is the second direction D2, and the corresponding reference direction AD2 is the first direction D1.

[0077] refer to Figure 3A In some examples, the first transmitting interface 1 and the second receiving interface 2' overlap and are substantially aligned (e.g., fully aligned) with each other in the arrangement direction AD1. For example, the opposite sidewalls of the first transmitting interface 1 in the reference direction AD2 are substantially aligned with the opposite sidewalls of the second receiving interface 2' in the reference direction AD2 in the arrangement direction AD1. The first conductive trace L1 is disposed between the first transmitting interface 1 in the first connection area CR1 and the second receiving interface 2' in the second connection area CR2, and is used to transmit data / signals from the first transmitting interface 1 to the second receiving interface 2'. A plurality of first conductive traces L1 extend in the arrangement direction AD1, for example, substantially parallel to each other.

[0078] For example, the first receiving interface 2 and the second transmitting interface 1' overlap and are substantially aligned (e.g., fully aligned) with each other in the arrangement direction AD1. For example, the opposite sidewalls of the first receiving interface 2 in the reference direction AD2 are substantially aligned with the opposite sidewalls of the second transmitting interface 1' in the reference direction AD2 in the arrangement direction AD1; a second conductive trace L2 is disposed between the first receiving interface 2 in the first connection area CR1 and the second transmitting interface 1' in the second connection area CR2, and is used to transmit data / signals from the second transmitting interface 1' to the first receiving interface 2; a plurality of second conductive traces L2 extend, for example, substantially parallel to each other in the arrangement direction AD1. The first conductive traces L1 and the second conductive traces L2 are, for example, conductive traces disposed in a connecting member, which will be described in detail below.

[0079] refer to Figure 3B In some embodiments, in a transceiver interface group, a set of transmit and receive interfaces connected to each other may overlap and partially align with each other in the arrangement direction AD1 (i.e., partially overlap). That is, the opposite sidewalls of the transmit interface in the reference direction AD2 and the opposite sidewalls of the receive interface in the reference direction AD2 may not be aligned with each other in the first direction D1, but rather offset from each other in the reference direction AD2. In this embodiment, a plurality of first conductive traces L1 and second conductive traces L2 located between the corresponding transmit and receive interfaces may also extend substantially parallel to each other along the first direction D1, but this disclosure is not limited thereto.

[0080] For example, such as Figure 3C As shown, in some embodiments where a set of interconnected transmit and receive interfaces overlap but are not fully aligned in the arrangement direction AD1, multiple first conductive traces L1 and second conductive traces L2 may extend in directions intersecting the first direction D1 and the second direction D2, and may be substantially parallel to each other.

[0081] refer to Figure 3D In other embodiments, in the transceiver interface group, a set of transmitting and receiving interfaces connected to each other may also be positioned in corresponding positions without overlapping each other in the arrangement direction AD1; for example, the first transmitting interface 1 and the second receiving interface 2' are offset but adjacent in the reference direction AD2, and the first receiving interface 2 and the second transmitting interface 1' are offset but adjacent in the reference direction AD2; in this way, multiple first conductive traces L1 and second conductive traces L2 located between the corresponding transmitting and receiving interfaces can be arranged parallel to each other without crossing each other, and for example, they extend parallel to each other in the direction intersecting the arrangement direction AD1 and the reference direction AD2.

[0082] It should be understood that the number of transceiver interface groups in each connection area group shown in the figure, as well as the number of transmit and receive interfaces in each transceiver interface group, are merely illustrative examples and are not intended to limit the scope of this disclosure. For example, each connection area group may include one or more transceiver interface groups based on product design and requirements, and each transceiver interface group may include one or more sets of transmit and receive interfaces. For example, each connection area may include transmit and receive interfaces arranged alternately along a reference direction, and the alternation of transmit and receive interfaces along the reference direction includes the case of alternating single transmit interfaces and single receive interfaces, as well as the case of alternating transmit interface groups containing n transmit interfaces and receive interface groups containing m receive interfaces (n>1, m>1, and m=n). For example, when a single transmit interface and a single receive interface are arranged alternately, the alternating transmit and receive interfaces include transmit interfaces, receive interfaces, transmit interfaces, receive interfaces, ... (or receive interfaces, transmit interfaces, receive interfaces, transmit interfaces, ...) arranged sequentially in the reference direction. Moreover, it may also include the case where only one transmit interface and only one receive interface are arranged side by side. When a transmit interface group containing n transmit interfaces and a receive interface group containing m receive interfaces are arranged alternately, for example, n=m=2, the alternating transmit and receive interfaces include, for example, transmit interfaces, transmit interfaces, receive interfaces, receive interfaces, ... arranged sequentially in the reference direction, or receive interfaces, receive interfaces, transmit interfaces, transmit interfaces, ... arranged sequentially in the said direction, and so on. Moreover, it may also include the case where only one transmit interface group and one receive interface group are arranged.

[0083] In some embodiments, the first sub-chip 101 may further include a first interface region 15 disposed on the edge of the first sub-chip 101 away from the corresponding main chip (i.e., the main chip disposed adjacent to it in the second direction), and the second sub-chip 201 may further include a second interface region 25 disposed on the edge of the second sub-chip 201 away from the corresponding main chip (i.e., the main chip disposed adjacent to it in the second direction). The interface region of the sub-chip may include input / output interfaces, such as PCIEPHY, Ethernet PHY, and other interface circuits, but this disclosure is not limited thereto. The input / output interfaces of the sub-chip may be interfaces used for integrating chipsets and other components for input / output.

[0084] In some embodiments, the first chip module and the second chip module may be rotationally symmetrical to each other. For example, the first chip module may be in the same orientation as the second chip module after rotating 180 degrees. The first main chip and the second main chip may be formed by the same semiconductor process and may have approximately the same chip structure. In this way, after rotating 180 degrees, the transceiver interface of the inter-module connection area of ​​the second main chip may correspond exactly to the inter-module connection area of ​​the first main chip, so that the transceiver interfaces in the second main chip and the first main chip are correspondingly set (e.g., approximately aligned in the arrangement direction), thereby minimizing the interconnection distance between the first and second main chips. Or even if the corresponding transmit interface and receive interface are not aligned in the arrangement direction, they can be in the corresponding positions, so that the conductive traces between the transmit interface and the receive interface can be set in parallel instead of crossing. This makes the data / signal transmission path between the transmit interface and the receive interface relatively short, thereby improving the data / signal transmission speed and thus improving the device performance.

[0085] In some embodiments, the package structure further includes one or more dummy chips to fill relatively empty areas in the plurality of chip modules, thereby further improving package warpage. For example, the package structure further includes at least one of the following: a first dummy chip disposed on one side of the first additional chip in a second direction and spaced apart from one of the first sub-chips and the second sub-chip in the first direction, the first dummy chip and the first additional chip having substantially aligned edges in the second direction, and the first dummy chip having substantially aligned edges with one of the first sub-chips and the second sub-chip in the first direction; a second dummy chip disposed on one side of the second additional chip in a second direction and spaced apart from the other of the first sub-chips and the second sub-chip in the first direction, the second dummy chip and the second additional chip having substantially aligned edges in the second direction, and the second dummy chip having substantially aligned edges with the other of the first sub-chips and the second sub-chip in the first direction. It should be understood that edge alignment of the plurality of chips and / or dies refers to the alignment of the corresponding sidewalls of the plurality of chips and / or dies.

[0086] For example, refer to Figure 1 The package structure 500 may include a first dummy chip 103 and a second dummy chip 203. The first dummy chip 103 is disposed on one side of the first auxiliary chip 102 in a second direction D2 and is spaced apart from the second sub-chip 201 in a first direction D1. For example, the first dummy chip 103 and the first auxiliary chip 102 have edges that are substantially aligned in the second direction D2. The first dummy chip 103 and the second sub-chip 201 have edges that are substantially aligned in the first direction D1. In some embodiments, the dummy chip may be or include a chip in which no active or passive devices are disposed, i.e., no electrical functions or other functions, but is primarily configured to improve warpage or stress structures.

[0087] In some embodiments, the overall width of one or more first additional chips 102 in the second direction D2 may be approximately equal to the width of the first main chip 100 in the second direction D2, and the second sub-chip 201 has an edge aligned with the first edge S1 of the first main chip 100 in the second direction D2. The width of the second sub-chip 201 in the first direction D1 may be less than the overall width of the first main chip 100 and the first additional chips 102 in the first direction D1. For example, the overall width of the first dummy chip 103 and the second sub-chip 201 in the first direction D1 may be approximately equal to the overall width of the first additional chip 102 and the first main chip 100 in the first direction D1; for example, the width of the first dummy chip 103 in the second direction D2 may be approximately equal to the width of the second sub-chip 201 in the second direction D2. It should be understood that the overall width of a plurality of chips / chips in a certain direction is equal to the sum of the width of the plurality of chips / chips in that direction and the spacing between adjacent chips / chips in that direction.

[0088] For example, the second dummy chip 203 is disposed on one side of the second auxiliary chip 202 in the second direction D2, and is spaced apart from the first sub-chip 101 in the first direction D1. For example, the second dummy chip 203 and the second auxiliary chip 202 have edges that are substantially aligned in the second direction D2. The second dummy chip 203 and the first sub-chip 101 have edges that are substantially aligned in the first direction D1.

[0089] In some embodiments, the overall width of one or more second additional chips 202 in the second direction D2 may be approximately equal to the width of the second main chip 200 in the second direction D2, and the first sub-chip 101 has an edge aligned with the first edge S1 of the second main chip 200 in the second direction D2. The width of the first sub-chip 101 in the first direction D1 may be less than the overall width of the second main chip 200 and the second additional chips 202 in the first direction D1. For example, the overall width of the second dummy chip 203 and the first sub-chip 101 in the first direction D1 may be approximately equal to the overall width of the second additional chip 202 and the second main chip 200 in the first direction D1; for example, the width of the second dummy chip 203 in the second direction D2 may be approximately equal to the width of the first sub-chip 101 in the second direction D2.

[0090] In some embodiments, the corresponding chips or dies in each chip module have substantially the same structure, size, and number, and can be formed by the same semiconductor process, for example, they can be formed from the same wafer. For example, the first main die 100 and the second main die 200 may have substantially the same structure and size, and can be formed from the same wafer by the same semiconductor process; the first sub-die 101 and the second sub-die 201 may have substantially the same structure and size, and can be formed from the same wafer by the same semiconductor process; the first additional chip 102 and the second additional chip 202 may have substantially the same structure and size, and can be formed from the same wafer by the same semiconductor process; the first dummy chip 103 and the second dummy chip 203 may have substantially the same structure and size, and can be formed from the same wafer by the same semiconductor process. For example, the number of main dies in each chip module may be the same, the number of sub-dies may be the same, the number of additional chips may be the same, and the number of dummy chips may be the same.

[0091] In some embodiments, the fourth edge S4 of the first master chip 100 is substantially aligned with the corresponding edges of the first auxiliary chip 102, the first sub-chip 101, and the second dummy chip 203 in the first direction D1; the fourth edge S4 of the second master chip 200 is substantially aligned with the corresponding edges of the second auxiliary chip 202, the second sub-chip 201, and the first dummy chip 103 in the first direction D1.

[0092] In this embodiment, the second dummy chip 203 can be considered as part of the first chip module M1, and the first dummy chip 103 can be considered as part of the second chip module M2. In this case, the outlines of the first and second chip modules are roughly L-shaped, and the chip module formed by the combination of the first and second chip modules is roughly square. Alternatively, the first dummy chip 103 can be considered as part of the first chip module M1, and the second dummy chip 203 can be considered as part of the second chip module M2. In this case, the outlines of the first and second chip modules are similar to a combination of two L-shaped shapes, and the chip module formed by the combination of the first and second chip modules is roughly square.

[0093] The embodiments disclosed herein, through the above-described arrangement of each chip / chip, enable the corresponding connection areas of the first and second chip modules to be arranged correspondingly to each other after orientation rotation, thereby reducing the interconnection distance and forming an overall outline with a roughly regular shape, thereby optimizing the occupied area of ​​the chip module and improving package warpage.

[0094] It should be understood that the number and location of the dummy chips shown in the figures are merely illustrative examples, and this disclosure is not limited thereto. For example, in other examples, the main chip may extend beyond the edge of the corresponding sub-chip in a second direction, and a dummy chip may also be provided on one side of the sub-chip, thereby giving the chip module composed of multiple chip modules and multiple dummy chips a more regular profile, which can improve package warpage. In other embodiments, the multiple chip modules themselves already have a more regular profile, so the dummy chips can be omitted.

[0095] Figure 2 In the embodiments, the configuration of the first dummy chip 103 and the second dummy chip 203 is similar to... Figure 1 Similar to the example shown, except that the positions of the first sub-core 101 and the second sub-core 201 are different. Figure 1 The embodiments are interchangeable. In this embodiment, the positional relationship between the first sub-chip 101 and other chips / chips such as the first dummy chip 103 is the same as... Figure 1 In the illustrated embodiment, the positional relationship between the second sub-chip 201 and other chips / chips such as the first dummy chip 103 is similar. Figure 1 The positional relationship between the first sub-chip 101 and other chips / chips such as the second dummy chip 203 in the illustrated embodiment is similar and will not be described again here.

[0096] exist Figure 2 In the illustrated embodiment, the first dummy chip 103 can be considered as part of the first chip module M1, and the second dummy chip 203 can be considered as part of the second chip module M2. The overall outline of the first chip module M1 can be square, the overall outline of the second chip module M2 can be square, and the module as a whole composed of the first chip module M1 and the second chip module M2 can also have a square outline. In this way, the individual outlines of the multiple chip modules and the overall outline can be relatively regular shapes, thereby further simplifying the arrangement of the chip modules and the chip modules. In this document, square can be a square or a rectangle. The outline of the multiple chips or chip modules includes the outline formed by the lines connecting the outer edges (i.e., outer walls) of the corresponding multiple chips.

[0097] In some embodiments, the packaging structure further includes a connecting member disposed on one side of the first chip module and the second chip module in a third direction perpendicular to the first and second directions, and providing electrical connections between a plurality of chips in the first and second chip modules. For example, the connecting member includes an adapter board, which provides electrical connections between a plurality of chips within the first chip module, between a plurality of chips within the second chip module, and between the first and second chip modules. It should be understood that a chiplet can also be referred to as a small chip, and the plurality of chips here includes a plurality of chips and / or a plurality of chipslets.

[0098] Figure 4 A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown; for example, Figure 4 Can be along Figure 1 and Figure 2 The corresponding profile lines (e.g., Figure 2 The cross-sectional view is taken from line A-A'. It should be understood that, for the sake of simplicity, the additional chip and dummy chip are not shown in the cross-sectional view.

[0099] refer to Figure 1 , Figure 2 and Figure 4 In some embodiments, the package structure 500 may be a chip-on-wafer-on-substrate (CoWoS) package, and further includes an adapter plate 300 and a package substrate 400. For example, the adapter plate 300 is located on one side of a plurality of chip modules in a third direction D3 perpendicular to the main surface of the chips, and the package substrate 400 is disposed on the side of the adapter plate 300 away from the chip modules. The third direction D3 is perpendicular to the plane containing the first direction D1 and the second direction D2.

[0100] In some embodiments, the adapter board 300 provides electrical connections between multiple chips in the first chip module M1 and the second chip module M2, that is, it provides electrical connections between multiple chips within a chip module and electrical connections between chip modules. For example, the adapter board 300 provides electrical connections between the first main chip 100 and the first sub-chip 101, between the first main chip 100 and the first auxiliary chip 102, between the second main chip 200 and the second sub-chip 201, between the second main chip 200 and the second auxiliary chip 202, and between the first chip module M1 and the second chip module M2. For example, electrical connections between multiple chips in multiple chip modules can be implemented using a single adapter board 300. For example, the orthographic projections of multiple chips / chips in the first chip module M1 and the second chip module M2 onto the packaging substrate 400 can all lie within the orthographic projection of the adapter board 300 onto the packaging substrate 400.

[0101] In some embodiments, each chip in a plurality of chip modules can be electrically connected to an adapter board 300 via a first conductive connector 260. The first conductive connector 260 may be or include microbumps. The adapter board 300 may include conductive lines 301 for electrical connections between corresponding chips. Figures 3A to 3D The first conductive trace L1 and the second conductive trace L2 shown may be portions of the conductive line 301 (e.g., portions extending in the horizontal direction).

[0102] An encapsulation layer 310 may also be provided on the adapter board 300. The encapsulation layer 310 encapsulates multiple chips to protect them. In some embodiments, the package structure may further include an underfill layer (not shown) that fills the space between each chip and the adapter board and surrounds the first conductive connector 260. For example, the encapsulation layer 310 may include a molding compound, such as an epoxy molding compound (EMC), but this disclosure is not limited thereto.

[0103] In some embodiments, the adapter board 300 may be a silicon-based adapter board, for example, it may include a semiconductor substrate such as a silicon substrate, substrate vias embedded in the semiconductor substrate, and interconnect structures disposed on the semiconductor substrate. The interconnect structures include dielectric structures (e.g., inorganic dielectric structures) and conductive lines at least partially embedded in the dielectric structures. The conductive lines may include one or more layers of conductive lines and / or conductive vias. The conductive lines provide interconnections between multiple chips and are electrically connected to the substrate vias, and further electrically connected to the packaging substrate through the substrate vias.

[0104] In other embodiments, the adapter board 300 may also be an organic adapter board including a redistribution structure, the redistribution structure including a redistribution layer (RDL) embedded in an organic dielectric structure, the redistribution layer (i.e., conductive lines) including one or more layers of conductive lines and / or conductive vias. Appropriate types of adapter boards can be selected based on product design and requirements, and this disclosure does not limit the specific type of adapter board.

[0105] In some embodiments, a second conductive connector 360 is provided on the side of the adapter board 300 away from the chip module. Multiple second conductive connectors 360 are disposed on this side of the adapter board 300 away from the chip module and located between the adapter board 300 and the packaging substrate 400 to provide an electrical connection between the adapter board 300 and the packaging substrate 400. The second conductive connector 360 may include conductive bumps, such as controlled collapsed chip connection (C4) bumps. In some embodiments, a bottom filler layer (not shown) may also be provided in the space between the adapter board 300 and the packaging substrate 400 to surround and cover the multiple second conductive connectors 360.

[0106] In some embodiments, a plurality of third conductive connectors 460 may be provided on the side of the packaging substrate 400 away from the adapter plate 300 to provide electrical connection between the packaging structure and other external components. For example, the packaging substrate 400 may include conductive members for connecting the second conductive connector 360 and the third conductive connector 460, so that multiple chip modules can be electrically connected to the packaging substrate 400 through the first conductive connector 260, the adapter plate 300 and the second conductive connector 360, and then connected to the third conductive connector 460, and can be further connected to external components, such as printed circuit boards (PCBs), through the third conductive connector 460. In some embodiments, the third conductive connector 460 may be or include solder balls, such as ball grid arrays (BGAs), but this disclosure is not limited thereto.

[0107] In some embodiments, the package structure 500 is further connected to other external components, such as a printed circuit board, via a third conductive connector 460. For example, the package structure 500 may be mounted on a printed circuit board, which may be disposed on the side of the package substrate 400 away from the adapter plate 300, and the third conductive connector 460 may be disposed between the package substrate 400 and the printed circuit board to provide an electrical connection between the package structure 500 and the printed circuit board.

[0108] In other embodiments, the connecting member includes: a first adapter plate and a second adapter plate, spaced apart on one side of the first chip module and the second chip module in a direction parallel to the main surfaces of the first chip module and the second chip module, the first adapter plate providing electrical connection between a plurality of chips within the first chip module, and the second adapter plate providing electrical connection between a plurality of chips within the second chip module; and a packaging substrate disposed on the side of the first adapter plate and the second adapter plate away from the first chip module and the second chip module, and providing electrical connection between the first chip module and the second chip module.

[0109] Figure 5 A schematic cross-sectional view of a packaging structure according to other embodiments of the present disclosure is shown. Figure 6 A schematic plan view of a packaging structure according to other embodiments of the present disclosure is shown. For example, Figure 5 It is along Figure 6 A cross-sectional view taken from line A-A'.

[0110] refer to Figure 5 and Figure 6 In some embodiments, multiple chip modules interconnect each other through corresponding adapter boards, and the interconnection between different chip modules can be achieved through the adapter board and the packaging substrate.

[0111] For example, the packaging structure 500 may further include a first adapter plate 300a, a second adapter plate 300b, and a packaging substrate 400. The first adapter plate 300a and the second adapter plate 300b are respectively disposed on one side of the first chip module M1 and the second chip module M2 in a third direction D3, and the first adapter plate 300a and the second adapter plate 300b may be arranged side-by-side at intervals in a direction parallel to the main surface of the chip modules (e.g., a horizontal direction). The packaging substrate 400 is located on the side of the first adapter plate 300a and the second adapter plate 300b away from the chip modules.

[0112] For example, the first adapter board 300a is correspondingly disposed with the first chip module M1 and provides electrical connections between multiple chips in the first chip module M1, such as providing electrical connections between the first main chip 100 and the first sub-chip 101, and electrical connections between the first main chip 100 and the first auxiliary chip 102. For example, the orthographic projection of multiple chips in the first chip module M1 on the packaging substrate 400 may be located within the orthographic projection of the first adapter board 300a on the packaging substrate 400.

[0113] The second adapter board 300b is correspondingly disposed to the second chip module M2 and provides electrical connections between multiple chips in the second chip module M2, such as electrical connections between the second main chip 200 and the second sub-chip 201, and electrical connections between the second main chip 200 and the second auxiliary chip 202. For example, the orthographic projection of multiple chips in the second chip module M2 on the packaging substrate 400 may be located within the orthographic projection of the second adapter board 300b on the packaging substrate 400.

[0114] The packaging substrate 400 provides an electrical connection between the first chip module M1 and the second chip module M2. For example, multiple chips in the first chip module M1 are interconnected with each other via a first adapter plate 300a, and are also electrically connected to the packaging substrate 400 via the first adapter plate 300a and corresponding conductive connectors. Multiple chips in the second chip module M2 are interconnected with each other via a second adapter plate 300b, and are also electrically connected to the packaging substrate 400 via the second adapter plate 300b and corresponding conductive connectors. In this way, the first chip module M1 and the second chip module M2 can be connected to each other via the packaging substrate 400.

[0115] For example, the first adapter board 300a includes a first conductive line 301a for providing interconnection between chips within the first chip module M1, and the second adapter board 300b includes a second conductive line 301b for providing interconnection between chips within the second chip module M2. The first adapter board 300a also includes a third conductive line 301c for providing electrical connection between the first chip module M1 and the packaging substrate 400; the second adapter board 300b also includes a fourth conductive line 301d for providing electrical connection between the second chip module M2 and the packaging substrate 400. The packaging substrate 400 includes interconnecting conductive lines 401 to provide interconnection between the first chip module M1 and the second chip module M2. For example, in this embodiment... Figures 3A to 3D The first conductive trace L1 and the second conductive trace L2 in the package substrate 400 may be a portion of the interconnect conductive line 401 in the package substrate 400, such as a portion of it extending in the horizontal direction.

[0116] In this embodiment, multiple chips in the first chip module M1 are interconnected with each other through conductive lines in the first adapter plate 300a, and multiple chips in the second chip module M2 are interconnected with each other through conductive lines in the second adapter plate 300b. The first chip module M1 and the second chip module M2 are interconnected with each other through a third conductive line 301c in the first adapter plate 300a, a fourth conductive line 301d in the second adapter plate 300b, and an interconnecting conductive line 401 in the packaging substrate 400.

[0117] In this embodiment, a first encapsulation layer 310a may be provided on the first adapter board 300a to encapsulate multiple chips in the first chip module M1, and a second encapsulation layer 310b may be provided on the second adapter board 300b to encapsulate multiple chips in the second chip module M2.

[0118] Similar to the aforementioned embodiments, each chip module is electrically connected to its corresponding adapter board via a first conductive connector 260; a second conductive connector 360 is provided between each adapter board and the packaging substrate 400 to provide electrical connection between the corresponding adapter board and the packaging substrate; a third conductive connector 460 may be provided on the side of the packaging substrate 400 away from the adapter board to provide electrical connection between the packaging structure 500 and external components (e.g., PCB). The first adapter board 300a and the second adapter board 300b may each be a silicon-based adapter board or an organic adapter board, or other suitable types of adapter boards.

[0119] It should be understood that the number of adapter boards shown in the above embodiments is merely illustrative and is not intended to limit the scope of this disclosure. An appropriate number of adapter boards can be configured based on product design and requirements to achieve interconnection between multiple chips in multiple chip modules via the adapter boards and / or packaging substrates.

[0120] In some embodiments, the first chip module and the second chip module are rotationally symmetrical to each other. For example, the orientation of each chip in the first chip module is the same as the orientation of each chip in the second chip module after rotating 180 degrees. In this document, rotational symmetry of multiple components means that the orientation of one component after rotating along a certain angle is the same as the orientation of another component, but it does not mean that the one component must completely coincide with the other component after rotation.

[0121] refer to Figure 1 , Figure 2 and Figure 6 For example, the first chip module M1 and the second chip module M2 are rotationally symmetrical to each other. The orientation of each chip in the first chip module M1 can be the same as the orientation of each chip after rotating the second chip module M2 by 180 degrees (for example, rotating it 180 degrees counterclockwise or clockwise in the horizontal direction).

[0122] Specifically, the first main chip 100 and the second main chip 200 are rotationally symmetrical to each other, and the orientation of the first main chip 100 can be the same as the orientation of the second main chip 200 after rotating counterclockwise or clockwise by 180 degrees in the horizontal direction; the first sub-chip 101 and the second sub-chip 201 are rotationally symmetrical to each other, and the orientation of the first sub-chip 101 can be the same as the orientation of the second sub-chip 201 after rotating counterclockwise or clockwise by 180 degrees in the horizontal direction; the first auxiliary chip 102 and the second auxiliary chip 202 are rotationally symmetrical to each other, and the orientation of the first auxiliary chip 102 can be the same as the orientation of the second auxiliary chip 202 after rotating counterclockwise or clockwise by 180 degrees in the horizontal direction.

[0123] With the above configuration, the connection areas corresponding to each chip / core can be set on the same side edge. For example, connection areas of the same type can be set on only one side edge, and the corresponding chips can be manufactured using the same semiconductor process. Moreover, by setting the first and second chip modules to be rotationally symmetrical, the corresponding connection areas on the same edge of the corresponding chips can correspond to each other, reducing (e.g., minimizing) the interconnection distance between the corresponding connection areas, thereby improving the functional density and optimizing the interface arrangement in each chip / core, for example, increasing the number of interfaces.

[0124] exist Figure 1 In the illustrated embodiment, the intra-group connection area and inter-module connection area of ​​each main chip are all located at the first edge of the main chip. This simplifies the interface design of the main chip and, for example, reduces the lateral dimension of the main chip (e.g., the dimension in the first direction D1). At the same time, by the arrangement of the chips in the chip module, the interconnection distance between the main chips and sub-chips within the chip module and the interconnection distance between main chips in the chip modules are reduced (e.g., minimized).

[0125] exist Figure 2 or Figure 6 In the illustrated embodiment, the intra-group connection area and inter-module connection area of ​​each main chip are set on different edges of the main chip, so that the overall outline of each chip module can be roughly regular in shape. In this way, the arrangement design of multiple chips in each chip module and between different chip modules can be simplified. At the same time, by the arrangement of each chip in the chip module, the interconnection distance between the main chip and sub-chips in the chip module and the interconnection distance between the main chips in the chip modules are reduced (e.g., minimized).

[0126] In various embodiments of this disclosure, by splitting the integrated chipset into main chips and sub-chips and integrating them in the package structure, and by adjusting the arrangement of each chip module, package warpage is improved and the interconnection distance between corresponding chips or chips can be reduced, thereby optimizing the package structure in terms of performance, power consumption, and area.

[0127] The following points need to be explained: (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can refer to the general design; (2) In the absence of conflict, the features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0128] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A packaging structure, characterized in that, include: The first chip module includes: a first integrated chipset, the first integrated chipset including a first main chip and a first sub-chip connected to each other, the first main chip including a first inter-module connection area and a first set of internal connection areas configured to be connected to the first sub-chip; The second chip module includes: a second integrated chipset, the second integrated chipset including a second main chip and a second sub-chip connected to each other, the second main chip including a second inter-module connection area and a second set of internal connection areas configured to be connected to the second sub-chip, the first chip module and the second chip module being connected to each other through transceiver interfaces located in the first inter-module connection area and the second inter-module connection area respectively; The first main core and the second main core each have a first edge including a first sub-edge region and a second sub-edge region, and the first inter-module connection region and the second inter-module connection region are respectively disposed in the first sub-edge region of the first main core and the first sub-edge region of the second main core; The first main core and the second main core are arranged along a first direction and partially offset in a second direction perpendicular to the first direction, such that the first sub-edge regions of the first main core and the second main core face each other in the first direction, and the second sub-edge region of the first main core faces one of the first sub-core and the second sub-core in the first direction, and the second sub-edge region of the second main core faces the other of the first sub-core and the second sub-core in the first direction.

2. The packaging structure according to claim 1, characterized in that, The first master chip and the second master chip are each logic chips, and the first sub-chip and the second sub-chip are each input / output chips.

3. The packaging structure according to claim 1, characterized in that, The first chip module further includes a first additional chip electrically connected to the first integrated chipset, and the first main chip also includes a first set of external connection areas configured to be connected to the first additional chip, wherein the first set of external connection areas and the connection area between the first module are disposed at different edges of the first main chip. The second chip module further includes a second additional chip electrically connected to the second integrated chipset, and the second main chip further includes a second set of external connection areas configured to connect to the second additional chip, the second set of external connection areas and the connection area between the second module are disposed at different edges of the second main chip.

4. The packaging structure according to claim 3, characterized in that, The first main core and the second main core each further include a second edge opposite to the first edge in the first direction, and the first group of external connection areas and the second group of external connection areas are respectively disposed on the second edge of the first main core and the second main core; The first additional chip is disposed on the side of the first main chip away from the second main chip and facing the second edge of the first main chip, and the second additional chip is disposed on the side of the second main chip away from the first main chip and facing the second edge of the second main chip.

5. The packaging structure according to claim 3, characterized in that, The first and second additional chips are memory chips.

6. The packaging structure according to claim 1, characterized in that, The first group of internal connection areas is disposed in the second sub-edge area of ​​the first edge of the first main core, and the first sub-core is disposed on one side of the second main core in the second direction and faces the second sub-edge area of ​​the first main core in the first direction. The side edge of the first sub-core facing the first main core is provided with a first sub-connection area configured to be connected to the first group of internal connection areas. The second group of inner connection areas is disposed in the second sub-edge area of ​​the first edge of the second main core, and the second sub-core is disposed on one side of the first main core in the second direction and faces the second sub-edge area of ​​the second main core in the first direction. The side edge of the second sub-core facing the second main core is provided with a second sub-connection area configured to be connected to the second group of inner connection areas.

7. The packaging structure according to claim 6, characterized in that, The first group of internal connection areas and the first inter-module connection areas of the first main core are arranged along the second direction at the first edge of the first main core. The second group of internal connection areas and the second inter-module connection areas of the second main core are arranged along the second direction at the first edge of the second main core. The first inter-module connection area and the second inter-module connection area are at least partially aligned in the first direction; The first group of inner connection regions and the first sub-connection regions are at least partially aligned in the first direction, and the second group of inner connection regions and the second sub-connection regions are at least partially aligned in the first direction.

8. The packaging structure according to claim 1, characterized in that, The first sub-core is disposed on one side of the first main core in the second direction and faces the second sub-edge region of the second main core in the first direction. The first group of internal connection regions is disposed on the side edge of the first main core near the first sub-core, and the first sub-core is provided with a first sub-connection region configured to be connected to the first group of internal connection regions on the side edge near the first main core. The second sub-core is disposed on one side of the second main core in the second direction and faces the second sub-edge region of the first main core in the first direction. The second group of inner connection regions is disposed on the side edge of the second main core near the second sub-core, and the second sub-core is provided with a second sub-connection region configured to be connected to the second group of inner connection regions on the side edge near the second main core.

9. The packaging structure according to claim 8, characterized in that, The first inter-module connection area of ​​the first main core and the second inter-module connection area of ​​the second main core are at least partially aligned in the first direction; The first group of internal connection regions of the first main core and the first sub-connection regions of the first sub-core are at least partially aligned in the second direction; as well as The second group of inner connection regions of the second main core and the second sub-connection regions of the second sub-core are at least partially aligned in the second direction.

10. The packaging structure according to any one of claims 6-9, characterized in that, The first inter-module connection area and the second inter-module connection area, the first group intra-connection area and the first sub-connection area, the second group intra-connection area and the second sub-connection area each constitute a connection area group. The first inter-module connection area, the first group intra-connection area and the second group intra-connection area are the first connection areas of the corresponding connection area groups, and the second inter-module connection area, the first sub-connection area and the second sub-connection area are the second connection areas of the corresponding connection area groups. Each connection area group includes one or more transceiver interface groups, and each transceiver interface group includes a first transmit interface and a first receive interface located in a first connection area, and a second transmit interface and a second receive interface located in a second connection area; the first transmit interface is electrically connected to the second receive interface, and the first receive interface is electrically connected to the second transmit interface.

11. The packaging structure according to claim 10, characterized in that, The first transmitting interface and the second receiving interface are at least partially aligned in the arrangement direction of the core in which the first connection area is located and the core in which the second connection area is located, and the first receiving interface and the second transmitting interface are at least partially aligned in the arrangement direction. or The first transmitting interface and the second receiving interface are offset but adjacent in a direction perpendicular to the arrangement direction.

12. The packaging structure according to any one of claims 2-9, characterized in that, It also includes at least one of the following: A first dummy chip is disposed on one side of the first additional chip in the second direction and is spaced apart from one of the first sub-core and the second sub-core in the first direction. The first dummy chip and the first additional chip have edges aligned in the second direction, and the first dummy chip and one of the first sub-core and the second sub-core have edges aligned in the first direction. The second dummy chip is disposed on one side of the second additional chip in the second direction and is spaced apart from the other of the first sub-chip and the second sub-chip in the first direction. The second dummy chip and the second additional chip have edges aligned in the second direction, and the second dummy chip and the other of the first sub-chip and the second sub-chip have edges aligned in the first direction.

13. The packaging structure according to any one of claims 1-9, characterized in that, Also includes: A connecting member is disposed on one side of the first chip module and the second chip module in a third direction perpendicular to the first direction and the second direction, and provides electrical connection between multiple chips of the first chip module and the second chip module.

14. The packaging structure according to claim 13, characterized in that, The connecting component includes an adapter board, which provides electrical connections between multiple chips within the first chip module, between multiple chips within the second chip module, and between the first chip module and the second chip module.

15. The packaging structure according to claim 13, characterized in that, The connecting component includes: A first adapter board and a second adapter board are arranged at intervals on one side of the first chip module and the second chip module in a direction parallel to the main surfaces of the first chip module and the second chip module, respectively. The first adapter board provides electrical connections between multiple chips within the first chip module, and the second adapter board provides electrical connections between multiple chips within the second chip module. A packaging substrate is disposed on the side of the first adapter plate and the second adapter plate away from the first chip module and the second chip module, and provides an electrical connection between the first chip module and the second chip module.

16. The packaging structure according to any one of claims 1-9, characterized in that, The first chip module and the second chip module are rotationally symmetrical to each other.

17. The packaging structure according to claim 16, characterized in that, The orientation of each chip in the first chip module is the same as the orientation of each chip in the second chip module after rotating 180 degrees.

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