Display panel and display device
By using a combination of high-dielectric materials such as hafnium oxide and zirconium oxide as the gate insulating layer in the display panel, the leakage current and control capability problems of traditional silicon dioxide gate insulating layers in micro LED display panels are solved, achieving higher display performance and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TRULY (RENSHOU) HIGH-END DISPLAY TECH LTD
- Filing Date
- 2025-04-15
- Publication Date
- 2026-06-16
AI Technical Summary
Traditional silicon dioxide gate insulating layers in micro LED display panels suffer from increased leakage current and reduced gate control over the channel, making it difficult to meet the requirements of high resolution and high refresh rate.
A combination of high-dielectric materials such as hafnium oxide, zirconium oxide and aluminum oxide is used as the gate insulating layer to improve the dielectric constant, thereby reducing leakage current and enhancing the gate's control over the channel.
It effectively reduces leakage current, improves the switching speed and energy efficiency of thin-film transistors, and enhances the stability and response speed of the display panel.
Smart Images
Figure CN224368222U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology
[0002] With the continuous development of display technology, the performance requirements for display panels are becoming increasingly stringent, especially in terms of miniaturization and high performance. In the structure of a display panel, thin-film transistors (TFTs) serve as key driving components, and their performance directly affects the overall display effect.
[0003] In traditional display panels, the gate insulating layer is typically made of silicon dioxide, a material known for its excellent insulation properties and process compatibility. As display panels evolve towards higher resolutions and higher refresh rates, the size of thin-film transistors continues to shrink, placing increasingly higher demands on the performance of the gate insulating layer. In Micro LED display technology, even greater requirements are placed on the stability of the backplane drive and the control of leakage current. Traditional silicon dioxide gate insulating layers face a dilemma: when their thickness decreases, the tunneling effect leads to a significant increase in leakage current; conversely, when their thickness increases, the gate's control over the channel weakens, reducing the transistor's switching speed and energy efficiency.
[0004] Therefore, there is an urgent need to develop a new type of display panel structure to solve the above-mentioned technical problems and improve the performance and reliability of the display panel. Utility Model Content
[0005] This invention provides a display panel and display device that effectively reduces leakage current.
[0006] In a first aspect, this utility model provides a display panel, comprising:
[0007] substrate,
[0008] An active layer is disposed on the substrate.
[0009] A high-dielectric insulating layer is disposed on the substrate; the high-dielectric insulating layer is made of a material with a dielectric constant higher than that of silicon oxide.
[0010] In some embodiments, the high-dielectric insulating layer is made of a material with a dielectric constant of 20 or higher.
[0011] In some embodiments, the high-dielectric insulating layer is made of one or more combinations of hafnium oxide, zirconium oxide, and aluminum oxide.
[0012] In some embodiments, a gate layer is further included, wherein the high-dielectric insulating layer is disposed on the active layer, and the gate layer is disposed on the high-dielectric insulating layer.
[0013] In some embodiments, the device further includes an interlayer insulating layer, a source electrode, and a drain electrode; the interlayer insulating layer is disposed on the gate layer, and vias are provided on the interlayer insulating layer and the high-dielectric insulating layer; the source electrode or the drain electrode is disposed on the interlayer insulating layer and connected to the active layer through the vias.
[0014] In some embodiments, a gate layer is further included, the gate layer being disposed on the high-dielectric insulating layer, and the active layer being disposed on the gate layer.
[0015] In some embodiments, a buffer layer is further included, the buffer layer being disposed on the gate layer, and the active layer being disposed on the buffer layer.
[0016] In some embodiments, the active layer is further comprising an interlayer insulating layer, a source electrode, and a drain electrode; the interlayer insulating layer is disposed on the active layer, and a via is provided on the interlayer insulating layer; the source electrode or the drain electrode is disposed on the interlayer insulating layer and connected to the active layer through the via.
[0017] In some embodiments, the active layer includes a substrate, a channel region, and a doped layer. The substrate is disposed on the substrate, and a plurality of grooves are provided on the substrate. The doped layer is disposed in the grooves, and the channel region is formed at the contact between the substrate and the high-dielectric insulating layer.
[0018] Secondly, the present invention provides a display device, comprising: a backlight substrate and the display panel described above; the backlight substrate is disposed on the side of the substrate facing away from the auxiliary layer.
[0019] The display panel provided by this invention effectively solves the technical problems existing in the miniaturization of panel thin-film transistor driving dimensions when using traditional silicon dioxide gate insulating layers by changing the gate insulating layer material of the thin-film transistor backplane to a high-dielectric material. Compared with traditional silicon dioxide gate insulating layers, high-dielectric materials can be used with a thicker physical thickness while maintaining the same capacitance, thereby effectively reducing leakage current and threshold voltage (Vth) drift, and solving the stability and leakage problems of micro-LED backplane driving. At the same time, because high-dielectric materials store more charge under the same electric field and have better insulation performance, the switching speed and energy efficiency of transistors are improved. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the first structure of the display panel provided by this utility model;
[0021] Figure 2 This is a schematic diagram of the second structure of the display panel provided by this utility model;
[0022] Figure 3 This is a schematic diagram of a display device provided by this utility model. Detailed Implementation
[0023] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0024] Furthermore, the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0025] Example 1
[0026] Please see Figure 1 , Figure 1 This is a schematic diagram of the first structure of the display panel provided by this utility model. The display panel 10 includes a substrate 101, an active layer 104, and a high-dielectric insulating layer 105. The active layer 104 is disposed on the substrate 101, and the high-dielectric insulating layer 105 is disposed on the substrate 101. The high-dielectric insulating layer 105 is made of a material with a dielectric constant higher than that of silicon oxide.
[0027] In this embodiment, the substrate 101 can be made of materials such as glass substrate, quartz substrate, plastic substrate, or flexible substrate. The thickness of the substrate 101 can be selected according to actual application requirements, typically from 0.3 mm to 1.5 mm. The surface of the substrate 101 is cleaned to ensure good adhesion of the subsequent thin film layer.
[0028] An active layer 104 is disposed on the substrate 101. The active layer 104 can be made of materials such as amorphous silicon, polycrystalline silicon, oxide semiconductors, or organic semiconductors. In this embodiment, the active layer 104 is preferably made of an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or zinc oxide (ZnO). The thickness of the active layer 104 is typically 30 nm to 200 nm, preferably 50 nm to 100 nm. The active layer 104 is formed on the substrate 101 by methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or sputtering.
[0029] A high-dielectric insulating layer 105 is disposed on the substrate 101. The dielectric constant of the material used in the high-dielectric insulating layer 105 is higher than that of silicon oxide. The dielectric constant of silicon oxide is approximately 3.9, therefore the dielectric constant of the material used in the high-dielectric insulating layer 105 must be greater than 3.9. The thickness of the high-dielectric insulating layer 105 is typically 10 nm to 100 nm, preferably 20 nm to 50 nm. The high-dielectric insulating layer 105 can be formed by methods such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).
[0030] Furthermore, the high-dielectric insulating layer 105 uses a material with a dielectric constant of 20 or higher. Materials with a high dielectric constant can provide higher capacitance density under the same electric field strength, thereby improving the performance of the display panel 10. Materials with a dielectric constant of 20 or higher can significantly reduce gate voltage, reduce power consumption, and improve the response speed of the display panel 10.
[0031] Specifically, the high-dielectric insulating layer 105 is made of one or more combinations of hafnium oxide, zirconium oxide, and aluminum oxide. Hafnium oxide (HfO2) has a dielectric constant of approximately 25, zirconium oxide (ZrO2) has a dielectric constant of approximately 22, and aluminum oxide (Al2O3) has a dielectric constant of approximately 9. In this embodiment, the high-dielectric insulating layer 105 preferably uses a combination of hafnium oxide and zirconium oxide, wherein the hafnium oxide content is 60% to 80%, and the zirconium oxide content is 20% to 40%. This combination can achieve a dielectric constant of approximately 23 to 24, while also exhibiting good thermal and chemical stability.
[0032] The display panel 10 in this embodiment further includes a gate layer 106, a high-dielectric insulating layer 105 disposed on the active layer 104, and the gate layer 106 disposed on the high-dielectric insulating layer 105. The gate layer 106 can be made of a metallic material, such as aluminum, copper, molybdenum, titanium, or alloys thereof. The thickness of the gate layer 106 is typically 100 nm to 500 nm, preferably 200 nm to 300 nm. The gate layer 106 is formed by methods such as physical vapor deposition (PVD) or sputtering, and is patterned by photolithography and etching processes to form the desired gate electrode pattern.
[0033] The display panel 10 in this embodiment further includes an interlayer insulating layer 107, a source electrode 108, and a drain electrode 109. The interlayer insulating layer 107 is disposed on the gate layer 106. Through-holes 110 are formed on the interlayer insulating layer 107 and the high-dielectric insulating layer 105. The source electrode 108 or drain electrode 109 is disposed on the interlayer insulating layer 107 and connected to the active layer 104 through the through-holes 110. The interlayer insulating layer 107 can be made of silicon oxide, silicon nitride, or organic insulating materials. The thickness of the interlayer insulating layer 107 is typically 300 nm to 1000 nm, preferably 400 nm to 600 nm. The interlayer insulating layer 107 is formed by methods such as plasma-enhanced chemical vapor deposition (PECVD) or spin coating.
[0034] The via 110 is formed on the interlayer insulating layer 107 and the high-dielectric insulating layer 105 by photolithography and etching processes. The diameter of the via 110 is typically 1 μm to 5 μm, preferably 2 μm to 3 μm. The depth of the via 110 depends on the total thickness of the interlayer insulating layer 107 and the high-dielectric insulating layer 105, and is typically 310 nm to 1100 nm.
[0035] The source electrode 108 and drain electrode 109 can be made of the same or different metal material as the gate layer 106, such as aluminum, copper, molybdenum, titanium, or alloys thereof. The thickness of the source electrode 108 and drain electrode 109 is typically 100 nm to 500 nm, preferably 200 nm to 300 nm. The source electrode 108 and drain electrode 109 are formed by methods such as physical vapor deposition (PVD) or sputtering, and patterned by photolithography and etching processes to form the desired source electrode 108 and drain electrode 109 electrode patterns. The source electrode 108 and drain electrode 109 are electrically connected to the active layer 104 through vias 110, forming the source electrode 108 and drain electrode 109 of the thin-film transistor.
[0036] The active layer 104 includes a substrate 1041, a channel region 1043, and a doped layer 1042. The substrate 1041 is disposed on the substrate 101, and a plurality of grooves 104a are formed on the substrate 1041. The doped layer 1042 is disposed within the grooves 104a. The channel region 1043 is formed at the contact between the substrate 1041 and the high-dielectric insulating layer 105. The substrate 1041 can be made of an undoped semiconductor material, such as an undoped oxide semiconductor material. The thickness of the substrate 1041 is typically 30 nm to 200 nm, preferably 50 nm to 100 nm.
[0037] The groove 104a is formed on the substrate 1041 by photolithography and etching processes. The depth of the groove 104a is typically 10 nm to 50 nm, preferably 20 nm to 30 nm. The width of the groove 104a is typically 1 μm to 5 μm, preferably 2 μm to 3 μm.
[0038] A doped layer 1042 is disposed within the recess 104a. The doped layer 1042 can be made of a doped semiconductor material, such as a doped oxide semiconductor material. The thickness of the doped layer 1042 is typically equal to the depth of the recess 104a, ranging from 10 nm to 50 nm, preferably from 20 nm to 30 nm. The doped layer 1042 is formed by methods such as ion implantation, plasma treatment, or selective deposition.
[0039] A channel region 1043 is formed at the contact between the substrate 1041 and the high-dielectric insulating layer 105. The length of the channel region 1043 is typically 1 μm to 10 μm, preferably 2 μm to 5 μm. The width of the channel region 1043 is typically 5 μm to 50 μm, preferably 10 μm to 30 μm. The channel region 1043 is the core part of the thin-film transistor, and its conductivity is controlled by the gate voltage to realize the switching function.
[0040] The display panel 10 may also include a light-shielding layer 102 and a buffer layer 103. The light-shielding layer 102 is disposed on the substrate 101, the buffer layer 103 is disposed on the light-shielding layer 102, and the active layer 104 is disposed on the buffer layer 103.
[0041] In this embodiment, the display panel 10 uses a high-dielectric insulating layer 105 as the gate insulating layer, which can obtain a higher gate capacitance at a lower gate voltage, thereby improving the switching performance of the thin-film transistor, reducing power consumption, and improving the response speed and display quality of the display panel 10.
[0042] Example 2
[0043] Please see Figure 2 , Figure 2 This is a schematic diagram of a second structure of the display panel provided by this utility model. The display panel 10 includes a substrate 101, an active layer 104, and a high-dielectric insulating layer 105. The active layer 104 is disposed on the substrate 101, and the high-dielectric insulating layer 105 is disposed on the substrate 101. The high-dielectric insulating layer 105 is made of a material with a dielectric constant higher than that of silicon oxide.
[0044] In this embodiment, the substrate 101 can be made of materials such as glass substrate 101, quartz substrate 101, plastic substrate 101, or flexible substrate 101. The thickness of the substrate 101 can be selected according to actual application requirements, typically from 0.3 mm to 1.5 mm. The surface of the substrate 101 is cleaned to ensure good adhesion of the subsequent thin film layer.
[0045] An active layer 104 is disposed on the substrate 101. The active layer 104 can be made of materials such as amorphous silicon, polycrystalline silicon, oxide semiconductors, or organic semiconductors. In this embodiment, the active layer 104 is preferably made of an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or zinc oxide (ZnO). The thickness of the active layer 104 is typically 30 nm to 200 nm, preferably 50 nm to 100 nm. The active layer 104 is formed on the substrate 101 by methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or sputtering.
[0046] A high-dielectric insulating layer 105 is disposed on the substrate 101. The dielectric constant of the material used in the high-dielectric insulating layer 105 is higher than that of silicon oxide. The dielectric constant of silicon oxide is approximately 3.9, therefore the dielectric constant of the material used in the high-dielectric insulating layer 105 must be greater than 3.9. The thickness of the high-dielectric insulating layer 105 is typically 10 nm to 100 nm, preferably 20 nm to 50 nm. The high-dielectric insulating layer 105 can be formed by methods such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).
[0047] Furthermore, the high-dielectric insulating layer 105 uses a material with a dielectric constant of 20 or higher. Materials with a high dielectric constant can provide higher capacitance density under the same electric field strength, thereby improving the performance of the display panel 10. Materials with a dielectric constant of 20 or higher can significantly reduce gate voltage, reduce power consumption, and improve the response speed of the display panel 10.
[0048] The high-dielectric insulating layer 105 is made of one or more combinations of hafnium oxide, zirconium oxide, and aluminum oxide. Hafnium oxide (HfO2) has a dielectric constant of approximately 25, zirconium oxide (ZrO2) has a dielectric constant of approximately 22, and aluminum oxide (Al2O3) has a dielectric constant of approximately 9. In this embodiment, the high-dielectric insulating layer 105 preferably uses a combination of hafnium oxide and aluminum oxide, wherein the hafnium oxide content is 70% to 90%, and the aluminum oxide content is 10% to 30%. This combination can achieve a dielectric constant of approximately 20 to 23, while also exhibiting good thermal and chemical stability.
[0049] The display panel 10 of this embodiment further includes a light-shielding layer 102, a buffer layer 103, and a gate layer 106. The light-shielding layer 102 is disposed on the substrate 101, a high-dielectric insulating layer 105 is disposed on the light-shielding layer 102, the gate layer 106 is disposed on the high-dielectric insulating layer 105, the buffer layer 103 is disposed on the gate layer 106, and the active layer 104 is disposed on the buffer layer 103. The gate layer 106 can be made of a metallic material, such as aluminum, copper, molybdenum, titanium, or alloys thereof. The thickness of the gate layer 106 is typically 100 nm to 500 nm, preferably 200 nm to 300 nm. The gate layer 106 is formed by physical vapor deposition (PVD) or sputtering, and patterned using photolithography and etching processes to form the desired gate electrode pattern.
[0050] The buffer layer 103 can be made of materials such as silicon oxide, silicon nitride, or combinations thereof. The thickness of the buffer layer 103 is typically 50 nm to 300 nm, preferably 100 nm to 200 nm. The buffer layer 103 is formed by methods such as plasma-enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The function of the buffer layer 103 is to prevent metal atoms in the gate layer 106 from diffusing into the active layer 104, while providing a smooth surface for the subsequent growth of the active layer 104.
[0051] Alternatively, the buffer layer 103 can also be made of a high-dielectric material. The dielectric constant of the material used in the buffer layer 103 is higher than that of silicon oxide. The dielectric constant of silicon oxide is approximately 3.9, therefore the dielectric constant of the material used in the buffer layer 103 must be greater than 3.9. The thickness of the buffer layer 103 is typically 10 nm to 100 nm, preferably 20 nm to 50 nm. The buffer layer 103 can be formed by methods such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).
[0052] Furthermore, the buffer layer 103 is made of a material with a dielectric constant of 20 or higher. Materials with a high dielectric constant can provide higher capacitance density under the same electric field strength, thereby improving the performance of the display panel 10. Materials with a dielectric constant of 20 or higher can significantly reduce gate voltage, decrease power consumption, and improve the response speed of the display panel 10.
[0053] The buffer layer 103 is made of one or more combinations of hafnium oxide, zirconium oxide, and aluminum oxide. Hafnium oxide (HfO2) has a dielectric constant of approximately 25, zirconium oxide (ZrO2) has a dielectric constant of approximately 22, and aluminum oxide (Al2O3) has a dielectric constant of approximately 9. In this embodiment, the high-dielectric insulating layer 105 preferably uses a combination of hafnium oxide and aluminum oxide, wherein the hafnium oxide content is 70% to 90% and the aluminum oxide content is 10% to 30%. This combination achieves a dielectric constant of approximately 20 to 23, while also exhibiting good thermal and chemical stability.
[0054] The display panel 10 in this embodiment further includes an interlayer insulating layer 107, a source electrode 108, and a drain electrode 109. The interlayer insulating layer 107 is disposed on the active layer 104, and a through-hole 110 is provided on the interlayer insulating layer 107. The source electrode 108 or drain electrode 109 is disposed on the interlayer insulating layer 107 and connected to the active layer 104 through the through-hole 110. The interlayer insulating layer 107 can be made of silicon oxide, silicon nitride, or organic insulating materials. The thickness of the interlayer insulating layer 107 is typically 300 nm to 1000 nm, preferably 400 nm to 600 nm. The interlayer insulating layer 107 is formed by methods such as plasma-enhanced chemical vapor deposition (PECVD) or spin coating.
[0055] The via 110 is formed on the interlayer insulating layer 107 by photolithography and etching processes. The diameter of the via 110 is typically 1 μm to 5 μm, preferably 2 μm to 3 μm. The depth of the via 110 is equal to the thickness of the interlayer insulating layer 107, typically 300 nm to 1000 nm.
[0056] The source electrode 108 and drain electrode 109 can be made of the same or different metal material as the gate layer 106, such as aluminum, copper, molybdenum, titanium, or alloys thereof. The thickness of the source electrode 108 and drain electrode 109 is typically 100 nm to 500 nm, preferably 200 nm to 300 nm. The source electrode 108 and drain electrode 109 are formed by methods such as physical vapor deposition (PVD) or sputtering, and patterned by photolithography and etching processes to form the desired source electrode 108 and drain electrode 109 electrode patterns. The source electrode 108 and drain electrode 109 are electrically connected to the active layer 104 through vias 110, forming the source electrode 108 and drain electrode 109 of the thin-film transistor.
[0057] The active layer 104 includes a substrate 1041, a channel region 1043, and a doped layer 1042. The substrate 1041 is disposed on the substrate 101, and a plurality of grooves 104a are formed on the substrate 1041. The doped layer 1042 is disposed within the grooves 104a. The channel region 1043 is formed at the contact between the substrate 1041 and the high-dielectric insulating layer 105. The substrate 1041 can be made of an undoped semiconductor material, such as an undoped oxide semiconductor material. The thickness of the substrate 1041 is typically 30 nm to 200 nm, preferably 50 nm to 100 nm.
[0058] The groove 104a is formed on the substrate 1041 by photolithography and etching processes. The depth of the groove 104a is typically 10 nm to 50 nm, preferably 20 nm to 30 nm. The width of the groove 104a is typically 1 μm to 5 μm, preferably 2 μm to 3 μm.
[0059] A doped layer 1042 is disposed within the recess 104a. The doped layer 1042 can be made of a doped semiconductor material, such as a doped oxide semiconductor material. The thickness of the doped layer 1042 is typically equal to the depth of the recess 104a, ranging from 10 nm to 50 nm, preferably from 20 nm to 30 nm. The doped layer 1042 is formed by methods such as ion implantation, plasma treatment, or selective deposition.
[0060] A channel region 1043 is formed at the contact between the substrate 1041 and the high-dielectric insulating layer 105. The length of the channel region 1043 is typically 1 μm to 10 μm, preferably 2 μm to 5 μm. The width of the channel region 1043 is typically 5 μm to 50 μm, preferably 10 μm to 30 μm. The channel region 1043 is the core part of the thin-film transistor, and its conductivity is controlled by the gate voltage to realize the switching function.
[0061] In this embodiment, the display panel 10 uses a high-dielectric insulating layer 105 as the gate insulating layer, which can achieve a higher gate capacitance at a lower gate voltage, thereby improving the switching performance of the thin-film transistor, reducing power consumption, and improving the response speed and display quality of the display panel 10. Compared with Embodiment 1, the display panel 10 in this embodiment adopts a different structure. The gate layer 106 is disposed on the high-dielectric insulating layer 105, and the active layer 104 is disposed on the gate layer 106, forming a bottom-gate structure thin-film transistor.
[0062] Example 3
[0063] Please see Figure 3 , Figure 3 This is a schematic diagram of a display device provided by this utility model. A display device includes a packaging substrate 20 and a display panel 10 as described in Embodiment 1 or Embodiment 2.
[0064] Specifically, the encapsulation substrate 20 can be made of materials such as a glass substrate, a quartz substrate, a plastic substrate 101, or a flexible substrate. The thickness of the encapsulation substrate 20 can be selected according to actual needs, for example, from 0.3mm to 1.5mm. The area of the encapsulation substrate 20 can be matched with the area of the display panel 10.
[0065] In this embodiment, the display device may further include a driving circuit, a control circuit, and a power supply circuit. The driving circuit provides driving signals to the display panel 10, the control circuit processes the input image signals and controls the operation of the driving circuit, and the power supply circuit provides the necessary power to the display device.
[0066] The display device in this embodiment uses the display panel 10 described in Embodiment 1 or Embodiment 2, which has low power consumption, high response speed, and good display quality. The display device can be applied to electronic devices such as televisions, monitors, laptops, tablets, and smartphones.
[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A display panel, characterized in that, include: substrate, An active layer is disposed on the substrate. A high-dielectric insulating layer is disposed on the substrate; the high-dielectric insulating layer is made of a material with a dielectric constant higher than that of silicon oxide.
2. The display panel according to claim 1, characterized in that, The high-dielectric insulating layer is made of a material with a dielectric constant of 20 or higher.
3. The display panel according to claim 2, characterized in that, The high-dielectric insulating layer is made of one or more combinations of hafnium oxide, zirconium oxide, and aluminum oxide.
4. The display panel according to claim 1, characterized in that, It also includes a gate layer, wherein the high-dielectric insulating layer is disposed on the active layer, and the gate layer is disposed on the high-dielectric insulating layer.
5. The display panel according to claim 4, characterized in that, It also includes an interlayer insulating layer, a source electrode, and a drain electrode; the interlayer insulating layer is disposed on the gate layer, and vias are disposed on the interlayer insulating layer and the high-dielectric insulating layer; the source electrode or the drain electrode is disposed on the interlayer insulating layer and is connected to the active layer through the vias.
6. The display panel according to claim 1, characterized in that, It also includes a gate layer disposed on the high-dielectric insulating layer, and the active layer disposed on the gate layer.
7. The display panel according to claim 6, characterized in that, It also includes a buffer layer disposed on the gate layer, and the active layer disposed on the buffer layer.
8. The display panel according to claim 6 or 7, characterized in that, It also includes an interlayer insulating layer, a source electrode, and a drain electrode; the interlayer insulating layer is disposed on the active layer, and a through-hole is disposed on the interlayer insulating layer, and the source electrode or the drain electrode is disposed on the interlayer insulating layer and connected to the active layer through the through-hole.
9. The display panel according to claim 4 or 6, characterized in that, The active layer includes a substrate, a channel region, and a doped layer. The substrate is disposed on the substrate and has multiple grooves. The doped layer is disposed in the grooves. The channel region is formed at the contact between the substrate and the high-dielectric insulating layer.
10. A display device, characterized in that, Includes: a packaging substrate and a display panel as described in any one of claims 1 to 9.