An electrode structure, LED chip
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YANGZHOU CHANGELIGHT
- Filing Date
- 2025-06-30
- Publication Date
- 2026-06-16
Smart Images
Figure CN224368236U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of semiconductor device manufacturing technology, and more specifically, relates to an electrode structure and an LED chip. Background Technology
[0002] With the continuous development of science and technology, LED (Light Emitting Diode) has become the most popular light source, with an increasingly higher market share and a wider range of applications. Compared with traditional light-emitting devices, LED chips have many advantages such as low power consumption, high color purity, long life, small size, fast response time, energy saving and environmental protection.
[0003] Current LED chip structure designs require different electrode layouts (e.g., upright, flip-chip, and reverse polarity structures) on the light-emitting surface to ensure current expansion and increase the effective light-emitting area. Common industry solutions include: 1. Using sophisticated designs of pad electrodes and electrode grid lines with different shapes and thicknesses to achieve the most suitable current expansion effect for the corresponding size and model. 2. Increasing the electrode ratio, i.e., increasing the number and width of electrode grid lines, to enhance current expansion. 3. Removing the ohmic contact layer beneath the pad electrodes, allowing the current from the pad electrodes to be conducted parallel to each electrode grid line before being conducted to the light-emitting structure via the ohmic contact layer, thus enhancing the expansion effect.
[0004] However, in practical applications, designing extremely precise continuous patterns involves complex processes and requires high precision equipment, making mass production impractical. While simply increasing the electrode ratio can improve current spread performance and light extraction efficiency to some extent, it also occupies the effective light extraction area. This necessitates significant effort to explore the relationship between light intensity and light extraction area to achieve optimal chip brightness, with limited improvement. Furthermore, the current flowing from the pad electrodes must traverse a very long section of the electrode gate line, a length far exceeding the distance for current conduction. Utility Model Content
[0005] In view of this, the present invention provides an electrode structure and an LED chip to solve the problems in the prior art where the electrode structure of the LED chip occupies the effective light-emitting area, has poor current expansion effect, and is complex in process, thus affecting the light emission uniformity and light emission efficiency of the LED chip.
[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0007] An electrode structure applied to an LED chip, characterized in that the electrode structure includes: an ohmic contact layer located on one side surface of a substrate, a pad electrode, and a main gate line and a sub-gate line connected to the pad electrode, wherein one side surface of the substrate is the light-emitting surface of the LED chip;
[0008] The pad electrodes are spaced apart from the ohmic contact layer. A portion of the surface of the ohmic contact layer has a groove extending toward the light-emitting surface. The sub-gate lines are embedded in the grooves by being covered by an insulating layer. The insulating layer has several through holes exposing the sub-gate lines. The main gate line is located on a portion of the ohmic contact layer away from the light-emitting surface and is connected to the sub-gate lines by filling each of the through holes. The current of the sub-gate lines is injected into the main gate line at multiple points through each of the through holes.
[0009] Preferably, the horizontal cross-sectional area of each of the through holes gradually increases in the direction away from the pad electrode.
[0010] Preferably, the spacing between adjacent vias gradually decreases in the direction away from the pad electrode.
[0011] Preferably, the width of the sub-gate line increases linearly or non-linearly along the direction away from the pad electrode.
[0012] Preferably, the main grid line covers a portion of the ohmic contact layer on the sidewall of the trench.
[0013] Preferably, the bottom of the trench exposes the ohmic contact layer;
[0014] Alternatively, the trench extends through the ohmic contact layer, and the bottom of the trench exposes the light-emitting surface.
[0015] Preferably, the electrode structure includes a plurality of the pad electrodes, a plurality of the main gate lines, and a plurality of the sub-gate lines.
[0016] Preferably, each of the pad electrodes is connected to at least one main gate line and at least one sub-gate line, and each of the main gate lines is connected to at least one sub-gate line.
[0017] This utility model also provides an LED chip, characterized in that it comprises:
[0018] A stacked structure, the stacked structure including at least a light-emitting structure, the light-emitting structure including a first type semiconductor layer, an active region and a second type semiconductor layer stacked in sequence, the side of the light-emitting structure near the first type semiconductor layer being the light-emitting surface of the LED chip;
[0019] The first electrode has an electrode structure as described in any of the preceding claims and is electrically connected to the first type of semiconductor layer.
[0020] The second electrode is electrically connected to the second type of semiconductor layer.
[0021] Preferably, the stacked structure further includes a dielectric film layer, a metal reflective layer, a metal bonding layer, and a conductive substrate disposed between the second type semiconductor layer and the second electrode and stacked sequentially. The conductive substrate is connected to the second electrode, and the dielectric film layer is connected to the second type semiconductor layer. The dielectric film layer has a conductive hole, and the conductive hole contains a conductive metal that conducts through the metal reflective layer and the second type semiconductor layer.
[0022] The first type of semiconductor layer includes a first type of confinement layer, a first type of current spreading layer, and a first type of roughening layer sequentially stacked on the surface of the active region toward the first electrode;
[0023] The second type of semiconductor layer includes a second type of confinement layer and a second type of current spreading layer sequentially stacked on the surface of the active region toward the direction of the second electrode.
[0024] By means of the above technical solution, this application provides an electrode structure and an LED chip. The electrode structure includes: an ohmic contact layer located on one side surface of a substrate, a pad electrode, and a main gate line and a sub-gate line connected to the pad electrode. One side surface of the substrate is the light-emitting surface of the LED chip. The pad electrode and the ohmic contact layer are spaced apart. A portion of the surface of the ohmic contact layer has a groove extending toward the light-emitting surface. The sub-gate line is embedded in the groove by being covered by an insulating layer, so that after the current flows out from the pad electrode, it simultaneously flows through the main gate line and the sub-gate line to form two sets of parallel current conduction paths. The insulating layer has several through holes exposing the sub-gate lines. The main gate line is located on the portion of the ohmic contact layer away from the light-emitting surface and is connected to the sub-gate line by filling each through hole. The current of the sub-gate line is injected into the main gate line at multiple points through each through hole, so that the sub-gate line provides compensation for the current of the main gate line, thereby enhancing the current conduction of the main gate line and improving the light emission uniformity and luminous efficiency of the LED chip. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of the electrode structure of an existing LED chip;
[0027] Figure 2 This is a schematic diagram of an electrode structure provided in an embodiment of the present utility model;
[0028] Figure 3 for Figure 2 A schematic cross-sectional view of the electrode structure along line EE;
[0029] Figure 4 A top view schematic diagram of an electrode structure provided in an embodiment of this utility model;
[0030] Figure 5 A flowchart illustrating a method for fabricating an electrode structure according to an embodiment of this utility model;
[0031] Figures 6 to 18 for Figure 5 The structural diagrams corresponding to each step of the manufacturing method shown are as follows;
[0032] Figure 19 This is a schematic diagram of the structure of an LED chip provided in an embodiment of the present utility model;
[0033] Figure 20 A flowchart illustrating a method for manufacturing an LED chip according to an embodiment of this utility model;
[0034] Figure 21 A flowchart of step one provided for an embodiment of this utility model;
[0035] Figures 22 to 25 for Figure 21 The diagram shows the structural schematics corresponding to each step of the manufacturing process.
[0036] Explanation of symbols in the diagram:
[0037] 01. Growth substrate; 02. Buffer layer; 03. Etching stop layer; C. Trench; C'. Trench pre-set area; D. Channel; T. Through-hole; Q. Groove;
[0038] 1. Ohmic contact layer; 2. Pad electrode; 2'. Pad electrode preset area; 3. Main gate line; 4. Sub-gate line; 5. Insulating layer; 6. First electrode; 7. Second electrode; 8. Dielectric film layer; 9. Metal reflective layer; 10. Metal bonding layer; 11. Conductive substrate; 12. Conductive metal; 20. Type I semiconductor layer; 21. Type I roughening layer; 22. Type I current spreading layer; 23. Type I confinement layer; 30. Active region; 40. Type II semiconductor layer; 41. Type II confinement layer; 42. Type II current spreading layer; 100. Substrate; 200. Light-emitting structure; 300. Electrode gate line. Detailed Implementation
[0039] To make the content of this utility model clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0040] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0041] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.
[0042] Existing LED chip design requires different electrode layouts on the light-emitting surface to ensure current expansion and increase the effective light-emitting area. For example... Figure 1 As shown (arrows in the figure indicate current direction), the existing LED chip electrode structure includes a pad electrode 2 and an electrode gate line 300, with the electrode gate line 300 disposed on the upper surface of the ohmic contact layer 1. When the current flowing from the pad electrode is conducted from the near end to the far end of the electrode gate line, it must traverse a very long section of the electrode gate line, a length far exceeding the distance for current conduction. Moreover, during the current flow from the near end to the far end of the electrode gate line, most of the current is directly conducted through the ohmic contact layer to the interior of the LED chip, resulting in only a very small current, or even none at all, reaching the far end of the electrode gate line. This affects the current spread of the electrode structure, thereby impacting the luminous uniformity and light extraction efficiency of the LED chip.
[0043] In view of this, the present application provides an electrode structure that is applied to an LED chip, such as... Figures 2 to 3 As shown, the electrode structure includes: an ohmic contact layer 1 located on one side surface of the substrate 100, a pad electrode 2, and a main gate line 3 and a sub-gate line 4 connected to the pad electrode 2. One side surface of the substrate 100 is the light-emitting surface of the LED chip.
[0044] The pad electrode 2 is spaced apart from the ohmic contact layer 1. A portion of the surface of the ohmic contact layer 1 has a groove C extending toward the light-emitting surface. The sub-gate line 4 is embedded in the groove C in a manner covered by the insulating layer 5. The insulating layer 5 has several through holes T that expose the sub-gate line 4. The main gate line 3 is located on the portion of the ohmic contact layer 1 that is away from the light-emitting surface and is connected to the sub-gate line 4 by filling each through hole T. The current of the sub-gate line 4 is injected into the main gate line 3 at multiple points through each through hole T.
[0045] It should be noted that, in the embodiments of this application... Figure 2 The middle arrow indicates the direction of current. The electrode structure includes: an ohmic contact layer 1 located on one side surface of the substrate 100, a pad electrode 2, and a main gate line 3 and a sub-gate line 4 connected to the pad electrode 2. One side surface of the substrate 100 is the light-emitting surface of the LED chip. The pad electrode 2 is spaced apart from the ohmic contact layer 1. A portion of the surface of the ohmic contact layer 1 has a groove C extending towards the light-emitting surface. The sub-gate line 4 is embedded in the groove C by being covered by an insulating layer 5. The sub-gate line 4 is insulated from the ohmic contact layer 1 by the insulating layer 5, so that after the current flows out from the pad electrode 2, it simultaneously flows through the main gate line 3 and the sub-gate line 4 to form two parallel current conduction paths. The insulating layer has several through holes exposing the sub-gate lines. The main gate line 3 is located on the portion of the ohmic contact layer 1 facing away from the light-emitting surface and is connected to the sub-gate line 4 by filling each through hole T, so that the main gate line 3 contacts the ohmic contact layer 1 to form a low-resistance interface. The via T serves as the current conduction channel between the main gate line 3 and the sub-gate line 4. Due to continuous current injection, the potential of the sub-gate line 4 continuously increases due to the accumulation of charge. Meanwhile, the current in the main gate line 3 is introduced into the light-emitting area inside the LED chip through the ohmic contact layer 1, where the potential remains stable. Since current flows from high potential to low potential, during the current conduction process, the current in the sub-gate line 4 is injected into the main gate line 3 at multiple points through the via T. This allows the sub-gate line 4 to compensate for the current in the main gate line 3, thereby enhancing the current conduction of the main gate line 3. This solves the problem of difficult current conduction and uneven current distribution at the far end of the main gate line 3 due to excessive transmission distance. This enhances the current extension of the electrode structure to the edge of the LED chip's light-emitting area, making the current distribution more uniform. Moreover, the current extension effect can be achieved without increasing the area ratio of the main gate line 3, increasing the effective light-emitting area and thus improving the light-emitting uniformity and luminous efficiency of the LED chip.
[0046] In addition, the sub-grid line 4 is embedded in the trench C by being wrapped by the insulating layer 5. The main grid line 3 is located on the part of the ohmic contact layer 1 that is away from the light-emitting surface and is connected to the sub-grid line 4 by filling each through hole T. This effectively avoids the risk of existing fine electrode grid lines falling off and enhances the robustness of the electrode structure.
[0047] In this application embodiment, the specific type of LED chip to which the electrode structure is applied is not limited. The electrode structure can be applied to LED chips of various sizes, such as upright, flip, miniature, or large-size.
[0048] In this embodiment, the specific shape of the through hole T is not limited. The through hole T can be any geometric shape, such as a circle, ellipse, triangle, rectangle or other geometric shapes.
[0049] Optionally, in some embodiments, the pad electrode 2 may be spaced apart from the ohmic contact layer 1 by the insulating layer 5.
[0050] Optionally, in some embodiments, the material of the ohmic contact layer 1 includes, but is not limited to, GaAs.
[0051] Optionally, in some embodiments, the material of the insulating layer 5 includes, but is not limited to, one or more of SiO2, SiN, and Al2O3.
[0052] Optionally, in some embodiments, the horizontal cross-sectional area of each via T gradually increases in the direction away from the pad electrode 2, so as to increase the area of the current conduction channel between the main gate line 3 and the sub-gate line 4, thereby strengthening the current compensation of the sub-gate line 4 to the main gate line 3 away from the pad electrode 2, improving the current expansion effect of the electrode structure, and thus making the current distribution more uniform.
[0053] Optionally, in some embodiments, the vias T are spaced apart along a direction away from the pad electrode 2.
[0054] Optionally, in some embodiments, the spacing between adjacent through holes T may be equal or unequal.
[0055] Optionally, in some embodiments, the spacing between adjacent vias T gradually decreases along the direction away from the pad electrode 2 to increase the density of the current conduction channels between the main gate line 3 and the sub-gate line 4, thereby enhancing the current compensation of the main gate line 3 away from the pad electrode 2 by the sub-gate line 4, improving the current expansion effect of the electrode structure, and thus making the current distribution more uniform.
[0056] Optionally, in some embodiments, the width of the sub-gate line 4 decreases linearly or non-linearly along the direction away from the pad electrode 2.
[0057] Optionally, in some embodiments, the width of the sub-gate line 4 increases linearly or non-linearly along the direction away from the pad electrode 2. This not only enhances the current compensation of the main gate line 3 away from the pad electrode 2 by the sub-gate line 4, improves the current expansion effect of the electrode structure, and makes the current distribution more uniform, but also increases the current expansion channel by the sub-gate line 4, which is equivalent to increasing the cross-sectional area of current transmission. Therefore, it can reduce the current congestion effect, reduce the resistance, and avoid the problem of local overheating caused by current congestion in the sub-gate line 4 near the pad electrode 2.
[0058] Optionally, in some embodiments, reference is made to... Figure 3 As shown, the main grid line 3 covers part of the ohmic contact layer 1 on the sidewall of the trench C.
[0059] It should be noted that in this embodiment of the application, the ohmic contact layer 1 covering part of the sidewall of the trench C by the main grid line 3 can not only enhance the robustness of the electrode structure, but also increase the ohmic contact area between the main grid line 3 and the ohmic contact layer 1, increase the current channel, reduce the resistance, thereby reducing the LED chip voltage, improving the reliability of the LED chip, suppressing light decay, and reducing energy consumption.
[0060] Optionally, in some embodiments, the bottom of the trench C exposes the ohmic contact layer 1;
[0061] Alternatively, trench C penetrates the ohmic contact layer 1, and the bottom of trench C exposes the light surface.
[0062] Optionally, in some embodiments, the sub-gate line 4 is located within the vertical range of the main gate line 3.
[0063] Optionally, in this embodiment, the horizontal width of the main gate line 3 is greater than the horizontal width of the sub-gate line 4.
[0064] Optionally, in another embodiment, some sub-gate lines 4 are located within the vertical range of the main gate line 3.
[0065] Optionally, in another embodiment, the sub-gate line 4 may not be located within the vertical range of the main gate line 3.
[0066] It should be noted that in the embodiments of this application, the sub-gate line 4 may not be located within the vertical range of the main gate line 3. For example, when the electrode structure is applied in a large-size LED chip, the electrode structure enhances the current expansion effect of the large-size LED chip, while the area ratio of the sub-gate line 4 is very small and will not affect the luminous intensity of the large-size LED chip.
[0067] Optionally, in some embodiments, the horizontal width of the sub-gate line 4 is greater than or equal to the horizontal width of the via T.
[0068] Optionally, in some embodiments, such as Figure 4 As shown, the electrode structure includes several pad electrodes 2, several main gate lines 3, and several sub-gate lines 4 (not shown in the figure), which are used to improve the current expansion effect of the electrode structure and thus make the current distribution more uniform.
[0069] It should be noted that this embodiment does not limit the specific number of pad electrodes 2, main gate lines 3, and sub-gate lines 4, and can be set according to actual needs. In some optional embodiments, the number of sub-gate lines 4 can be the same as the number of main gate lines 3, and in another optional embodiment, the number of sub-gate lines 4 can be greater than the number of main gate lines 3.
[0070] It should also be noted that in this embodiment, each sub-grid line 4 may or may not be located at the same horizontal height. This application does not limit this and can be set according to actual needs.
[0071] Optionally, in some embodiments, a single pad electrode 2 is connected to at least one main gate line 3 and at least one sub-gate line 4, and a single main gate line 3 is connected to at least one sub-gate line 4.
[0072] Optionally, in some embodiments, adjacent main gate lines 3 are interconnected, and adjacent sub-gate lines 4 are interconnected.
[0073] Based on the above embodiments of this application, another embodiment of this application also provides a method for fabricating an electrode structure, such as... Figure 5 As shown, Figure 5 A flowchart illustrating a method for fabricating an electrode structure according to an embodiment of this utility model. The method for fabricating the electrode structure provided in this application includes:
[0074] Step S01, as follows Figure 6 As shown, a substrate 100 is provided, one side surface of the substrate 100 has an ohmic contact layer 1, and one side surface of the substrate 100 is the light-emitting surface of the LED chip.
[0075] like Figure 7 As shown, a pad electrode preset area 2' and a trench preset area C' are defined on the part of the ohmic contact layer 1 that is away from the light-emitting surface.
[0076] In one optional embodiment of this application, the pad electrode preset area 2' and the trench preset area C' are formed by means of spin coating, exposure, development, etc.
[0077] Step S02, as follows Figure 8 As shown, the ohmic contact layer 1 of the trench preset area C' is etched to form the trench C.
[0078] In one optional embodiment of this application, etching is included, but not limited to, using a dry etching process such as inductively coupled plasma (ICP) to remove photoresist and form trench C.
[0079] In an optional embodiment of this application, such as Figure 9 As shown, the bottom of trench C exposes the ohmic contact layer 1.
[0080] In another optional embodiment of this application, such as Figure 10 As shown, the trench C penetrates the ohmic contact layer 1, and the bottom of the trench C exposes the light surface.
[0081] Step S03, as Figures 11 to 12 As shown, an insulating layer 5 is deposited on the sidewalls and bottom of trench C to form a channel D.
[0082] It should be noted that in this embodiment, in Figure 9 The device is fabricated on the structure shown, and in other embodiments it can also be fabricated on... Figure 10 The fabrication process is carried out on the device structure shown, which will not be described in detail here.
[0083] In an optional embodiment of this application, the insulating layer 5 may be formed using an atomic layer deposition (ALD) apparatus, including but not limited to.
[0084] Step S04, as Figures 13 to 14 As shown, sub-grid lines 4 are vapor-deposited within channel D.
[0085] Step S05, as follows Figure 15 As shown, an insulating layer 5 is deposited again so that the sub-gate line 4 is covered by the insulating layer 5.
[0086] Step S06, as follows Figures 16 to 18 As shown, the patterned insulating layer 5 forms through holes T with several exposed sub-gate lines 4, and the ohmic contact layer 1 of the pad electrode preset area 2' is removed to form a groove Q that exposes the light surface, and the sidewall of the groove Q exposes a portion of the sub-gate lines 4.
[0087] In an optional embodiment of this application, reference is made to... Figure 17 As shown, the patterned insulating layer 5 forms through-holes T with several exposed sub-gate lines 4, while also exposing a portion of the ohmic contact layer 1 on the sidewall of the trench C.
[0088] In one optional embodiment of this application, the through-hole photolithography pattern is formed by means of spin coating, exposure, development, etc., including but not limited to using BOE etching followed by removal of photoresist to simultaneously form through-hole T and groove Q, and expose part of the ohmic contact layer 1 on the sidewall of the trench C.
[0089] Step S07, Reference Figures 2 to 3 As shown, the main gate line 3 and the pad electrode 2 are fabricated;
[0090] Main gate lines 3 are vapor-deposited on a portion of the surface of the ohmic contact layer 1, and connected to sub-gate lines 4 by filling each through-hole T.
[0091] Electrode 2 is deposited on the Q-groove pad to connect with the main gate line 3 and the sub-gate line 4, and is spaced apart from the ohmic contact layer 1.
[0092] In another embodiment of this application, an LED chip is also provided, such as Figure 19 As shown, the LED chip provided in this application embodiment includes:
[0093] The stacked structure includes at least a light-emitting structure 200, which includes a first type semiconductor layer 20, an active region 30 and a second type semiconductor layer 40 stacked sequentially. The side of the light-emitting structure 200 closest to the first type semiconductor layer 20 is the light-emitting surface of the LED chip.
[0094] The first electrode 6 adopts any of the above-mentioned electrode structures and is electrically connected to the first type semiconductor layer 20.
[0095] The second electrode 7 is electrically connected to the second type semiconductor layer 40.
[0096] Optionally, in this embodiment, the doping type of the ohmic contact layer 1 can be type I doping.
[0097] Optionally, in this embodiment, the second electrode 7 is located on the side of the light-emitting structure 200 away from the light-emitting surface.
[0098] Optionally, in some embodiments, reference is made to... Figure 19 As shown, the stacked structure also includes a dielectric film layer 8, a metal reflective layer 9, a metal bonding layer 10, and a conductive substrate 11 disposed between the second type semiconductor layer 40 and the second electrode 7 and stacked sequentially. The conductive substrate 11 is connected to the second electrode 7, and the dielectric film layer 8 is connected to the second type semiconductor layer 40. The dielectric film layer 8 is provided with a conductive hole, and a conductive metal 12 that conducts through the metal reflective layer 9 and the second type semiconductor layer 40 is provided in the conductive hole.
[0099] The first type semiconductor layer 20 includes a first type confinement layer 23, a first type current spreading layer 22 and a first type roughening layer 21 sequentially stacked on the surface of the active region 30 toward the direction of the first electrode 6;
[0100] The second type semiconductor layer 40 includes a second type confinement layer 41 and a second type current spreading layer 42 sequentially stacked on the surface of the active region 30 in the direction of the second electrode 7.
[0101] In an optional embodiment of this application, the material of the first type confinement layer 23 includes, but is not limited to, AlInP; the material of the first type current spreading layer 22 includes, but is not limited to, AlGaInP; and the material of the first type roughening layer 21 includes, but is not limited to, AlGaInP.
[0102] In an optional embodiment of this application, the material of the second type confinement layer 41 includes, but is not limited to, AlInP; the material of the second type current spreading layer 42 includes, but is not limited to, GaP.
[0103] Based on the above embodiments of this application, another embodiment of this application also provides a method for manufacturing an LED chip, such as... Figure 20 As shown, Figure 20 A flowchart illustrating a method for manufacturing an LED chip according to an embodiment of this utility model. The method for manufacturing an LED chip according to this application includes:
[0104] Step 1: Prepare a stacked structure, which includes at least 200 light-emitting structures;
[0105] The light-emitting structure 200 includes a first type semiconductor layer 20, an active region 30 and a second type semiconductor layer 40 stacked sequentially along the growth direction. The side of the light-emitting structure 200 closest to the first type semiconductor layer 20 is the light-emitting surface of the LED chip.
[0106] Step 2: Prepare the first electrode 6. The first electrode 6 adopts any of the electrode structures mentioned above and forms an electrical connection with the first type semiconductor layer 20.
[0107] Step 3: Prepare a second electrode 7 on the side of the light-emitting structure 200 away from the light-emitting surface, and form an electrical connection between the second electrode 7 and the second type semiconductor layer 40.
[0108] In an optional embodiment of this application, in order to simplify the manufacturing process, the fabrication of the ohmic contact layer 1 in the electrode structure is carried out in advance during the process of preparing the stacked structure in step one. The ohmic contact layer 1 is located on the light-emitting surface, providing a basis for the fabrication of the first electrode 6.
[0109] Based on the above embodiments, in an optional embodiment of this application, such as Figure 21 As shown, Figure 21 A flowchart of step one provided in the embodiments of this utility model. Step one provided in the embodiments of this application specifically includes:
[0110] Step A01, as follows Figure 22 As shown, a growth substrate 01 is provided, and an epitaxial structure is grown on the growth substrate 01;
[0111] The epitaxial structure includes a buffer layer 02, an etch stop layer 03, an ohmic contact layer 1, and a light-emitting structure 200, which are stacked sequentially along the growth direction.
[0112] In one optional embodiment of this application, epitaxial structures are grown using a method including but not limited to metal-organic chemical vapor deposition (MOCVD).
[0113] Optionally, in this embodiment, the material of the growth substrate 01 includes, but is not limited to, GaAs.
[0114] Optionally, in this embodiment, the doping type of the buffer layer 02, the corrosion stop layer 03, and the ohmic contact layer 1 can be type I doping.
[0115] Optionally, in this embodiment, the material of the buffer layer 02 includes, but is not limited to, GaAs; the material of the corrosion stop layer 03 includes, but is not limited to, GaInP; and the material of the ohmic contact layer 1 includes, but is not limited to, GaAs.
[0116] Step A02, as follows Figure 23 As shown, a dielectric film layer 8 is deposited on the second type semiconductor layer 40, and a conductive hole penetrating the dielectric film layer 8 is formed. Then, a conductive metal 12 is fabricated in the conductive hole.
[0117] Step A03, as follows Figure 24 As shown, after the metal reflective layer 9 is deposited on the dielectric film layer 8, the conductive substrate 11 is bonded to the metal reflective layer 9 through the metal bonding layer 10. The metal bonding layer 10 is located on the side of the metal reflective layer 9 away from the dielectric film layer 8.
[0118] Step A04, as follows Figure 25 As shown, the growth substrate 01, buffer layer 02 and etching stop layer 03 are removed in sequence to expose the ohmic contact layer 1.
[0119] Based on the above embodiments, in an optional embodiment of this application, the first type semiconductor layer 20 includes a first type roughening layer 21, a first type current spreading layer 22 and a first type confinement layer 23 stacked sequentially along the growth direction; the second type semiconductor layer 40 includes a second type confinement layer 41 and a second type current spreading layer 42 stacked sequentially along the growth direction.
[0120] Based on the above embodiments, in an optional embodiment of this application, in step three, the second electrode 7 is formed on the side surface of the conductive substrate 11 facing away from the metal bonding layer 10.
[0121] In summary, the above technical solution achieves the following results:
[0122] This embodiment provides an electrode structure applied to an LED chip. The electrode structure includes: an ohmic contact layer 1 located on one side surface of a substrate 100, a pad electrode 2, and a main gate line 3 and a sub-gate line 4 connected to the pad electrode 2. One side surface of the substrate 100 is the light-emitting surface of the LED chip. The pad electrode 2 is spaced apart from the ohmic contact layer 1. A portion of the surface of the ohmic contact layer 1 has a trench C extending towards the light-emitting surface. The sub-gate line 4 is embedded in the trench C, covered by an insulating layer 5. The sub-gate line 4 is insulated from the ohmic contact layer 1 by the insulating layer 5, allowing current to flow from the pad electrode 2 and simultaneously through the main gate line 3 and the sub-gate line 4, forming two parallel current conduction paths. The insulating layer has several through-holes exposing the sub-gate lines. The main gate line 3 is located on the portion of the ohmic contact layer 1 facing away from the light-emitting surface and is connected to the sub-gate line 4 by filling each through-hole T, so that the main gate line 3 contacts the ohmic contact layer 1. The via T forms a low-resistivity interface and serves as a current conduction channel between the main gate line 3 and the sub-gate line 4. Due to continuous current injection, the potential of the sub-gate line 4 continuously increases due to the accumulation of charge. Meanwhile, the current in the main gate line 3 is introduced into the light-emitting area inside the LED chip through the ohmic contact layer 1, and the potential remains stable. Since current flows from high potential to low potential, during the current conduction process, the current in the sub-gate line 4 is injected into the main gate line 3 at multiple points through the via T, so that the sub-gate line 4 provides compensation for the current in the main gate line 3, thereby enhancing the current conduction of the main gate line 3. This solves the problem of difficult current conduction and uneven current distribution at the far end of the main gate line 3 due to excessive transmission distance, thereby enhancing the current extension of the electrode structure to the edge of the light-emitting area of the LED chip, making the current distribution more uniform. Moreover, the current extension effect can be achieved without increasing the area ratio of the main gate line 3, increasing the effective light-emitting area, and thus improving the light emission uniformity and luminous efficiency of the LED chip.
[0123] In addition, the sub-grid lines are embedded in the trench by being wrapped in an insulating layer, and the main grid lines are located on the part of the ohmic contact layer away from the light-emitting surface and are connected to the sub-grid lines by filling each through hole, which effectively avoids the risk of existing fine electrode grid lines falling off and enhances the robustness of the electrode structure.
[0124] Furthermore, by setting the horizontal cross-sectional area of each via to gradually increase in the direction away from the pad electrode, the area of the current conduction channel between the main gate line and the sub-gate line is increased, thereby strengthening the current compensation of the sub-gate line to the main gate line away from the pad electrode, improving the current expansion effect of the electrode structure, and thus making the current distribution more uniform.
[0125] Furthermore, by setting the spacing between adjacent vias to gradually decrease in the direction away from the pad electrode, the density of the current conduction channels between the main gate line and the sub-gate line is increased, thereby strengthening the current compensation of the sub-gate line to the main gate line away from the pad electrode, improving the current expansion effect of the electrode structure, and thus making the current distribution more uniform.
[0126] Furthermore, by setting the width of the sub-gate lines to increase linearly or non-linearly along the direction away from the pad electrode, it is possible not only to enhance the current compensation of the main gate lines away from the pad electrode by the sub-gate lines, improve the current expansion effect of the electrode structure, and make the current distribution more uniform, but also to increase the current expansion channel by the sub-gate lines, which is equivalent to increasing the cross-sectional area of current transmission. Therefore, it can reduce the current congestion effect, reduce the resistance, and avoid the problem of local overheating caused by current congestion of the sub-gate lines near the pad electrode.
[0127] Furthermore, by setting a partial ohmic contact layer covering the sidewall of the trench with the main grid line, not only can the robustness of the electrode structure be enhanced, but the ohmic contact area between the main grid line and the ohmic contact layer can also be increased, the current channel can be enlarged, and the resistance can be reduced, thereby reducing the LED chip voltage, improving the reliability of the LED chip, suppressing light decay, and reducing energy consumption.
[0128] Furthermore, by setting the electrode structure to include several pad electrodes, several main gate lines, and several sub-gate lines, the current expansion effect of the electrode structure can be improved, thereby making the current distribution more uniform.
[0129] The electrode structure fabrication method provided in this embodiment achieves the beneficial effects of the above-mentioned electrode structure while being simple to fabricate, low in preparation cost, and easy to mass-produce.
[0130] This embodiment provides an LED chip, comprising: a stacked structure, the stacked structure including at least a light-emitting structure, the light-emitting structure including a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially, the side of the light-emitting structure near the first type semiconductor layer being the light-emitting surface of the LED chip; a first electrode, which adopts any of the above-mentioned electrode structures and is electrically connected to the first type semiconductor layer; and a second electrode, which is electrically connected to the second type semiconductor layer. By setting the first electrode to adopt any of the above-mentioned electrode structures, the current extension of the first electrode to the edge of the light-emitting region of the LED chip is enhanced, making the current distribution more uniform, thereby improving the light emission uniformity and luminous efficiency of the LED chip.
[0131] This embodiment provides a method for manufacturing an LED chip that achieves the beneficial effects of the aforementioned LED chip while being simple to manufacture, low in production cost, and easy to scale up for mass production.
[0132] Those skilled in the art should understand that in the disclosure of this utility model, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as a limitation of this utility model.
[0133] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0134] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An electrode structure applied to an LED chip, characterized in that, The electrode structure includes: an ohmic contact layer located on one side surface of the substrate, a pad electrode, and a main gate line and a sub-gate line connected to the pad electrode, wherein one side surface of the substrate is the light-emitting surface of the LED chip; The pad electrodes are spaced apart from the ohmic contact layer. A portion of the surface of the ohmic contact layer has a groove extending toward the light-emitting surface. The sub-gate lines are embedded in the grooves by being covered by an insulating layer. The insulating layer has several through holes exposing the sub-gate lines. The main gate line is located on a portion of the ohmic contact layer away from the light-emitting surface and is connected to the sub-gate lines by filling each of the through holes. The current of the sub-gate lines is injected into the main gate line at multiple points through each of the through holes.
2. The electrode structure according to claim 1, characterized in that: The horizontal cross-sectional area of each of the vias gradually increases in the direction away from the pad electrode.
3. The electrode structure according to claim 1, characterized in that: The spacing between adjacent vias gradually decreases in the direction away from the pad electrode.
4. The electrode structure according to claim 1, characterized in that: The width of the sub-gate line increases linearly or non-linearly along the direction away from the pad electrode.
5. The electrode structure according to claim 1, characterized in that: The main grid line covers a portion of the ohmic contact layer on the sidewall of the trench.
6. The electrode structure according to claim 1, characterized in that: The bottom of the trench exposes the ohmic contact layer; Alternatively, the trench extends through the ohmic contact layer, and the bottom of the trench exposes the light-emitting surface.
7. The electrode structure according to claim 1, characterized in that: The electrode structure includes a plurality of the pad electrodes, a plurality of the main gate lines, and a plurality of the sub-gate lines.
8. The electrode structure according to claim 1, characterized in that: Each of the pad electrodes is connected to at least one main gate line and at least one sub-gate line, and each main gate line is connected to at least one sub-gate line.
9. An LED chip, characterized in that, include: A stacked structure, the stacked structure including at least a light-emitting structure, the light-emitting structure including a first type semiconductor layer, an active region and a second type semiconductor layer stacked in sequence, the side of the light-emitting structure near the first type semiconductor layer being the light-emitting surface of the LED chip; The first electrode adopts the electrode structure described in any one of claims 1 to 8 and is electrically connected to the first type of semiconductor layer; The second electrode is electrically connected to the second type of semiconductor layer.
10. The LED chip according to claim 9, characterized in that: The stacked structure further includes a dielectric film layer, a metal reflective layer, a metal bonding layer, and a conductive substrate disposed between the second type semiconductor layer and the second electrode and stacked sequentially. The conductive substrate is connected to the second electrode, and the dielectric film layer is connected to the second type semiconductor layer. The dielectric film layer is provided with a conductive hole, and the conductive hole is provided with a conductive metal that conducts through the metal reflective layer and the second type semiconductor layer. The first type of semiconductor layer includes a first type of confinement layer, a first type of current spreading layer, and a first type of roughening layer sequentially stacked on the surface of the active region toward the first electrode; The second type of semiconductor layer includes a second type of confinement layer and a second type of current spreading layer sequentially stacked on the surface of the active region toward the direction of the second electrode.