Semiconductor device

Abstract

A semiconductor device includes a first semiconductor substrate and a plurality of first metal lines extending in a first direction in the first semiconductor substrate. Each of the first metal lines includes a plurality of first discrete portions spaced apart along the first direction. The semiconductor device further includes a second semiconductor substrate and a second metal line under each of the first metal lines and extending in the first direction in the second semiconductor substrate. The second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the second discrete portions are alternately interleaved with the first discrete portions along the first direction. The semiconductor device further includes a bonding connector connecting the second discrete portions to corresponding ones of the first metal lines.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] As consumer devices shrink to meet consumer demands, the size of individual components within these devices inevitably decreases. Semiconductor devices, which constitute the main components of devices such as mobile phones, tablets, and the like, also face pressure to become smaller, with individual components within these devices (e.g., transistors, resistors, capacitors, etc.) facing corresponding pressure to reduce size. To achieve smaller horizontal or lateral footprints and / or increased density in semiconductor die packaging, various semiconductor device packaging technologies can be used to incorporate one or more semiconductor dies into a single package. Some three-dimensional (3D) integrated circuit (IC) device structures, such as wafer-on-wafer (WoW) structures, are formed by stacking and bonding multiple IC devices (i.e., chips) at the semiconductor wafer level. 3D IC device structures offer improved integration density and advantages such as higher speed and greater bandwidth due to the reduced interconnect length between stacked chips.

[0003] One enablement technology used in semiconductor device manufacturing processes is the formation of ultra-thick metal (UTM) layers for inductors in radio frequency (RF) integrated circuits, antennas with low-loss requirements, high-voltage (HV) integrated circuits for power supplies or display drivers, and high-current power lines with low-impedance paths and minimum voltage drop requirements.

[0004] However, conventional semiconductor processing techniques are not easily compatible with ultra-thick metal (UTM). For example, as wafer stacking technology becomes increasingly popular, wafer warpage induced by metal stress caused by long ultra-thick metal wires is a major process challenge. Wafer bonding processes and subsequent back-side silicon wafer processes can be affected by warpage induced on the wafer. Therefore, advancements in the formation of structures with ultra-thick metal routing are necessary to reduce warpage and prevent wafer deformation due to metal stress, and further improvements are needed to meet required design standards, thus keeping progress toward increasingly smaller components. Utility Model Content

[0005] One embodiment of this disclosure is a semiconductor device including a first semiconductor substrate and a plurality of first metal lines extending in the first semiconductor substrate along a first direction. Each of the first metal lines includes a plurality of first discrete portions spaced apart along the first direction. The semiconductor device further includes a second semiconductor substrate and a second metal line below each of the first metal lines and extending in the second semiconductor substrate along the first direction. The second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the second discrete portions and the first discrete portions alternate along the first direction. The semiconductor device further includes a bonding connector that connects the second discrete portions to corresponding portions in the first metal lines.

[0006] Another embodiment of this disclosure is a semiconductor device including a first semiconductor substrate, a plurality of first metal lines extending along a first direction in the first semiconductor substrate, and a first dummy line extending along a second direction in the first semiconductor substrate. Each of the first metal lines includes a plurality of first discrete portions spaced apart along the first direction, and the first dummy line is positioned between a plurality of adjacent first discrete portions. The semiconductor device further includes a second semiconductor substrate and a second metal line below each of the first metal lines and extending along the first direction in the second semiconductor substrate. The second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the second discrete portions and the first discrete portions alternate along the first direction. The semiconductor device further includes a bonding connector that connects the second discrete portions to corresponding portions in the first metal lines.

[0007] Another embodiment of this disclosure is a semiconductor device including a first semiconductor substrate and a plurality of first metal lines extending in the first semiconductor substrate along a first direction. Each of the first metal lines includes a plurality of first discrete portions spaced apart along the first direction. The semiconductor device further includes a second semiconductor substrate, a second metal line below each of the first metal lines and extending in the second semiconductor substrate along the first direction, and a second dummy line extending in the second semiconductor substrate along a second direction. The second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the second discrete portions and the first discrete portions alternately intersect along the first direction. The second dummy line is positioned between a plurality of adjacent second discrete portions. The semiconductor device further includes a bonding connector that connects the second discrete portions to corresponding portions in the first metal lines. Attached Figure Description

[0008] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be emphasized that, according to industry standards, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0009] Figure 1 The illustration shows a process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0010] Figure 2 A perspective view of a semiconductor device according to an embodiment of the present disclosure is shown;

[0011] Figure 3A , Figure 3B ,and Figure 3C Showing a bottom view and a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 4 The illustration shows a process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0013] Figure 5 A perspective view of a semiconductor device according to an embodiment of the present disclosure is shown;

[0014] Figure 6A , Figure 6B , Figure 6C , Figure 6D ,and Figure 6E The figures show a bottom view and a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;

[0015] Figure 7 The illustration shows a process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0016] Figure 8 A perspective view of a semiconductor device according to an embodiment of the present disclosure is shown;

[0017] Figure 9A , Figure 9B , Figure 9C , Figure 9D ,and Figure 9E Showing a bottom view and a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0018] [Symbol Explanation]

[0019] 100: Process Flow

[0020] 200: Semiconductor devices

[0021] 201: First Semiconductor Wafer

[0022] 202: First Metal Wire

[0023] 203: First Discrete Part

[0024] 203a, 203b: First discrete part

[0025] 211: Second semiconductor wafer

[0026] 213: Second Discrete Part

[0027] 213a, 213b: Second discrete part

[0028] 221: Connector

[0029] 221a: First mating connector

[0030] 221b: Second mating connector

[0031] 400: Process Flow

[0032] 500: Semiconductor Devices

[0033] 501: First Semiconductor Wafer

[0034] 502: First Metal Wire

[0035] 503: First Discrete Part

[0036] 503a, 503b: First discrete part

[0037] 504: First Dummy Line

[0038] 505: First Discrete Dummy Part

[0039] 505a: First Discrete Dummy Part

[0040] 511: Second semiconductor wafer

[0041] 512: Second metal wire

[0042] 513: Second Discrete Part

[0043] 513a: Second Discrete Part

[0044] 514: Second Dummy Line

[0045] 515: Second Discrete Dummy Part

[0046] 515a: Second Discrete Dummy Part

[0047] 521: Connector

[0048] 521a: First mating connector

[0049] 521b: Second mating connector

[0050] 700: Process Flow

[0051] 800: Semiconductor Device

[0052] 801: First Semiconductor Wafer

[0053] 802: First Metal Wire

[0054] 803: First Discrete Part

[0055] 803a, 803b: First discrete part

[0056] 804: First Dummy Line

[0057] 805: First Discrete Dummy Part

[0058] 805a: First Discrete Dummy Part

[0059] 806: Second Dummy Line

[0060] 807: Second Discrete Dummy Part

[0061] 807a: Second Discrete Dummy Part

[0062] 808: Second metal wire

[0063] 809: Second Discrete Part

[0064] 809a: Second Discrete Part

[0065] 811: Second semiconductor wafer

[0066] 812: Third metal wire

[0067] 813: Third Discrete Part

[0068] 813a: Third Discrete Part

[0069] 814: Third Dummy Line

[0070] 815: Third Discrete Dummy Part

[0071] 815a: Third Discrete Dummy Part

[0072] 816: Fourth Dummy Line

[0073] 817: Fourth Discrete Virtual Part

[0074] 817a: Fourth Discrete Dummy Part

[0075] 818: Fourth Metal Wire

[0076] 819: Fourth Discrete Part

[0077] 819a: Fourth Discrete Part

[0078] 821: Connector

[0079] 821a: First mating connector

[0080] 821b: Second mating connector

[0081] 821c: Third mating connector

[0082] 832: Cross-shaped metal wire

[0083] S110~S150: Operation

[0084] S410~S470: Operation

[0085] S710~S770: Operation Detailed Implementation

[0086] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific embodiments and instances of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the dimensions of an element are not limited to the range or values ​​disclosed, but depend on the process conditions and / or the desired nature of the apparatus. Furthermore, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed and inserted between the first and second features such that the first and second features are not in direct contact. For simplicity, various features may be drawn arbitrarily at different scales.

[0087] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly. Additionally, the term “made of” may mean “comprising” or “consisting of.”

[0088] Ultra-thick metal (UTM) windings are used to reduce the voltage drop (IR drop) in back-end-of-the-line (BEOL) circuit designs. However, UTM long wires are typically wound in one direction and can deteriorate due to metal stress, inducing unbalanced wafer warpage on the wafer surface. Thus, when the UTM approach is applied to silicon processes, wafer-on-wafer (WoW) structures can be affected by deterioration and unbalanced wafer warpage. For example, significant wafer warpage can lead to problems in wafer bonding processes such as wafer bond slip, bubbles between stacked wafer interfaces, and challenging die-to-die alignment accuracy. Furthermore, back-side silicon wafer processes, such as lithography alignment and / or packaging difficulties, can also be affected by wafer deformation due to poor wafer bonding performance. Backside pressure faults (BSPF) on the electrostatic chuck can also occur due to significant wafer warpage. The embodiments disclosed herein provide an improved ultra-thick metal (UTM) winding structure and a method for forming the same, thereby reducing wafer warpage caused by metal stress. For example, ultra-thick metal (UTM) with a diced wire structure reduces wafer warpage and releases stress, thereby improving the performance of wafer bonding and back-side silicon wafer processes.

[0089] In some embodiments of this disclosure, ultra-thick metal (UTM) with a diced wire structure is formed. Those skilled in the art will understand that this disclosure can be applied to the formation of other structures.

[0090] Figure 1 The figure illustrates a process flow 100 for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 2 A perspective view of a semiconductor device 200 according to an embodiment of the present disclosure is shown. In some embodiments, such as Figure 2 As shown, a first semiconductor wafer 201 is provided in operation S110. A portion of the first semiconductor wafer 201 is as follows: Figure 2 As shown, to clearly and better illustrate the features of this disclosure.

[0091] Figure 3A , Figure 3B ,and Figure 3C The figures show a bottom view and a cross-sectional view of a semiconductor device 200 according to an embodiment of the present disclosure. Figure 3A Display as shown Figure 2 The semiconductor device 200 shown is viewed from below. Figure 3B Show along Figure 2The diagram shows a cross-sectional view of a semiconductor device 200 cut in the plane of AA'. Figure 3C Show along Figure 2 The diagram shows a cross-sectional view of a semiconductor device 200 cut in the BB' plane.

[0092] In some embodiments, the first semiconductor wafer 201 includes a first substrate (not shown) and a first dielectric layer (not shown) on the first substrate. The first substrate may be made of silicon, although it may also be formed of other group III, group IV, and / or group V elements, such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the first dielectric layer is made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or the like.

[0093] In some embodiments, the first circuit is formed on the first substrate. The first circuit may be any type of circuit suitable for a particular application. For example, the first circuit may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and / or the like.

[0094] Reference Return Figure 1 In some embodiments, such as Figure 2 , Figure 3B ,and Figure 3C As shown, in operation S120, a plurality of first metal lines 202 are formed in the first semiconductor wafer 201. For example, as Figure 2 As shown, a plurality of first metal lines 202 extend along the Y direction. The plurality of first metal lines 202 may be distributed in the X direction. The X direction may be perpendicular to the Y direction. In some embodiments, the angle between the X direction and the Y direction is an acute angle.

[0095] In some embodiments, a plurality of first metal wires 202 are uniformly distributed in the X direction. In some embodiments, the plurality of first metal wires 202 have multiple sets of different first wire pitches along the X direction.

[0096] In some embodiments, a plurality of first metal lines 202 are formed by forming trenches or vias in a first semiconductor wafer 201 according to a design pattern, and then filling the trenches or vias with a conductive material. Those skilled in the art will understand that other methods for forming a plurality of first metal lines 202 can also be applied to the first semiconductor wafer 201.

[0097] In some embodiments, the plurality of first metal lines 202 have a thickness in the range of 1 μm to 20 μm. In some embodiments, the plurality of first metal lines 202 have a thickness in the range of 2 μm to 10 μm.

[0098] In some embodiments, the plurality of first metal wires 202 comprise copper. In some embodiments, the plurality of first metal wires 202 comprise copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like.

[0099] In some embodiments, such as Figure 2 and Figure 3B As shown, each of the plurality of first metal lines 202 includes a plurality of first discrete portions 203 (e.g., 203a and 203b). In some embodiments, each of the plurality of first discrete portions 203 (e.g., 203a) is separated from an adjacent first discrete portion (e.g., 203b).

[0100] In some embodiments, a plurality of first discrete portions 203 (e.g., 203a and 203b) are spaced apart from each other and uniformly distributed in the Y direction. In some embodiments, the plurality of first discrete portions 203 (e.g., 203a and 203b) have multiple sets of first discrete portion pitches along the Y direction.

[0101] Reference Return Figure 1 In some embodiments, such as Figure 2 As shown, a second semiconductor wafer 211 is provided in operation S130.

[0102] In some embodiments, the second semiconductor wafer 211 includes a second substrate (not shown) and a second dielectric layer (not shown) on the second substrate. The second substrate may be made of silicon, although it may also be formed of other group III, group IV, and / or group V elements, such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the second dielectric layer is made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or the like.

[0103] In some embodiments, the second circuit is formed on the second substrate. The second circuit can be any type of circuit suitable for a particular application. For example, the second circuit may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and / or the like.

[0104] Reference Return Figure 1 In some embodiments, such as Figure 2 , Figure 3A , Figure 3B ,and Figure 3C As shown, in operation S140, a plurality of second metal lines 212 are formed in the second semiconductor wafer 211. For example, the plurality of second metal lines 212 extend along the Y direction. The plurality of second metal lines 212 are distributed in the X direction. A portion of the second semiconductor wafer 211 is as follows: Figure 2 As shown, to clearly and better illustrate the features of this disclosure.

[0105] In some embodiments, such as Figure 2 and Figure 3C As shown, each of the plurality of second metal lines 212 is positioned below a corresponding first metal line of the plurality of first metal lines 202. For example, each of the plurality of second metal lines 212 is aligned with a corresponding first metal line of the plurality of first metal lines 202 along the Z direction.

[0106] In some embodiments, such as Figure 2 and Figure 3A As shown, a plurality of second metal wires 212 are uniformly distributed in the X direction. In some embodiments, along the X direction, the second pitch P2 of the plurality of second metal wires 212 is equal to the first pitch P1 of the plurality of first metal wires 202. In some other embodiments, the plurality of second metal wires 212 have multiple sets of different second wire pitches along the X direction.

[0107] In some embodiments, a plurality of second metal lines 212 are formed by forming trenches or vias in a second semiconductor wafer 211 according to a design pattern, and then filling the trenches or vias with a conductive material. Those skilled in the art will understand that other methods for forming a plurality of second metal lines 212 can also be applied to the second semiconductor wafer 211.

[0108] In some embodiments, the plurality of second metal lines 212 have a thickness in the range of 1 μm to 20 μm. In some embodiments, the plurality of second metal lines 212 have a thickness in the range of 2 μm to 10 μm.

[0109] In some embodiments, the plurality of second metal wires 212 comprise copper. In some embodiments, the plurality of second metal wires 212 comprise copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like.

[0110] In some embodiments, each of the plurality of second metal lines 212 includes a plurality of second discrete portions 213 (e.g., 213a and 213b). In some embodiments, each of the plurality of second discrete portions 213 (e.g., 213a) is separated from an adjacent second discrete portion (e.g., 213b). In some embodiments, as Figure 2 and Figure 3BAs shown, a plurality of second discrete portions 213 (e.g., 213a and 213b) and a plurality of first discrete portions 203 (e.g., 203a and 203b) alternately intersect along a first direction.

[0111] In some embodiments, a plurality of second discrete portions 213 are spaced apart from each other and uniformly distributed in the Y direction. In some embodiments, along the Y direction, the fourth portion pitch P4 of the plurality of second discrete portions 213 is equal to the third portion pitch P3 of the plurality of first discrete portions 203. In some embodiments, the plurality of second discrete portions 213 (e.g., 213a and 213b) have multiple sets of second discrete portion pitches along the Y direction.

[0112] Reference Return Figure 1 In some embodiments, such as Figure 2 , Figure 3B ,and Figure 3C As shown, the mating connector 221 is formed in operation S150.

[0113] In some embodiments, the coupling connector 221 is configured to connect each of a plurality of first discrete portions 203 to an adjacent first discrete portion 203 via a plurality of second discrete portions 213. For example, in some embodiments, a first discrete portion 203a is connected to a corresponding second discrete portion 213a via a first coupling connector 221a. Then, the corresponding second discrete portion 213a is connected to an adjacent first discrete portion 203b via a second coupling connector 221b. In some embodiments, the plurality of first discrete portions 203 of the first metal wires of a plurality of first metal wires 202 are electrically connected to each other.

[0114] In some embodiments, the bonding of the bonding connector 221 to the first semiconductor wafer 201 and the second semiconductor wafer 211 is achieved through a wafer-on-wafer (WoW) bonding process. In the wafer-on-wafer bonding process, the first semiconductor wafer 201 is bonded to the second semiconductor wafer 211, and the bonding connector 221 is bonded to a plurality of first metal lines 202 and a plurality of second metal lines 212 by metal-to-metal direct bonding. In some embodiments, a first discrete portion 203a and a corresponding second discrete portion 213a are bonded to the first bonding connector 221a by metal-to-metal direct bonding. In some embodiments, an annealing process is performed after the wafer-on-wafer bonding process to further enhance the bonding between the first semiconductor wafer 201 and the second semiconductor wafer 211. Through the wafer-on-wafer bonding process, the bonding connector 221 can connect each of the plurality of first discrete portions 203 of the first metal line 202 to a plurality of second discrete portions 213 of the corresponding second metal line 212.

[0115] In some embodiments, the mating connector 221 is made of a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, combinations thereof, and / or the like.

[0116] In ultra-thick metal (UTM) with diced wire structures, multiple discrete sections (e.g., 203 and 213) replace long continuous metal lines extending in one direction, allowing metal stress to be released, thereby reducing wafer warpage and achieving equilibrium. For a 12-inch wafer with associated continuous metal lines and a thickness of 3.5 μm, the wafer warpage in the X direction is approximately 280 μm, and the warpage in the Y direction is approximately 90 μm. Due to the warpage, the wafer's bow offset is approximately 190 μm. Conversely, in some embodiments disclosed herein, for a 12-inch wafer with metal lines and a thickness of 3.5 μm, the wafer warpage in the X direction is reduced to approximately 93 μm, and the warpage in the Y direction is reduced to approximately -11 μm. Due to the warpage, the wafer's bow offset is approximately 104 μm. Compared to warpage in conventional wafers, the wafer warpage in the X direction is reduced by approximately 67%, and the warpage in the Y direction is reduced by approximately 112%. The bow-shaped offset reduces the bow-shaped offset in conventional wafers by approximately 45%.

[0117] For a pre-bonded wafer with associated continuous metal lines, the warpage of the pre-bonded wafer is approximately 285 μm in the X direction and approximately 89 μm in the Y direction. Due to the warpage, the bow offset of the pre-bonded wafer is approximately 196 μm. Conversely, in some embodiments of this disclosure, the warpage of the pre-bonded wafer in the X direction is reduced to approximately 56 μm and the warpage in the Y direction is reduced to approximately -51 μm. Due to the warpage, the bow offset of the pre-bonded wafer is approximately 107 μm. Compared to warpage in conventional pre-bonded wafers, the warpage in the X direction is reduced by approximately 80%, and the warpage in the Y direction is reduced by approximately 157%. The bow offset is reduced by approximately 45% of the bow offset in conventional pre-bonded wafers. According to some embodiments of this disclosure, the bow value of the wafer warpage in the Y direction is negative. In other words, the bow bends in the opposite direction compared to warpage in conventional pre-bonded wafers. The pre-bonded wafer may have integrated other wafers or structures, and embodiments including negative warpage can further release stress attributable to those additional wafers or structures.

[0118] For a thinned wafer stack structure with conventional continuous metal lines, the warpage of the wafer stack is approximately 377 μm in the X direction and approximately 86 μm in the Y direction. Due to the warpage, the bow offset of the thinned wafer stack structure is approximately 291 μm. Conversely, in some embodiments disclosed herein, the warpage of the thinned wafer stack structure is reduced to approximately -28 μm in the X direction and approximately -161 μm in the Y direction. Due to the warpage, the bow offset of the thinned wafer stack structure is approximately 133 μm. Compared to the warpage in conventional thinned wafer stack structures, the warpage in the X direction is reduced by approximately 107%, and the warpage in the Y direction is reduced by approximately 287%. The bow offset is reduced by approximately 54% of the bow offset in conventional thinned wafer stack structures.

[0119] Figure 4 The illustration shows a process flow 400 for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 5 A perspective view of a semiconductor device 500 according to an embodiment of the present disclosure is shown. In some embodiments, such as Figure 5 As shown, a first semiconductor wafer 501 is provided in operation S410. A portion of the first semiconductor wafer 501 is as follows: Figure 5 As shown, to clearly and better illustrate the features of this disclosure.

[0120] Figure 6A , Figure 6B , Figure 6C , Figure 6D ,and Figure 6E The figures show a bottom view and a cross-sectional view of a semiconductor device 500 according to an embodiment of the present disclosure. Figure 6A Display as shown Figure 5 The semiconductor device 500 shown is viewed from below. Figure 6B Show along Figure 5 The diagram shows a cross-sectional view of a semiconductor device 500 cut in the AA' plane. Figure 6C Show along Figure 5 The diagram shows a cross-sectional view of a semiconductor device 500 cut in the BB' plane.

[0121] Figure 6D Show along Figure 5 The diagram shows a cross-sectional view of a semiconductor device 500 cut in the CC' plane. Figure 6E Show along Figure 5 The diagram shows a cross-sectional view of a semiconductor device 500 cut in the DD' plane.

[0122] In some embodiments, the first semiconductor wafer 501 includes a first substrate (not shown) and a first dielectric layer (not shown) on the first substrate. The first substrate may be made of silicon, although it may also be formed of other group III, group IV, and / or group V elements, such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the first dielectric layer is made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or the like.

[0123] In some embodiments, the first circuit is formed on the first substrate. The first circuit may be any type of circuit suitable for a particular application. For example, the first circuit may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and / or the like.

[0124] Reference Return Figure 4 In some embodiments, such as Figure 5 , Figure 6B ,and Figure 6C As shown, in operation S420, a plurality of first metal lines 502 are formed in the first semiconductor wafer 501. For example, as... Figure 5 As shown, a plurality of first metal lines 502 extend along the Y direction. The plurality of first metal lines 502 may be distributed in the X direction. The X direction may be perpendicular to the Y direction. In some embodiments, the angle between the X direction and the Y direction is an acute angle.

[0125] In some embodiments, a plurality of first metal wires 502 are uniformly distributed in the X direction. In some embodiments, the plurality of first metal wires 502 have multiple sets of different first wire pitches along the X direction.

[0126] In some embodiments, such as Figure 5 and Figure 6B As shown, each of the plurality of first metal lines 502 includes a plurality of first discrete portions 503 (e.g., 503a and 503b). In some embodiments, each of the plurality of first discrete portions 503 (e.g., 503a) is separated from an adjacent first discrete portion (e.g., 503b).

[0127] In some embodiments, a plurality of first discrete portions 503 (e.g., 503a and 503b) are spaced apart from each other and uniformly distributed in the Y direction. In some embodiments, the plurality of first discrete portions 503 (e.g., 503a and 503b) have multiple sets of first discrete portion pitches along the Y direction.

[0128] Reference Return Figure 4 In some embodiments, such as Figure 5 and Figure 6D As shown, in operation S430, a plurality of first dummy lines 504 are formed in the first semiconductor wafer 501. For example, as Figure 5 As shown, a plurality of first dummy lines 504 extend along the X direction. The plurality of first dummy lines 504 may be distributed in the Y direction. In some embodiments, dummy lines such as the plurality of first dummy lines 504 are not electrically connected to other dummy lines or other metal lines. The dummy lines are not electrically connected to other semiconductor devices, such as N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and / or the like.

[0129] In some embodiments, such as Figure 5 As shown, a plurality of first dummy lines 504 are positioned along the Y direction between adjacent first discrete portions 503. For example, the first dummy lines are positioned between two adjacent first discrete portions 503a and 503b.

[0130] In some embodiments, such as Figure 5 As shown, each of the plurality of first dummy lines 504 includes a plurality of first discrete dummy portions 505 (e.g., 505a). In some embodiments, each of the plurality of first discrete dummy portions 505 (e.g., 505a) of the first dummy line 504 is separated from the adjacent first discrete dummy portions of the first dummy line 504.

[0131] In some embodiments, the plurality of first metal lines 502 and the plurality of first dummy lines 504 are formed by forming trenches or vias in the first semiconductor wafer 501 according to a design pattern, and then filling the trenches or vias with a conductive material. Those skilled in the art will understand that other methods for forming the plurality of first metal lines 502 and the plurality of first dummy lines 504 can also be applied to the first semiconductor wafer 501.

[0132] In some embodiments, the plurality of first metal wires 502 and the plurality of first dummy wires 504 are made of the same conductive material. In some embodiments, the plurality of first metal wires 502 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like. In some embodiments, the plurality of first dummy wires 504 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like.

[0133] In some embodiments, the plurality of first metal lines 502 and the plurality of first dummy lines 504 have a thickness in the range of 1 μm to 20 μm. In some embodiments, the plurality of first metal lines 502 and the plurality of first dummy lines 504 have a thickness in the range of 2 μm to 10 μm.

[0134] Reference Return Figure 4 In some embodiments, such as Figure 5 As shown, a second semiconductor wafer 511 is provided in operation S440. A portion of the second semiconductor wafer 511 is as follows: Figure 5 As shown, to clearly and better illustrate the features of this disclosure.

[0135] In some embodiments, the second semiconductor wafer 511 includes a second substrate (not shown) and a second dielectric layer (not shown) on the second substrate. The second substrate may be made of silicon, although it may also be formed of other group III, group IV, and / or group V elements, such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the second dielectric layer is made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or the like.

[0136] In some embodiments, the second circuit is formed on the second substrate. The second circuit can be any type of circuit suitable for a particular application. For example, the second circuit may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and / or the like.

[0137] Reference Return Figure 4 In some embodiments, such as Figure 5 , Figure 6A , Figure 6B ,and Figure 6D As shown, in operation S450, a plurality of second metal lines 512 are formed in the second semiconductor wafer 511. For example, the plurality of second metal lines 512 extend along the Y direction. The plurality of second metal lines 512 are distributed in the X direction.

[0138] In some embodiments, such as Figure 6E As shown, each of the plurality of second metal lines 512 is positioned below a corresponding first metal line of the plurality of first metal lines 502. For example, each of the plurality of second metal lines 512 is aligned with a corresponding first metal line of the plurality of first metal lines 502 along the Z direction.

[0139] In some embodiments, such as Figure 5 and Figure 6A As shown, a plurality of second metal wires 512 are uniformly distributed in the X direction. In some other embodiments, the plurality of second metal wires 512 have multiple sets of different second wire pitches along the X direction.

[0140] In some embodiments, each of the plurality of second metal lines 512 includes a plurality of second discrete portions 513 (e.g., 513a). In some embodiments, each of the plurality of second discrete portions 513 (e.g., 513a) is separated from an adjacent second discrete portion 513. In some embodiments, such as Figure 5 and Figure 6B As shown, a plurality of second discrete portions 513 (e.g., 513a) and a plurality of first discrete portions 503 (e.g., 503a) alternate along a first direction.

[0141] In some embodiments, a plurality of second discrete portions 513 are spaced apart from each other and are uniformly distributed in the Y direction. In some embodiments, the plurality of second discrete portions 513 (e.g., 513a) have multiple sets of second discrete portion pitches along the Y direction.

[0142] Reference Return Figure 4 In some embodiments, such as Figure 5 , Figure 6A ,and Figure 6C As shown, in operation S460, a plurality of second dummy lines 514 are formed in the second semiconductor wafer 511. For example, as Figure 5 As shown, a plurality of second dummy lines 514 extend along the X direction. The plurality of second dummy lines 514 may be distributed in the Y direction. In some embodiments, the dummy lines, such as the plurality of second dummy lines 514, are not electrically connected to each other or to any metal wire. The dummy lines are not electrically connected to semiconductor devices, such as N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and / or the like.

[0143] In some embodiments, such as Figure 5 As shown, a plurality of second dummy lines 514 are positioned along the Y direction between adjacent second discrete portions 513. In some embodiments, the second dummy lines are positioned between two adjacent second discrete portions 513.

[0144] In some embodiments, such as Figure 5As shown, each of the plurality of second dummy lines 514 includes a plurality of second discrete dummy portions 515 (e.g., 515a). In some embodiments, each of the plurality of second discrete dummy portions 515 (e.g., 515a) of the second dummy line 514 is separated from the adjacent second discrete dummy portions of the second dummy line 514.

[0145] In some embodiments, a plurality of second metal lines 512 and a plurality of second dummy lines 514 are formed by forming trenches or vias in a second semiconductor wafer 511 according to a design pattern, and then filling the trenches or vias with a conductive material. Those skilled in the art will understand that other methods for forming a plurality of second metal lines 512 and a plurality of second dummy lines 514 may also be applied to the second semiconductor wafer 511.

[0146] In some embodiments, the plurality of second metal wires 512 and the plurality of second dummy wires 514 are made of the same material. In some embodiments, the plurality of second metal wires 512 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like. In some embodiments, the plurality of second dummy wires 514 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like.

[0147] In some embodiments, the plurality of second metal lines 512 and the plurality of second dummy lines 514 have a thickness in the range of 1 μm to 20 μm. In some embodiments, the plurality of second metal lines 512 and the plurality of second dummy lines 514 have a thickness in the range of 2 μm to 10 μm.

[0148] Reference Return Figure 4 In some embodiments, such as Figure 5 , Figure 6B ,and Figure 6E As shown, the mating connector 521 is formed in operation S470.

[0149] In some embodiments, the coupling connector 521 is configured to connect each of a plurality of first discrete portions 503 to an adjacent first discrete portion 503 via a plurality of second discrete portions 513. For example, a first discrete portion 503a is connected to a corresponding second discrete portion 513a via a first coupling connector 521a. Then, the corresponding second discrete portion 513a is connected to an adjacent first discrete portion 503b via a second coupling connector 521b. In some embodiments, the plurality of first discrete portions 503 of the first metal wires of a plurality of first metal wires 502 are electrically connected to each other.

[0150] In some embodiments, the bonding of the bonding connector 521 to the first semiconductor wafer 501 and the second semiconductor wafer 511 is achieved through a wafer-on-wafer (WoW) bonding process. In the wafer-on-wafer bonding process, the first semiconductor wafer 501 is bonded to the second semiconductor wafer 511, and the bonding connector 521 is bonded to a plurality of first metal lines 502 and a plurality of second metal lines 512 via metal-to-metal direct bonding. For example, a first discrete portion 503a and a corresponding second discrete portion 513a are bonded to the first bonding connector 521a via metal-to-metal direct bonding. In some embodiments, an annealing process is performed after the wafer-on-wafer bonding process to further enhance the bonding between the first semiconductor wafer 501 and the second semiconductor wafer 511. Through the wafer-on-wafer bonding process, the bonding connector 521 can connect each of the plurality of first discrete portions 503 of the first metal line 502 to a plurality of second discrete portions 513 of the corresponding second metal line 512.

[0151] In some embodiments, the mating connector 521 is made of a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, combinations thereof, and / or the like.

[0152] Figure 7 The figure illustrates a process flow 700 for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 8 A perspective view of a semiconductor device 800 according to an embodiment of the present disclosure is shown. In some embodiments, such as Figure 8 As shown, a first semiconductor wafer 801 is provided in operation S710. A portion of the first semiconductor wafer 801 is as follows: Figure 8 As shown, to clearly and better illustrate the features of this disclosure.

[0153] Figure 9A , Figure 9B , Figure 9C , Figure 9D ,and Figure 9E The figures show a bottom view and a cross-sectional view of a semiconductor device 800 according to an embodiment of the present disclosure. Figure 9A Display as shown Figure 8 The semiconductor device 800 shown is viewed from below. Figure 9B Show along Figure 8 The diagram shows a cross-sectional view of a semiconductor device 800 cut in plane AA'. Figure 9C Show along Figure 8 The diagram shows a cross-sectional view of a semiconductor device 800 cut in the BB' plane.

[0154] Figure 9D Show along Figure 8 The diagram shows a cross-sectional view of a semiconductor device 800 cut in the CC' plane. Figure 9E Show along Figure 8 The diagram shows a cross-sectional view of a semiconductor device 800 cut in the DD' plane.

[0155] In some embodiments, the first semiconductor wafer 801 includes a first substrate (not shown) and a first dielectric layer (not shown) on the first substrate. The first substrate may be made of silicon, although it may also be formed of other group III, group IV, and / or group V elements, such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the first dielectric layer is made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or the like.

[0156] In some embodiments, the first circuit is formed on the first substrate. The first circuit may be any type of circuit suitable for a particular application. For example, the first circuit may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and / or the like.

[0157] Reference Return Figure 7 In some embodiments, such as Figure 8 , Figure 9D ,and Figure 9E As shown, in operation S720, a plurality of first metal lines 802 are formed in the first semiconductor wafer 801. For example, as Figure 8 As shown, a plurality of first metal lines 802 extend along the Y direction. The plurality of first metal lines 802 may be distributed in the X direction. The X direction may be perpendicular to the Y direction. In some other embodiments, the angle between the X and Y directions is an acute angle.

[0158] In some embodiments, a plurality of first metal wires 802 are uniformly distributed in the X direction. In some embodiments, the plurality of first metal wires 802 have multiple sets of different first wire pitches along the X direction.

[0159] In some embodiments, such as Figure 8 and Figure 9B As shown, each of the plurality of first metal lines 802 includes a plurality of first discrete portions 803 (e.g., 803a and 803b). In some embodiments, each of the plurality of first discrete portions 803 (e.g., 803a) is separated from an adjacent first discrete portion (e.g., 803b).

[0160] In some embodiments, a plurality of first discrete portions 803 (e.g., 803a and 803b) are spaced apart from each other and uniformly distributed in the Y direction. In some embodiments, the plurality of first discrete portions 803 (e.g., 803a and 803b) have multiple sets of first discrete portion pitches along the Y direction.

[0161] Alternatively, in some embodiments, during operation S720, a plurality of second metal lines 808 are formed in the first semiconductor wafer 801. For example, such as Figure 8 As shown, a plurality of second metal lines 808 extend along the X direction. The plurality of second metal lines 808 may be distributed in the Y direction. In some embodiments, as... Figure 8 As shown, each of the plurality of second metal lines 808 is positioned between adjacent first discrete portions 803. In some embodiments, the second metal line 808 is positioned between two adjacent first discrete portions 803a and 803b.

[0162] In some embodiments, a plurality of second metal wires 808 are uniformly distributed in the Y direction. In some embodiments, the plurality of second metal wires 808 have multiple sets of different second wire pitches along the Y direction.

[0163] In some embodiments, such as Figure 8 and Figure 9B As shown, each of the plurality of second metal lines 808 includes a plurality of second discrete portions 809 (e.g., 809a). In some embodiments, each of the plurality of second discrete portions 809 (e.g., 809a) is separated from an adjacent second discrete portion.

[0164] In some embodiments, a plurality of second discrete portions 809 (e.g., 809a) are uniformly distributed in the X direction. In some embodiments, the plurality of second discrete portions 809 (e.g., 809a) have multiple sets of second discrete portion pitches along the X direction.

[0165] Reference Return Figure 7 In some embodiments, such as Figure 8 and Figure 9B As shown, in operation S730, a plurality of first dummy lines 804 are formed in the first semiconductor wafer 801. For example, as Figure 8 As shown, multiple first dummy lines 804 extend along the X direction. These multiple first dummy lines 804 may be distributed along the Y direction.

[0166] In some embodiments, such as Figure 8 As shown, a plurality of first dummy lines 804 are positioned along the Y direction between adjacent first discrete portions 803. In some embodiments, the first dummy lines are positioned between two adjacent first discrete portions 803a and 803b.

[0167] In some embodiments, such as Figure 8 As shown, each of the plurality of first dummy lines 804 includes a plurality of first discrete dummy portions 805 (e.g., 805a). In some embodiments, each of the plurality of first discrete dummy portions 805 (e.g., 805a) of the first dummy line 804 is separated from the adjacent first discrete dummy portions of the first dummy line 804.

[0168] In some embodiments, a plurality of first discrete dummy portions 805 (e.g., 805a) are uniformly distributed in the X direction. In some embodiments, the plurality of first discrete dummy portions 805 (e.g., 805a) have multiple sets of first dummy portion pitches along the X direction.

[0169] Alternatively, or otherwise, in some embodiments, such as Figure 8 , Figure 9C ,and Figure 9E As shown, in operation S730, a plurality of second dummy lines 806 are formed in the first semiconductor wafer 801. For example, as Figure 8 As shown, multiple second dummy lines 806 extend along the Y direction. These multiple second dummy lines 806 may be distributed along the X direction.

[0170] In some embodiments, such as Figure 8 As shown, each of the plurality of second dummy lines 806 is positioned along the X direction between adjacent first metal lines 802.

[0171] In some embodiments, such as Figure 8 As shown, each of the plurality of second dummy lines 806 includes a plurality of second discrete dummy portions 807 (e.g., 807a). In some embodiments, each of the plurality of second discrete dummy portions 807 (e.g., 807a) of the second dummy line 806 is separated from the adjacent second discrete dummy portions of the second dummy line 806.

[0172] In some embodiments, a plurality of second discrete dummy portions 807 (e.g., 807a) are uniformly distributed in the Y direction. In some embodiments, the plurality of second discrete dummy portions 807 (e.g., 807a) have multiple sets of second dummy portion pitches along the Y direction.

[0173] In some embodiments, the plurality of first metal lines 802, the plurality of second metal lines 808, the plurality of first dummy lines 804, and the plurality of second dummy lines 806 are formed by forming trenches or vias in the first semiconductor wafer 801 according to a design pattern, and then filling the trenches or vias with a conductive material. Those skilled in the art will understand that other methods for forming the plurality of first metal lines 802, the plurality of second metal lines 808, the plurality of first dummy lines 804, and the plurality of second dummy lines 806 can also be applied to the first semiconductor wafer 801.

[0174] In some embodiments, the plurality of first metal lines 802, the plurality of second metal lines 808, the plurality of first dummy lines 804, and the plurality of second dummy lines 806 are made of the same conductive material.

[0175] In some embodiments, a plurality of first metal lines 802 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like. In some embodiments, a plurality of second metal lines 808 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like. In some embodiments, a plurality of first dummy lines 804 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like. In some embodiments, a plurality of second dummy lines 806 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like.

[0176] Reference Return Figure 7 In some embodiments, such as Figure 8 As shown, a second semiconductor wafer 811 is provided in operation S740. A portion of the second semiconductor wafer 811 is as follows: Figure 8 As shown, to clearly and better illustrate the features of this disclosure.

[0177] In some embodiments, the second semiconductor wafer 811 includes a second substrate (not shown) and a second dielectric layer (not shown) on the second substrate. The second substrate may be made of silicon, although it may also be formed of other group III, group IV, and / or group V elements, such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the second dielectric layer is made of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or the like.

[0178] In some embodiments, the second circuit is formed on the second substrate. The second circuit can be any type of circuit suitable for a particular application. For example, the second circuit includes various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and / or the like.

[0179] Reference Return Figure 7 In some embodiments, such as Figure 8 , Figure 9A , Figure 9B ,and Figure 9C As shown, in operation S750, a plurality of third metal lines 812 are formed in the second semiconductor wafer 811. For example, the plurality of third metal lines 812 extend along the Y direction. The plurality of third metal lines 812 are distributed in the X direction.

[0180] In some embodiments, such as Figure 9E As shown, each of the plurality of third metal lines 812 is positioned below a corresponding first metal line among the plurality of first metal lines 802. For example, each of the plurality of third metal lines 812 is aligned with a corresponding first metal line among the plurality of first metal lines 802 along the Z direction.

[0181] In some embodiments, such as Figure 8 and Figure 9A As shown, a plurality of third metal wires 812 are uniformly distributed in the X direction. In some other embodiments, the plurality of third metal wires 812 have multiple sets of different third wire pitches along the X direction.

[0182] In some embodiments, each of the plurality of third metal lines 812 includes a plurality of third discrete portions 813 (e.g., 813a). In some embodiments, each of the plurality of third discrete portions 813 (e.g., 813a) is separated from an adjacent third discrete portion 813. In some embodiments, as Figure 8 , Figure 9B ,and Figure 9C As shown, a plurality of third discrete portions 813 (e.g., 813a) and a plurality of first discrete portions 803 (e.g., 803a) alternate along a first direction.

[0183] In some embodiments, a plurality of third discrete portions 813 are spaced apart from each other and uniformly distributed in the Y direction. In some embodiments, the plurality of third discrete portions 813 (e.g., 813a) have multiple sets of third discrete portion pitches along the Y direction.

[0184] Alternatively, in some embodiments, during operation S750, a plurality of fourth metal lines 818 are formed in the second semiconductor wafer 811. For example, such as Figure 8 As shown, a plurality of fourth metal lines 818 extend along the X direction. The plurality of fourth metal lines 818 may be distributed in the Y direction. In some embodiments, as... Figure 8 As shown, each of the plurality of fourth metal lines 818 is positioned between adjacent third discrete portions 813. In some embodiments, the fourth metal line 818 is positioned between two adjacent third discrete portions 813.

[0185] In some embodiments, a plurality of fourth metal wires 818 are uniformly distributed in the Y direction. In some embodiments, the plurality of fourth metal wires 818 have multiple sets of different fourth wire pitches along the Y direction.

[0186] In some embodiments, such as Figure 8 and Figure 9AAs shown, each of the plurality of fourth metal lines 818 includes a plurality of fourth discrete portions 819 (e.g., 819a). In some embodiments, each of the plurality of fourth discrete portions 819 (e.g., 819a) is separated from the adjacent fourth discrete portion.

[0187] In some embodiments, a plurality of fourth discrete portions 819 (e.g., 819a) are uniformly distributed in the X direction. In some embodiments, the plurality of fourth discrete portions 819 (e.g., 819a) have multiple sets of fourth discrete portion pitches along the X direction.

[0188] Reference Return Figure 7 In some embodiments, such as Figure 8 , Figure 9A ,and Figure 9D As shown, in operation S760, a plurality of third dummy lines 814 are formed in the second semiconductor wafer 811. For example, as Figure 8 As shown, multiple third dummy lines 814 extend along the X direction. These multiple third dummy lines 814 may be distributed along the Y direction.

[0189] In some embodiments, such as Figure 8 As shown, a plurality of third dummy lines 814 are positioned along the Y direction between adjacent third discrete portions 813. In some embodiments, the third dummy lines are positioned between two adjacent third discrete portions 813.

[0190] In some embodiments, such as Figure 8 As shown, each of the plurality of third dummy lines 814 includes a plurality of third discrete dummy portions 815 (e.g., 815a). In some embodiments, each of the plurality of third discrete dummy portions 815 (e.g., 815a) of the third dummy line 814 is separated from the adjacent third discrete dummy portions of the third dummy line 814.

[0191] In some embodiments, a plurality of third discrete portions 813 (e.g., 813a) are uniformly distributed in the Y direction. In some embodiments, the plurality of third discrete portions 813 (e.g., 813a) have multiple sets of third discrete portion pitches along the Y direction.

[0192] Alternatively, or otherwise, in some embodiments, such as Figure 8 , Figure 9A ,and Figure 9C As shown, in operation S760, a plurality of fourth dummy lines 816 are formed in the second semiconductor wafer 811. For example, as Figure 8 As shown, multiple fourth dummy lines 816 extend along the Y direction. These multiple fourth dummy lines 816 may be distributed along the X direction.

[0193] In some embodiments, such as Figure 8 and Figure 9A As shown, each of the plurality of fourth dummy lines 816 is positioned along the X direction between adjacent third metal lines 812.

[0194] In some embodiments, each of the plurality of fourth dummy lines 816 includes a plurality of fourth discrete dummy portions 817 (e.g., 817a). In some embodiments, each of the plurality of fourth discrete dummy portions 817 (e.g., 817a) of the fourth dummy line 816 is separated from an adjacent fourth discrete dummy portion of the fourth dummy line 816.

[0195] In some embodiments, a plurality of fourth discrete dummy portions 817 (e.g., 817a) are uniformly distributed in the Y direction. In some embodiments, the plurality of fourth discrete dummy portions 817 (e.g., 817a) have multiple sets of fourth dummy portion pitches along the X direction.

[0196] In some embodiments, a plurality of third metal lines 812, a plurality of fourth metal lines 818, a plurality of third dummy lines 814, and a plurality of fourth dummy lines 816 are formed by forming trenches or vias in a second semiconductor wafer 811 according to a designed pattern, and then filling the trenches or vias with a conductive material. Those skilled in the art will understand that other methods for forming the plurality of third metal lines 812, the plurality of fourth metal lines 818, the plurality of third dummy lines 814, and the plurality of fourth dummy lines 816 can also be applied to the second semiconductor wafer 811.

[0197] In some embodiments, the plurality of third metal lines 812, the plurality of fourth metal lines 818, the plurality of third dummy lines 814, and the plurality of fourth dummy lines 816 are made of the same material.

[0198] In some embodiments, the plurality of third metal lines 812 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like. In some embodiments, the plurality of fourth metal lines 818 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like. In some embodiments, the plurality of third dummy lines 814 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like. In some embodiments, the plurality of fourth dummy lines 816 include copper, aluminum, gold, silver, silicon, combinations thereof, and / or the like.

[0199] Reference Return Figure 7 In some embodiments, such as Figure 8 , Figure 9B , Figure 9C ,and Figure 9E As shown, the mating connector 821 is formed in operation S770.

[0200] In some embodiments, the engagement connector 821 is configured to electrically connect a plurality of first discrete portions 803 via a plurality of third discrete portions 813. For example, a first discrete portion 803a is connected to a corresponding third discrete portion 813a via a first engagement connector 821a. Then, the corresponding third discrete portion 813a is connected to an adjacent first discrete portion 803b via a second engagement connector 821b. In some embodiments, the plurality of first discrete portions 803 of the first metal wires of a plurality of first metal wires 802 are electrically connected to each other.

[0201] Alternatively, in some embodiments, the third discrete portion 813a is connected to the second discrete portion 809a via a third engagement connector 821c.

[0202] In some embodiments, the coupling connector 821 connects at least one of a plurality of third discrete portions 813 and a plurality of fourth discrete portions 819 to at least one of a plurality of first discrete portions 803 and a plurality of second discrete portions 809.

[0203] In some embodiments, such as Figure 8 and Figure 9A As shown, in operation S750, a cross-shaped metal line 832 is formed in the second semiconductor wafer 811. In some embodiments, the cross-shaped metal line 832 is positioned between adjacent third metal lines 812. In some embodiments, the cross-shaped metal line 832 is positioned between adjacent fourth metal lines 818. In some embodiments, a second discrete portion 809a is connected to the cross-shaped metal line 832 via a bonding connector 821.

[0204] In some embodiments, the bonding of the bonding connector 821 to the first semiconductor wafer 801 and the second semiconductor wafer 811 is achieved through a wafer-on-wafer (WoW) bonding process. In the wafer-on-wafer bonding process, the first semiconductor wafer 801 is bonded to the second semiconductor wafer 811, and the bonding connector 821 is bonded to a plurality of first metal lines 802 and a plurality of third metal lines 812 via metal-to-metal direct bonding. For example, a first discrete portion 803a and a corresponding third discrete portion 813a are bonded to the first bonding connector 821a via metal-to-metal direct bonding. In some embodiments, an annealing process is performed after the wafer-on-wafer bonding process to further enhance the bonding between the first semiconductor wafer 801 and the second semiconductor wafer 811. Through the wafer-on-wafer bonding process, the bonding connector 821 can connect each of the plurality of first discrete portions 803 of the first metal line 802 to the plurality of third discrete portions 813 of the corresponding third metal line 812.

[0205] In some embodiments, the mating connector 821 is made of a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, combinations thereof, and / or the like.

[0206] Forming dummy lines between the spaced portions of metal lines can reduce unbalanced wafer warpage and relieve stress. Unbalanced wafer warpage and stress can be further reduced by adding another set of dummy lines between portions of metal lines extending in different directions. For example, for a 12-inch wafer with discrete metal lines having dummy lines inserted therebetween, the bow offset attributable to warpage in semiconductor devices 500 and 800 is less than 50 μm. Through the embodiments disclosed herein, the bow offset is reduced by approximately 17% in conventional devices. In other words, the embodiments disclosed herein provide an improvement of approximately 5.8 times in bow offset compared to conventional devices. In some embodiments, the density of discrete metal lines and dummy lines along the Y direction is substantially equal to the density of discrete metal lines and dummy lines along the X direction, such that metal stress is reduced in both directions.

[0207] This disclosure provides an improved metal wire-wound structure and its formation method, based on a novel ultra-thick metal (UTM) with a diced wire structure. Compared to prior art and configurations, the disclosed structure and method reduce wafer warpage and balance the bow value of wafer warpage in the X / Y directions by relieving stress. Embodiments of this disclosure provide an improved ultra-thick metal (UTM) wire-wound design with a diced wire structure for wafer-on-wafer (WoW) and / or other three-dimensional (3D) integrated circuit (IC) device structures, improving the warpage problem of WoW and / or 3D IC device structures attributed to metal stress. Therefore, the performance of wafer bonding and back-side silicon wafer processes used in manufacturing semiconductor devices can be improved.

[0208] This disclosure discloses a method of manufacturing a semiconductor device, including providing a first semiconductor substrate and forming a plurality of first metal lines extending along a first direction in the first semiconductor substrate. Each of the first metal lines includes a first discrete portion spaced apart along the first direction. The method further includes providing a second semiconductor substrate and a second metal line formed below each of the first metal lines and extending along the first direction in the second semiconductor substrate. The second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the second discrete portions and the first discrete portions alternate along the first direction. The method further includes forming a bonding connector that connects the second discrete portions to corresponding first metal lines among the first metal lines. In embodiments, the first metal lines and the second metal lines are distributed along a second direction, and the first direction is perpendicular to the second direction. In embodiments, the first metal lines are uniformly distributed in the second direction; and each second metal line is uniformly distributed in the second direction. In embodiments, the second metal lines are aligned with their counterparts in the first metal lines along a third direction, and the third direction is perpendicular to both the first and second directions. In embodiments, the first discrete portions are uniformly distributed along the first direction; and the second discrete portions are uniformly distributed along the first direction. In one embodiment, the method further includes forming a first dummy line in a first semiconductor substrate, the first dummy line extending along a second direction and positioned between adjacent first discrete portions of a first discrete portion. In another embodiment, the first dummy line includes a plurality of first discrete dummy portions uniformly distributed along the second direction. In yet another embodiment, the method further includes forming a second dummy line in a second semiconductor substrate, the second dummy line extending along the second direction and positioned between adjacent second discrete portions of a second discrete portion. In yet another embodiment, the second dummy line includes a plurality of second discrete dummy portions uniformly distributed along the second direction.

[0209] Another embodiment of this disclosure discloses a method for manufacturing a semiconductor device, including providing a first semiconductor substrate and forming a plurality of first metal lines extending along a first direction and a plurality of second metal lines extending along a second direction in the first semiconductor substrate. Each of the first metal lines includes a plurality of first discrete portions spaced apart along the first direction, and each of the second metal lines includes a plurality of second discrete portions spaced apart along the second direction. The method further includes forming a first dummy line extending along the second direction and positioned between adjacent first discrete portions of the first discrete portions in the first semiconductor substrate, and forming a second dummy line extending along the first direction and positioned between adjacent second discrete portions of the second discrete portions in the first semiconductor substrate. In an embodiment, the first dummy line includes a plurality of first discrete dummy portions uniformly distributed along the first direction. In an embodiment, the second dummy line includes a plurality of second discrete dummy portions uniformly distributed along the second direction. In an embodiment, the method further includes providing a second semiconductor substrate and forming a plurality of third metal lines extending along the first direction and a plurality of fourth metal lines extending along the second direction in the second semiconductor substrate. Each of the third metal lines includes a plurality of third discrete portions spaced apart along a first direction, and each of the fourth metal lines includes a plurality of fourth discrete portions spaced apart along a second direction. The method further includes forming a bonding connector connecting at least one of the third and fourth discrete portions to at least one of the first and second discrete portions. In an embodiment, the method further includes forming a third dummy line extending along the second direction and positioned between adjacent third discrete portions of the third discrete portions in a second semiconductor substrate, and forming a fourth dummy line extending along the first direction and positioned between adjacent fourth discrete portions of the fourth discrete portions in the second semiconductor substrate. In an embodiment, the method further includes forming a cross-shaped metal line in the second semiconductor substrate, the cross-shaped metal line being positioned between adjacent third discrete portions of the third discrete portions and between adjacent fourth discrete portions of the fourth discrete portions. In an embodiment, the first direction is perpendicular to the second direction.

[0210] Another embodiment of this disclosure is a semiconductor device including a first semiconductor substrate and a plurality of first metal lines extending in the first semiconductor substrate along a first direction. Each of the first metal lines includes a plurality of first discrete portions spaced apart along the first direction. The semiconductor device further includes a second semiconductor substrate and a second metal line below each of the first metal lines and extending in the second semiconductor substrate along the first direction. The second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the second discrete portions and the first discrete portions alternate along the first direction. The semiconductor device further includes a bonding connector that connects the second discrete portions to corresponding portions of the first metal lines. In an embodiment, the first metal lines and the second metal lines are distributed along a second direction, and the first direction is perpendicular to the second direction. In an embodiment, the first metal lines are uniformly distributed in the second direction, and the second metal lines are uniformly distributed in the second direction. In an embodiment, the first discrete portions are uniformly distributed along the first direction, and the second discrete portions are uniformly distributed along the first direction.

[0211] Another embodiment of this disclosure is a semiconductor device including a first semiconductor substrate, a plurality of first metal lines extending along a first direction in the first semiconductor substrate, and a first dummy line extending along a second direction in the first semiconductor substrate. Each of the first metal lines includes a plurality of first discrete portions spaced apart along the first direction, and the first dummy line is positioned between a plurality of adjacent first discrete portions. The semiconductor device further includes a second semiconductor substrate and a second metal line below each of the first metal lines and extending along the first direction in the second semiconductor substrate. The second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the second discrete portions and the first discrete portions alternate along the first direction. The semiconductor device further includes a bonding connector that connects the second discrete portions to corresponding portions in the first metal lines. In an embodiment, the first dummy line includes a plurality of first discrete dummy portions uniformly distributed along the second direction. In an embodiment, the first metal lines are uniformly distributed in the second direction.

[0212] Another embodiment of this disclosure is a semiconductor device including a first semiconductor substrate and a plurality of first metal lines extending along a first direction in the first semiconductor substrate. Each of the first metal lines includes a plurality of first discrete portions spaced apart along the first direction. The semiconductor device further includes a second semiconductor substrate, a second metal line extending along the first direction below each of the first metal lines in the second semiconductor substrate, and a second dummy line extending along a second direction in the second semiconductor substrate. The second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the second discrete portions and the first discrete portions alternately intersect along the first direction. The second dummy line is positioned between a plurality of adjacent second discrete portions of the second discrete portions. The semiconductor device further includes a bonding connector that connects the second discrete portions to corresponding portions in the first metal lines. In an embodiment, the second dummy line includes a plurality of second discrete dummy portions uniformly distributed along the second direction.

[0213] Another embodiment of this disclosure is a method of manufacturing a semiconductor device, including providing a first semiconductor substrate and forming a plurality of first metal lines extending along a first direction and a plurality of second metal lines extending along a second direction in the first semiconductor substrate. Each of the plurality of first metal lines includes a plurality of first discrete portions spaced apart along the first direction, and each of the plurality of second metal lines includes a plurality of second discrete portions spaced apart along the second direction. The method further includes providing a second semiconductor substrate and forming a plurality of third metal lines extending along the first direction and a plurality of fourth metal lines extending along the second direction in the second semiconductor substrate. Each of the plurality of third metal lines includes a plurality of third discrete portions spaced apart along the first direction, and each of the plurality of fourth metal lines includes a plurality of fourth discrete portions spaced apart along the second direction. The method further includes forming a bonding connector to connect at least one of the plurality of third discrete portions and the plurality of fourth discrete portions to at least one of the plurality of first discrete portions and the plurality of second discrete portions.

[0214] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A first semiconductor substrate; In the first semiconductor substrate, a plurality of first metal lines extend along a first direction, each of the plurality of first metal lines comprising a plurality of first discrete portions spaced apart along the first direction. A second semiconductor substrate; Below each of the plurality of first metal lines and extending along the first direction in the second semiconductor substrate, wherein the second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the plurality of second discrete portions alternately intersect the plurality of first discrete portions along the first direction; and The plurality of second discrete portions are connected to a corresponding engagement connector of the plurality of first metal wires.

2. The semiconductor device as claimed in claim 1, characterized in that, in: The plurality of first metal wires and the second metal wire are distributed along a second direction, and The first direction is perpendicular to the second direction.

3. The semiconductor device as claimed in claim 1, characterized in that, in: The plurality of first metal wires are uniformly distributed in a second direction.

4. The semiconductor device as claimed in claim 1, characterized in that, in: The plurality of first discrete portions are uniformly distributed along the first direction, and The plurality of second discrete portions are uniformly distributed along the first direction.

5. A semiconductor device, characterized in that, Include: A first semiconductor substrate; In the first semiconductor substrate, a plurality of first metal lines extend along a first direction, each of the plurality of first metal lines comprising a plurality of first discrete portions spaced apart along the first direction. A first dummy line extends along a second direction and is positioned between a plurality of adjacent first discrete portions in the first semiconductor substrate. A second semiconductor substrate; Below each of the plurality of first metal lines and extending along the first direction in the second semiconductor substrate, wherein the second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the plurality of second discrete portions alternately intersect the plurality of first discrete portions along the first direction; and The plurality of second discrete portions are connected to a corresponding engagement connector of the plurality of first metal wires.

6. The semiconductor device as claimed in claim 5, characterized in that, in: The first dummy line includes a plurality of first discrete dummy parts that are uniformly distributed along the second direction.

7. The semiconductor device as claimed in claim 5, characterized in that, in: The plurality of first metal wires are evenly distributed in the second direction.

8. The semiconductor device as claimed in claim 5, characterized in that, in: The plurality of first discrete portions are uniformly distributed along the first direction, and The plurality of second discrete portions are uniformly distributed along the first direction.

9. A semiconductor device, characterized in that, Include: A first semiconductor substrate; In the first semiconductor substrate, a plurality of first metal lines extend along a first direction, each of the plurality of first metal lines comprising a plurality of first discrete portions spaced apart along the first direction. A second semiconductor substrate; A second metal line extending along the first direction below each of the plurality of first metal lines in the second semiconductor substrate, wherein the second metal line includes a plurality of second discrete portions spaced apart along the first direction, and the plurality of second discrete portions and the plurality of first discrete portions alternately intersect along the first direction; A second dummy line, in the second semiconductor substrate, the second dummy line extends along a second direction and is positioned between a plurality of adjacent second discrete portions; and The plurality of second discrete portions are connected to a corresponding engagement connector of the plurality of first metal wires.

10. The semiconductor device as claimed in claim 9, characterized in that, in: The second dummy line includes a plurality of second discrete dummy parts that are uniformly distributed along the second direction.

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