Semiconductor test structure and wafer
By designing a semiconductor test structure for breakdown voltage testing, the problem of insufficient breakdown characteristic evaluation between via structures and metal interconnects is solved. This enables comprehensive evaluation and reliability modeling of dielectric materials, providing data support for process optimization and improving chip reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2025-07-04
- Publication Date
- 2026-06-16
AI Technical Summary
Existing technologies lack specific test structures for the breakdown characteristics between via structures and metal interconnects, resulting in insufficient process window verification and an inability to effectively assess the critical breakdown parameters of dielectric materials under mass production conditions, which affects the long-term reliability and yield control of chips.
A semiconductor test structure is designed, including a substrate, first and second metal line structures, via structures, and metal pads. By setting different spacing and voltage gradients, breakdown voltage tests are performed to simulate the three-dimensional interconnection scenario of an actual chip and evaluate the ultimate performance of dielectric materials.
By quantifying the impact of process deviations on breakdown voltage, this study reveals the risk of dielectric breakdown, provides data for design rule optimization and process window verification, improves the engineering applicability of test results, identifies abnormal breakdown issues, and ensures chip reliability.
Smart Images
Figure CN224368298U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductors, and in particular to a semiconductor testing structure and wafer. Background Technology
[0002] As process nodes continue to shrink, the spacing between metal interconnects and between via structures and metal interconnects is constantly decreasing. The resulting inter-line leakage current and dielectric breakdown issues have become core challenges restricting chip reliability. Process deviations in spacing can significantly alter the distribution characteristics of breakdown voltage (VBD), while design flaws in the spacing between via structures and adjacent metal interconnects can directly lead to early breakdown failure of the dielectric layer.
[0003] The current product design lacks a dedicated test structure for the breakdown characteristics between via structures and metal interconnects, resulting in insufficient process window verification and an inability to effectively assess the critical breakdown parameters of dielectric materials under mass production conditions. This poses a significant risk to the long-term reliability and yield control of the chip. Therefore, there are areas for improvement. Utility Model Content
[0004] The purpose of this invention is to provide a semiconductor test structure and wafer capable of testing breakdown voltage.
[0005] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:
[0006] This utility model provides a semiconductor testing structure, including:
[0007] Substrate;
[0008] At least one first metal line structure is formed on the substrate;
[0009] At least one via structure, each via structure being formed within a corresponding first metal wire structure;
[0010] At least one second metal line structure is formed on the substrate, the second metal line structure being located on one side of a corresponding first metal line structure;
[0011] A first metal pad is formed on the substrate, coupled to a high-level voltage, and electrically connected to the first metal wire structure;
[0012] A second metal pad is formed on the substrate, coupled to a low-level voltage or ground, and electrically connected to the second metal wire structure.
[0013] In one embodiment of the present invention, at least one third metal line structure is further included, the third metal line structure being formed on the substrate, and each of the first metal line structures is located on the corresponding third metal line structure.
[0014] In one embodiment of this utility model, the first metal wire structure is a straight metal wire, and multiple first metal wire structures are arranged at intervals.
[0015] In one embodiment of the present invention, the second metal wire structure is a straight metal wire, and each second metal wire structure is located between two adjacent first metal wire structures.
[0016] In one embodiment of the present invention, a plurality of spacings are formed between each of the first metal wire structures and its adjacent second metal wire structures, and the plurality of spacings are of the same size.
[0017] In one embodiment of this utility model, the width of the first metal wire structure is smaller than the spacing, and the width of the second metal wire structure is smaller than the spacing.
[0018] In one embodiment of this utility model, the aperture of the via structure increases from bottom to top, and all the via structures are located on the same horizontal plane.
[0019] In one embodiment of this utility model, the via structure and the second metal wire structure are located on different horizontal planes.
[0020] The present invention also provides a wafer comprising the aforementioned semiconductor test structure, wherein the number of the semiconductor test structures is at least one, and the semiconductor test structure is formed within a dicing channel.
[0021] In one embodiment of this invention, the spacing between the first metal line structure and its adjacent second metal line structure in the semiconductor test junction located at different positions is different.
[0022] As described above, this invention provides a semiconductor test structure and wafer. By setting tests with different spacings, it can quantify the impact of process deviations on breakdown voltage, reveal the dielectric breakdown risk caused by reduced spacing, provide data support for design rule optimization and process window verification, and avoid early failures caused by process fluctuations or design defects. The non-coplanar layout of the via structure and the second metal line structure simulates the three-dimensional interconnection scenario of an actual chip, which can realistically reflect the breakdown characteristics under complex electric field distributions, help discover abnormal breakdown problems caused by unreasonable structural design or process anomalies, and improve the engineering applicability of test results. By adopting a progressive voltage application strategy, the critical breakdown voltage value at different positions and spacings can be accurately measured, comprehensively evaluating the limiting performance of dielectric materials under mass production conditions, making up for the deficiency of insufficient critical parameter evaluation in traditional tests, and providing a basis for reliability modeling and material selection.
[0023] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a top view of a semiconductor testing structure in one embodiment of the present invention;
[0026] Figure 2 This is a cross-sectional view of a semiconductor testing structure in one embodiment of the present invention;
[0027] Figure 3 This is a top view of a semiconductor test structure at another location in one embodiment of the present invention.
[0028] In the figure: 10, substrate; 20, first metal line structure; 30, second metal line structure; 40, via structure; 50, third metal line structure; 60, first metal pad; 70, second metal pad. Detailed Implementation
[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0030] Please see Figure 1 and Figure 2 This utility model discloses a semiconductor test structure capable of performing specialized tests on the breakdown characteristics between via structures and metal interconnects. The semiconductor test structure may include a substrate 10, a first metal line structure 20, a second metal line structure 30, a via structure 40, a third metal line structure 50, a first metal pad 60, and a second metal pad 70.
[0031] Please see Figure 1 and Figure 2In some embodiments, substrate 10 refers to the base carrier of the semiconductor device and may be made of silicon or other semiconductor materials. Substrate 10 provides a supportive and electrically isolated environment for subsequent metal line structures. Trench structures formed in substrate 10 by an etching process are used to accommodate a third metal line structure 50. The third metal line structure 50 may be designed in a straight line shape. The third metal line structure 50 can serve a supporting function. The material of the third metal line structure 50 may be copper.
[0032] Please see Figure 1 and Figure 2 In some embodiments, at least one first trench structure and at least one second trench structure may be etched on the substrate 10. The first trench structure may be located above the third metal line structure 50 to form the first metal line structure 20. The second trench structure may be located between two adjacent first trench structures to form the second metal line structure 30. Via structures 40 may be used to connect metal lines of different layers, with each via structure 40 formed within a corresponding first metal line structure 20. At least one via structure 40 is present, and its function is to provide electrical connection between the first metal line structure 20 and other layers of metal lines (such as the third metal line structure 50).
[0033] Please see Figure 2 In some embodiments, the aperture of the via structure 40 is tapered or stepped in the vertical direction, with a smaller bottom aperture and a larger top aperture, due to process limitations (such as the tapered effect of the etching process).
[0034] Please see Figure 2 In some embodiments, the bottom or top of all via structures 40 are aligned at the same horizontal level. This ensures that all via structures 40 have the same electrical and physical conditions during testing, facilitating comparison and analysis of test results. The via structures 40 and the second metal line structure 30 are located at different levels (i.e., different metal layers) in the vertical direction. This is for achieving multilayer metal interconnects or for testing the electrical characteristics (such as breakdown voltage) between different metal layers. By placing the via structures 40 and the second metal line structure 30 on different horizontal planes, the layout of multilayer metal interconnects in an actual chip can be simulated, allowing for testing of its reliability and performance.
[0035] Please see Figure 1 and Figure 2In some embodiments, the first metal wire structure 20 can be a straight metal wire. Multiple first metal wire structures 20 can be arranged at intervals, maintaining a certain distance from each other. The second metal wire structure 30 can also be a straight metal wire. Each second metal wire structure 30 can be located between two adjacent first metal wire structures 20, forming an alternating arrangement. The material of the first metal wire structure 20 can be copper. The material of the second metal wire structure 30 can also be copper.
[0036] Please see Figure 1 and Figure 2 In some embodiments, each first metal wire structure 20 forms multiple spacings with its adjacent second metal wire structure 30, and these spacings are of the same size. The width of the first metal wire structure 20 is smaller than the spacing. The width of the second metal wire structure 30 is also smaller than the spacing. This design can simulate the interaction between the via structure 40 and the second metal wire structure 30 at different spacings, such as breakdown characteristics. The fact that the widths of the first metal wire structure 20 and the second metal wire structure 30 are smaller than the spacing ensures that the test results primarily reflect the effect of the spacing on the breakdown voltage, rather than the effect of the width of the non-metal wire structure.
[0037] Please see Figure 2 In some embodiments, the specific width of the first metal line structure 20 is not limited. The width of the first metal line structure 20 can be in the range of 40nm to 60nm. For example, the width of the first metal line structure 20 can be 40nm, 50nm, 60nm, etc.
[0038] Please see Figure 2 In some embodiments, the specific width of the second metal line structure 30 is not limited. The width of the second metal line structure 30 can be in the range of 40nm to 60nm. For example, the width of the second metal line structure 30 can be 40nm, 50nm, 60nm, etc. The width of the first metal line structure 20 and the width of the second metal line structure 30 may be different.
[0039] Please see Figure 2 In some embodiments, the specific size of the via structure 40 is not limited. The size of the via structure 40 can be in the range of 40nm to 60nm. For example, the size of the via structure 40 can be 40nm, 50nm, 60nm, etc.
[0040] Please see Figure 1In some embodiments, a first metal pad 60 (high pin) may be formed on the substrate 10. The first metal pad 60 may be coupled to a high-level voltage (e.g., power supply voltage VDD). The first metal pad 60 may be electrically connected to the first metal wire structure 20 to provide a high-level voltage to the first metal wire structure 20 for testing breakdown voltage. Breakdown voltage refers to the voltage at which the dielectric between the via structure 40 and the second metal wire structure 30 breaks down under the influence of an electric field. Breakdown voltage can be used to evaluate the dielectric insulation performance and reliability. By measuring the breakdown voltage, it can be determined whether the dielectric between the via structure 40 and the second metal wire structure 30 meets design requirements and whether there are potential reliability issues.
[0041] Please see Figure 1 In some embodiments, a second metal pad 70 (low pin) may be formed on the substrate 10. The second metal pad 70 may be coupled to a low-level voltage or ground (e.g., ground voltage VSS). The second metal pad 70 may be electrically connected to the second metal line structure 30 for testing breakdown voltage. The first metal pad 60 and the second metal pad 70 provide high-level and low-level voltages, respectively, forming the voltage gradient required for testing. The first metal line structure 20 and the second metal line structure 30 are connected to different voltage sources via corresponding metal pads to simulate the operating conditions of metal interconnects in an actual chip.
[0042] Please see Figure 1 and Figure 2 In some embodiments, the breakdown voltage between the via structure 40 in the first metal wire structure 20 and its adjacent second metal wire structure 30 is tested by applying a test voltage to the first metal wire structure 20. When a voltage is applied to the first metal wire structure 20, an electric field is formed between the via structure 40 and the adjacent second metal wire structure 30. As the voltage increases, the electric field strength gradually increases until it reaches the breakdown voltage, causing the dielectric to break down. By measuring the breakdown voltage, the insulation performance between the via structure 40 and its adjacent second metal wire structure 30, as well as the reliability of the dielectric, can be evaluated.
[0043] In some embodiments, the test voltage applied to the first metal wire structure 20 can be between 1V and 100V. By covering the range from low to high voltage, the electrical characteristics between the via structure 40 and the second metal wire structure 30 can be comprehensively evaluated. During testing, the applied test voltage can start from 1V and increase by 1V after each test until it reaches 100V. Since the spacing affects the electric field distribution and the magnitude of the breakdown voltage, by conducting tests under different spacing conditions, the influence of spacing on the breakdown voltage can be studied, providing data support for process optimization and design rules. This method of gradually increasing the voltage can systematically test the changes in breakdown voltage. By gradually increasing the voltage, the critical value of the breakdown voltage can be accurately found, avoiding missing key data due to excessive voltage jumps.
[0044] This invention also discloses a wafer, which, in addition to the actual chip circuitry, may also include semiconductor test structures specifically designed for testing. These semiconductor test structures allow for monitoring of process quality during wafer manufacturing and provide data support for design optimization. The wafer may have at least one semiconductor test structure. Multiple semiconductor test structures can cover different areas of the wafer, improving the representativeness and reliability of the test data. Through multiple semiconductor test structures, the process uniformity and electrical characteristics of the wafer at different locations can be comprehensively evaluated.
[0045] In some embodiments, semiconductor test structures can be located within scribe lines on a wafer, i.e., the blank areas between chips. A scribe line refers to the area on a wafer used to divide chips; it typically does not contain actual circuitry and is therefore suitable for placing test structures. Placing the test structure within the scribe line avoids occupying chip area and facilitates testing before wafer dicing.
[0046] Please see Figure 1 and Figure 3 In some embodiments, multiple semiconductor test structures can be formed on the dicing channels within a wafer. Within the same semiconductor test structure, the spacing between adjacent first metal line structures 20 and second metal line structures 30 must be identical. For semiconductor test structures at different locations, the spacing between adjacent first metal line structures 20 and second metal line structures 30 can be different. For example, for a semiconductor test structure at a certain location, the spacing between the first metal line structure 20 and its adjacent second metal line structure 30 can be 110 nm. As another example, for semiconductor test structures at other locations, the spacing between the first metal line structure 20 and its adjacent second metal line structure 30 can be 114 nm.
[0047] Please see Figure 1 and Figure 3 In some embodiments, the spacing between the first metal line structure 20 and its adjacent second metal line structure 30 can be in the range of 110nm to 160nm. By setting a reasonable range, common metal line spacing conditions in actual chips can be covered, ensuring the practicality and representativeness of the test results. The spacing can be gradually increased according to a certain gradient, for example, by 4nm or 7nm each time. By setting different gradient spacings, a series of test data can be generated for analyzing the quantitative relationship between spacing and electrical characteristics (such as the relationship between spacing and breakdown voltage).
[0048] In some embodiments, by performing breakdown voltage tests on semiconductor test structures in different dicing paths, breakdown voltage data at different locations and spacings on the wafer can be obtained. Through testing, the wafer's process uniformity can be evaluated, the presence of local defects or process deviations can be determined, and data support can be provided for design optimization.
[0049] As can be seen, the unexpected effect of this invention in the above scheme is that by setting tests with different spacings, the impact of process deviations on breakdown voltage can be quantified, revealing the dielectric breakdown risk caused by reduced spacing, providing data support for design rule optimization and process window verification, and avoiding early failures caused by process fluctuations or design defects. The non-coplanar layout of the via structure and the second metal line structure simulates the three-dimensional interconnection scenario of the actual chip, which can realistically reflect the breakdown characteristics under complex electric field distribution, help to discover abnormal breakdown problems caused by unreasonable structural design or process abnormalities, and improve the engineering applicability of test results. By adopting a progressive voltage application strategy, the critical breakdown voltage value at different positions and spacings can be accurately measured, comprehensively evaluating the limiting performance of dielectric materials under mass production conditions, making up for the deficiency of insufficient critical parameter evaluation in traditional tests, and providing a basis for reliability modeling and material selection.
[0050] The embodiments of this utility model disclosed above are merely illustrative of the present utility model. The embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Obviously, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.
Claims
1. A semiconductor testing structure, characterized in that, include: Substrate; At least one first metal line structure is formed on the substrate; At least one via structure, each via structure being formed within a corresponding first metal wire structure; At least one second metal line structure is formed on the substrate, the second metal line structure being located on one side of a corresponding first metal line structure; A first metal pad is formed on the substrate, coupled to a high-level voltage, and electrically connected to the first metal wire structure; A second metal pad is formed on the substrate, coupled to a low-level voltage or ground, and electrically connected to the second metal wire structure.
2. The semiconductor test structure according to claim 1, characterized in that, It also includes at least one third metal line structure formed on the substrate, and each of the first metal line structures is located on the corresponding third metal line structure.
3. The semiconductor test structure according to claim 1, characterized in that, The first metal wire structure is a straight metal wire, and multiple first metal wire structures are arranged at intervals.
4. The semiconductor test structure according to claim 3, characterized in that, The second metal wire structure is a straight metal wire, and each second metal wire structure is located between two adjacent first metal wire structures.
5. The semiconductor test structure according to claim 4, characterized in that, Each of the first metal wire structures forms multiple spacings with its adjacent second metal wire structure, and the multiple spacings are of the same size.
6. The semiconductor test structure according to claim 5, characterized in that, The width of the first metal wire structure is smaller than the spacing, and the width of the second metal wire structure is smaller than the spacing.
7. The semiconductor test structure according to claim 1, characterized in that, The aperture of the via structure increases from bottom to top; all the via structures are located on the same horizontal plane.
8. The semiconductor test structure according to claim 7, characterized in that, The via structure and the second metal wire structure are located on different horizontal planes.
9. A wafer, characterized in that, The semiconductor test structure includes any one of claims 1 to 8, wherein the number of semiconductor test structures is at least one, and the semiconductor test structure is formed within a dicing channel.
10. The wafer according to claim 9, characterized in that, The spacing between the first metal line structure and its adjacent second metal line structure in the semiconductor test junction located at different positions is different.