An extensible multi-ADC interleaved sampling circuit
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN XUANJING TECH CO LTD
- Filing Date
- 2025-08-20
- Publication Date
- 2026-06-19
Smart Images
Figure CN224385501U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of data acquisition in electronic information technology, and more specifically, to a scalable multi-ADC interleaved sampling circuit. Background Technology
[0002] To overcome the performance bottleneck of a single ADC, the industry commonly employs time-interleaved sampling technology. Its core idea is to use M ADCs in parallel, allocating a sampling clock with a phase difference of 360 / M degrees to each ADC. These M ADCs take turns sampling the input signal, and finally, their sampled data are combined, thereby achieving an overall sampling rate increase of M times compared to a single ADC. For example... Figure 1 The diagram shown is a schematic of the basic principle of dual-channel interleaved sampling. By using two clocks with phases offset by 180 degrees (sampling clock 1 and sampling clock 2) to drive the two sampling channels respectively, the system's equivalent sampling rate is doubled.
[0003] In terms of specific circuit implementation, existing technologies mainly offer the following solutions:
[0004] Option 1: Simple internal interleaving of dual-channel ADC
[0005] like Figure 2 As shown, this is a basic interleaved sampling structure. It is typically integrated within a single ADC chip, containing an ADC core and two parallel input channels (channel A and channel B). This is achieved through three analog switches (…). Figure 2 The combined control of S1, S2, and S3 shown can achieve different operating modes. For example, when S1 is closed, S2 is open, and S3 is closed, the A and B channels of the ADC acquire analog input signal 1 in parallel; when S1 and S3 are closed and S2 is open, the A and B channels acquire analog input signal 2 in parallel. In this parallel mode, if the A and B channels use clocks with a 180-degree phase difference for sampling, the sampling rate of a single input signal can be doubled. As shown in the table, if the sampling rate of a single ADC channel is 100MHz, it can be doubled to 200MHz.
[0006] The drawbacks of this solution are extremely obvious: its scalability is essentially zero. Its structure is fixed inside the chip, limited to the interleaving of two channels, and cannot be further improved by adding an external ADC to increase the sampling rate or support more input signals, falling far short of meeting the needs of applications requiring higher sampling rates or more channels.
[0007] Option 2: On-chip integrated switch matrix solution
[0008] To achieve higher interleaving ratios and more input channels, a more complex approach is to integrate a large-scale switching matrix within a single ASIC chip, such as... Figure 3 As shown, this matrix connects multiple external analog inputs to the channels of multiple internal ADC modules. By controlling the on / off states of the switches within the matrix, any one or more input signals can be flexibly routed to one or more ADC channels for sampling.
[0009] Although this solution is more powerful than the first solution in terms of functionality, it has exposed many serious problems that are difficult to overcome in practical applications:
[0010] Poor scalability and flexibility: The switch matrix and ADC core are integrated on the same chip, meaning the number of ADCs, channels, and interconnect topology are permanently fixed once the chip is fabricated. When the system needs to be upgraded, such as expanding from 4 channels to 8 channels, or requiring a higher total sampling rate, the only way is to redesign, fabricate, and verify the chip—an extremely costly and time-consuming process. The system lacks modular upgrade capabilities and has extremely poor flexibility.
[0011] Serious signal integrity issues: In high-frequency analog signal paths, any non-ideal factors are amplified. The on-chip switch matrix wiring is extremely complex, with numerous signal lines of varying lengths crisscrossing, leading to severe signal integrity problems.
[0012] Parasitic effects: Complex metal interconnects can introduce significant parasitic capacitance and inductance, creating unnecessary filtering effects at high frequencies and affecting the frequency response of the signal.
[0013] Crosstalk occurs when a high-frequency signal on one signal line couples to an adjacent signal line through a capacitor or inductor. In a dense switching matrix, the signal from one channel can "leak" to other channels, severely reducing the isolation between channels and degrading signal quality.
[0014] Clock feedthrough: The high-speed clock signal that controls the on / off state of the switch will have its edges coupled to the analog signal path through the parasitic capacitance of the switch, superimposing unnecessary noise spikes on the analog signal and reducing the signal-to-noise ratio (SNR).
[0015] Channel mismatch is a significant issue: this is one of the most critical problems in time-interleaved ADC systems. Due to the asymmetric physical structure of the switching matrix, the physical path lengths from different analog inputs to different ADC channels are almost impossible to be perfectly equal. This difference in path length leads to three key mismatches between channels:
[0016] Gain mismatch: Different paths have different resistances and parasitic loads, which causes the signal amplitude to differ when it reaches different ADC channels.
[0017] Bias mismatch: There is a difference in the DC bias voltage of each switch and ADC channel.
[0018] Time mismatch: Different path lengths mean different signal propagation delays. In time-interleaved systems, this tiny nanosecond or even picosecond delay difference (i.e., time offset) can cause the sampling time to deviate from the ideal equal-interval time point, resulting in severe interleaving artifacts at the digital output and significantly reducing the spurious-free dynamic range of the system.
[0019] In summary, existing technologies face a series of pressing technical challenges in achieving scalable, high-performance multi-ADC interleaved sampling, including poor scalability, low flexibility, difficulty in guaranteeing signal integrity, severe channel mismatch, and high development costs. Utility Model Content
[0020] To address the shortcomings of the aforementioned background technologies, a high-performance multi-ADC interleaved sampling solution is provided, which features a simpler structure, more flexible design, and lower cost.
[0021] To achieve the above objectives, this utility model provides a scalable multi-ADC interleaved sampling circuit, which includes:
[0022] At least two analog-to-digital converter modules;
[0023] Multiple analog input terminals;
[0024] And a switching circuit consisting of multiple switches;
[0025] Each of the at least two analog-to-digital converter modules includes at least one analog input channel;
[0026] The switching circuit includes multiple interconnecting switches, which are disposed between the analog input channels of the analog-to-digital converter module to connect the analog input channels to form a ring topology.
[0027] The switching circuit also includes multiple input switches, and each of the analog input terminals is connected to a node on the ring topology through its corresponding input switch.
[0028] In a preferred embodiment, the analog-to-digital converter module includes a first analog-to-digital converter module and a second analog-to-digital converter module; the first analog-to-digital converter module has a first A channel and a first B channel; the second analog-to-digital converter module has a second A channel and a second B channel.
[0029] In a preferred embodiment, the interconnecting switch includes: a first channel interconnecting switch connected between the first A channel and the first B channel; a second channel interconnecting switch connected between the second A channel and the second B channel; and a bridging interconnecting switch connected between the first B channel and the second A channel.
[0030] In a preferred embodiment, the interconnecting switch further includes a loop-closing switch connected between the second B channel and the first A channel.
[0031] In a preferred embodiment, each of the analog input terminals is connected to a unique analog-to-digital converter module's analog input channel via its corresponding input switch.
[0032] In a preferred embodiment, the ring topology is configured such that the analog input channel of the newly added analog-to-digital converter module can be connected in series to the original ring topology by adding an analog-to-digital converter module and a corresponding interconnecting switch.
[0033] In a preferred embodiment, the signal transmission path lengths of the interconnecting switch and the input switch from either of the analog input terminals to either of the analog input channels are the same.
[0034] In a preferred embodiment, the switching circuit is configured to apply the analog input signal to all analog input channels simultaneously by closing the input switch corresponding to a selected analog input terminal and simultaneously closing all interconnecting switches.
[0035] In a preferred embodiment, a controller is further included; the controller is connected to the control terminals of the input switch and the interconnecting switch respectively, and is used to output control signals according to a preset sampling mode to independently control the closed or open state of each switch.
[0036] In a preferred embodiment, the switch in the switching circuit is a discrete analog switch, a MOSFET, or a relay. Beneficial effects
[0037] Compared with the prior art, the technical solution provided by this utility model has the following significant advantages:
[0038] 1. Scalability: This invention adopts a modular design concept, treating the ADC module and switching circuit as independent units. The core of the system is a ring topology composed of interconnected switches. When it is necessary to add ADC channels to improve the sampling rate or support more inputs, simply "insert" the new ADC module and corresponding interconnected switches into the ring structure, like adding a link to a chain, without requiring fundamental modifications to the existing circuitry. This "plug-and-play" scalability completely solves the fundamental problem of poor scalability in existing on-chip integrated solutions.
[0039] 2. Symmetry: The ring topology has a natural advantage in physical layout due to its symmetry. During PCB design, the ring can be easily laid out in a geometrically symmetrical shape, allowing for precise control of the signal trace length from any input node to any ADC channel, ensuring high consistency. This physically eliminates time offset, gain mismatch, and bias mismatch caused by path length differences, significantly improving the performance of interleaved sampling, especially spurious-free dynamic range.
[0040] 3. High configuration flexibility and resource utilization: By independently programming and controlling all input switches and interconnect switches through an external controller, this circuit can dynamically implement multiple operating modes, optimally allocating limited ADC resources. For example, all ADC channel resources can be concentrated on a single high-bandwidth signal to achieve the highest system sampling rate; alternatively, ADC channels can be grouped to simultaneously sample multiple different signals at a moderate rate in parallel. This flexibility allows the circuit to adapt to a variety of complex and changing application scenarios. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 This is a schematic diagram illustrating the basic principle of time-interleaved sampling in existing technologies.
[0043] Figure 2 This is a schematic diagram of the internal interleaving circuit of a simple dual-channel ADC in the prior art.
[0044] Figure 3 This is a schematic diagram of an interleaved sampling circuit based on an on-chip integrated switch matrix in the prior art.
[0045] Figure 4 This is a schematic diagram illustrating the basic concept of the ring topology proposed in this utility model.
[0046] Figure 5 This is a schematic diagram of the scalability of the ring topology in this utility model, showing the series structure from ADC1 to ADCn.
[0047] Figure 6 This is a circuit diagram of a specific embodiment of the present invention, showing a configuration of 4 inputs and 2 dual-channel ADCs.
[0048] Figure 7 Is with Figure 6 A table showing examples of sampling modes and sampling rates that can be achieved under different switch combinations for the circuit.
[0049] Figure 8 This is a wiring connection diagram in an embodiment of the present invention to ensure channel symmetry.
[0050] Figure 9 Yes Figure 6 Another, clearer illustration of the circuit structure highlights the connection between the input switches and the interconnecting switches.
[0051] Explanation of reference numerals in the attached figures:
[0052] ADC1: First Analog-to-Digital Converter Module
[0053] ADC2: Second Analog-to-Digital Converter Module
[0054] Channel A 1, Channel A 2, Channel B 1, Channel B 2: Analog input channels
[0055] Analog Input 1, Analog Input 2, Analog Input 3, Analog Input 4: Analog Input Terminals
[0056] S1, S2, S3, S4: Input switches
[0057] S5 - First channel interconnection switch, S6 - Jumper interconnection switch, S7 - Second channel interconnection switch, S8 - Loop closing switch. Detailed Implementation
[0058] To make the objectives, technical solutions, and advantages of this utility model clearer, the following detailed description of the expandable multi-ADC interleaved sampling circuit of this utility model, in conjunction with the accompanying drawings and embodiments, is provided. It should be understood that the specific embodiments described herein are merely illustrative of this utility model and are not intended to limit its scope.
[0059] In the description of this utility model, unless otherwise stated, "a plurality of" means two or more; the terms "center," "longitudinal," "lateral," "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0060] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will be able to understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0061] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.
[0062] Overall Structure
[0063] Please see Figure 4 and Figure 5 The core idea of this utility model is to construct a ring topology. For example... Figure 4 As shown, multiple sampling channels (channel 1 to N) are connected end-to-end to form a closed loop. Analog signals can be injected from any node on the loop. Figure 5 As shown, this structure has excellent scalability; the input channels of multiple independent analog-to-digital converter modules (ADC1, ..., ADCn) can be connected in series to form a longer "link" or "loop".
[0064] The structure and working principle of this utility model will be explained in detail below with a specific embodiment containing four analog input terminals and two dual-channel analog-to-digital converter modules. The circuit structure of this embodiment is as follows: Figure 6 , Figure 8 and Figure 9 As shown.
[0065] Detailed Description of Examples
[0066] 1. Circuit component composition
[0067] The circuit in this embodiment includes the following main parts:
[0068] The first analog-to-digital converter (ADC1) and the second analog-to-digital converter (ADC2) are the core sampling units of the circuit. In this example, we assume that both ADC1 and ADC2 are dual-channel ADCs, each containing one A channel and one B channel. For ease of explanation, we will refer to the two channels of ADC1 as "first A channel" and "first B channel," and the two channels of ADC2 as "second A channel" and "second B channel." We assume that the maximum sampling rate for each channel is 100 MSPS.
[0069] Analog input terminals (analog input 1, 2, 3, 4): These are four independent interfaces for external analog signal sources.
[0070] Switching circuit: Consists of 8 high-performance analog switches, divided into two groups:
[0071] Input switches (S1, S2, S3, S4): There are 4 switches in total. Each switch is responsible for connecting one analog input to a specific node in the ring topology. Specifically, S1 connects to analog input 1, S2 connects to analog input 2, S3 connects to analog input 3, and S4 connects to analog input 4.
[0072] Interconnecting switches (S5, S7, S6, S8): 4 in total. These switches are responsible for connecting the various ADC channels to form a ring topology. The on / off state of these switches determines the specific shape of the loop and the direction of signal flow.
[0073] 2. Circuit connection relationship (refer to) Figure 9 )
[0074] The connection relationship between the components is the key to this utility model, as detailed below:
[0075] Enter the connection:
[0076] One end of the input switch S1 is connected to analog input 1, and the other end is connected to the input node of the first A channel.
[0077] One end of the input switch S2 is connected to analog input 2, and the other end is connected to the input node of the first B channel.
[0078] One end of input switch S3 is connected to analog input 3, and the other end is connected to the input node of the second A channel.
[0079] One end of input switch S4 is connected to analog input 4, and the other end is connected to the input node of the second B channel.
[0080] Interconnection:
[0081] The first channel interconnection switch S5 is connected between the input nodes of the first A channel and the first B channel.
[0082] The second channel interconnection switch S7 is connected between the input nodes of the second A channel and the second B channel.
[0083] The bridging switch S6 is connected between the input nodes of the first B channel and the second A channel.
[0084] The loop closure switch S8 is connected between the input nodes of the second B channel and the first A channel.
[0085] By combining these eight switches, the four ADC channels (first A / B, second A / B) can be flexibly connected into various paths, forming a powerful and reconfigurable ring network. The state (closed / open) of all switches is controlled by a central controller (not shown in the diagram) according to application requirements.
[0086] It is worth noting that the state (closed / open) of all input switches (S1-S4) and interconnecting switches (S5-S8) is controlled by a single...
[0087] A controller (not shown in the diagram) provides unified control. This controller can be a microcontroller (MCU), FPGA, or dedicated logic control circuit, connected to the control terminal of each switch. Based on the specific requirements of the system application (e.g., selecting which input signal to acquire and what sampling rate is needed), the controller sends corresponding control signals to the switch circuits to precisely and independently set the on / off state of each switch, thereby dynamically constructing the required signal path and operating mode. This centralized programmable control is key to achieving high circuit flexibility.
[0088] 3. Working Mode and Operation Method
[0089] In the implementation of this utility model, the switching elements constituting the switching circuit can be selected according to specific application scenarios and performance requirements. For example, in applications with high requirements for switching speed and signal integrity, high-performance discrete analog switch integrated circuits can be selected. As an alternative, MOSFETs can also be used to construct the switching unit, and conduction and cutoff can be achieved by controlling their gate voltage. This method is low-cost and easy to integrate. In some special occasions where the requirements for switching losses are not strict or where a large power drive is required, relays can also be used as switching elements. All these different implementation methods fall within the protection scope of this utility model.
[0090] The following will refer to Figure 7 The example table shown details the operating modes of this circuit in different application scenarios. In the notation, "1" represents a closed switch, and "0" represents an open switch.
[0091] Mode 1: Single-channel maximum sampling rate mode (400 MSPS)
[0092] The goal of this mode is to concentrate the sampling capabilities of all four ADC channels on a single analog input signal to achieve the highest sampling rate achievable by the system.
[0093] Scenario: Collecting "Analog Input 1"
[0094] Switch states: S1=1, S2=0, S3=0, S4=0; S5=1, S6=1, S7=1, S8=0.
[0095] Signal path analysis:
[0096] The analog input signal 1 is injected into the input node of the first A channel through the closed S1.
[0097] Since all interconnecting switches S5, S7, and S6 are closed, the input nodes of these four ADC channels are shorted together, forming an equipotential point.
[0098] Therefore, the signal from analog input 1 is simultaneously applied to all four channels: the first A channel, the first B channel, the second A channel, and the second B channel.
[0099] Sampling method: In this case, the central controller needs to provide four strictly synchronized sampling clocks for these four channels, each with a phase offset of 90 degrees. For example:
[0100] Channel A, first channel: clock phase 0°
[0101] Channel B, first channel: clock phase 90°
[0102] Second Channel A: Clock Phase 180°
[0103] Second B channel: Clock phase 270°
[0104] Result: The four channels sampled analog input 1 in turn at a rate of 100 MSPS and at quarter-cycle time intervals. Finally, by rearranging and combining the four sampled data in chronological order, a high-speed data stream with an equivalent sampling rate of 4 × 100 MSPS = 400 MSPS was obtained.
[0105] Similarly, when it is necessary to acquire analog input 2 at 400 MSPS, simply set the switch states as follows: S2=1, S1 / 3 / 4=0; S5-S7=1, S8=0. The acquisition of inputs 3 and 4 can be done in the same manner.
[0106] Mode 2: Dual-channel parallel interleaved sampling mode (200 MSPS / channel)
[0107] The goal of this mode is to sample two analog input signals simultaneously and distribute system resources equally between the two signals, with each signal receiving the interleaved sampling capability of two ADC channels.
[0108] Scenario: Simultaneously collecting "Analog Input 1" and "Analog Input 3"
[0109] Switch states: S1=1, S3=1, S2=0, S4=0; S5=1, S7=1, S6=0, S8=0. (Refer to...) Figure 7 (Input lines 1 and 3)
[0110] Signal path analysis:
[0111] Signal 1 path: The signal of analog input 1 enters the first A channel through S1. Since S5 is closed, this signal is also sent to the first B channel. Therefore, analog input 1 is sampled by both the first A channel and the first B channel.
[0112] Signal 3 path: The signal from analog input 3 enters the second A channel through S3. Since S7 is closed, this signal is also sent to the second A channel. Therefore, analog input 3 is sampled jointly by the second A channel and the second B channel.
[0113] Results: Both analog input 1 and analog input 3 achieved dual-channel interleaved sampling, and their effective sampling rates were increased to 2 × 100 MSPS = 200 MSPS.
[0114] Other dual-channel combinations: By similarly configuring the switches, parallel sampling of any two input signals at 200 MSPS can be achieved. For example, Figure 7 The given "1, 2 input" combination (S1=1, S2=1, S6=1, S8=1) can be analyzed to show that input 1 is sampled by the first A channel and the second B channel, and input 2 is sampled by the first B channel and the second A channel.
[0115] Mode 3: Four-channel parallel independent sampling mode (100 MSPS / channel)
[0116] The goal of this mode is to sample all four analog input signals independently at the same time, with each signal occupying one ADC channel.
[0117] Switch states: S1=1, S2=1, S3=1, S4=1; S5=0, S7=0, S6=0, S8=0.
[0118] Signal path analysis:
[0119] All interconnect switches are off, and the four ADC channels are electrically isolated from each other.
[0120] The analog input 1 signal is sent to the first A channel only through S1.
[0121] The signal from analog input 2 is sent to the first B channel only through S2.
[0122] The signal from analog input 3 is sent to the second A channel only via S3.
[0123] The signal from analog input 4 is sent to the second B channel only via S4.
[0124] Sampling method: The four channels can use clocks of the same phase or clocks of different phases as needed to sample their respective input signals independently.
[0125] Result: The function of a four-channel data acquisition card was realized, with the sampling rate of each channel being the reference rate of the ADC, i.e., 100 MSPS.
[0126] 4. Implementation of Extensibility and Symmetry
[0127] Extensibility (see reference) Figure 5 The modular structure of this embodiment makes it extremely easy to expand. To upgrade the system to 6-channel interleaving, simply:
[0128] A new dual-channel third analog-to-digital converter module (ADC3) has been added.
[0129] Disconnect the existing loop, for example, disconnect S8.
[0130] By using the new interconnect switch, the second B channel can be connected to the first channel of ADC3, and then the second channel of ADC3 can be connected back to the first A channel, thus seamlessly "plugging" ADC3 into the loop.
[0131] Additionally, new input switches can be added to the channel nodes of ADC3 to support more analog inputs.
[0132] This process physically involves simply adding components to the PCB board without altering the original structure of ADC1 and ADC2.
[0133] Symmetry (refer to) Figure 8 In PCB layout design, the advantages of ring topology are fully realized. For example... Figure 8As shown, ADC1 and ADC2 can be placed symmetrically, and the interconnecting traces connecting them (paths corresponding to S5, S7, S6, and S8) can be designed to be of completely equal length. For example, the physical trace length from the first A channel node through S5 to the second A channel node can be precisely equal to the length from the first B channel node through S7 to the second B channel node. This symmetrical layout ensures that the complete signal path length from any input node (such as the output of S1) to any sampling channel on the ring (such as first A, first B, second A, and second B) is highly consistent or has predictable, compensable differences. This physical symmetry is an effective means of solving time bias in interleaved sampling.
[0134] In summary, this invention, through its innovative ring topology switch network structure, flexibly organizes independent ADC modules, which not only perfectly solves the shortcomings of existing technologies in terms of scalability and flexibility, but also greatly improves signal integrity and channel consistency through its inherent symmetry advantage. Thus, it can achieve a high-performance high-speed multi-channel data acquisition system with lower cost and simpler design.
[0135] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.
Claims
1. A scalable multi-ADC interleaved sampling circuit, comprising: At least two analog-to-digital converter modules; Multiple analog input terminals; And a switching circuit consisting of multiple switches; The feature is that each of the at least two analog-to-digital converter modules includes at least one analog input channel; The switching circuit includes multiple interconnecting switches, which are disposed between the analog input channels of the analog-to-digital converter module to connect the analog input channels to form a ring topology. The switching circuit also includes multiple input switches, and each of the analog input terminals is connected to a node on the ring topology through its corresponding input switch.
2. The circuit according to claim 1, characterized in that, The analog-to-digital converter module includes a first analog-to-digital converter module and a second analog-to-digital converter module; The first analog-to-digital converter module has a first A channel and a first B channel; The second analog-to-digital converter module has a second A channel and a second B channel.
3. The circuit according to claim 2, characterized in that, The interconnecting switch includes: A first channel interconnection switch is connected between the first channel A and the first channel B; A second channel interconnect switch is connected between the second channel A and the second channel B; A bridging interconnect switch is connected between the first B channel and the second A channel.
4. The circuit according to claim 2, characterized in that, The interconnecting switch further includes: A loop closure switch is connected between the second B channel and the first A channel.
5. The circuit according to claim 1, characterized in that, Each of the analog input terminals is connected to a unique analog-to-digital converter module's analog input channel via its corresponding input switch.
6. The circuit according to claim 1, characterized in that, The ring topology is configured such that by adding an analog-to-digital converter module and a corresponding interconnecting switch, the analog input channel of the newly added analog-to-digital converter module can be connected in series to the original ring topology.
7. The circuit according to claim 1, characterized in that, The interconnecting switches and input switches have the same signal transmission path length from any of the analog input terminals to any of the analog input channels.
8. The circuit according to claim 1, characterized in that, The switching circuit is configured to apply the analog input signal to all analog input channels simultaneously by closing the input switch corresponding to a selected analog input terminal and simultaneously closing all interconnecting switches.
9. The circuit according to claim 1, characterized in that, It also includes a controller; the controller is connected to the control terminals of the input switch and the interconnecting switch respectively, and is used to output control signals according to a preset sampling mode to independently control the closed or open state of each switch.
10. The circuit according to claim 1, characterized in that, The switches in the switching circuit are discrete analog switches, MOSFETs, or relays.