Control and readout circuit for very large pixel arrays, sensors and cameras

Abstract

This utility model relates to the field of image sensor technology, specifically a control and readout circuit, sensor, and camera for an ultra-large-scale pixel array. It includes four pixel array control units 1-4 and four pixel data readout units 5-8. By dividing the control and data readout circuit of the image sensor into four regions, each region containing one pixel array control unit and one pixel data readout unit, the four regions operate independently. The upper and lower regions start operating simultaneously. Only the separated circuit sections need to be analyzed to perform exposure control and data readout for the pixel array. This greatly simplifies the circuit scale to be analyzed, significantly shortens the project cycle, and requires only half the time of traditional methods to process the control and data readout of all rows of pixels. Furthermore, it improves the frame rate.

Description

Technical Field

[0001] This utility model relates to the field of image sensor technology, and in particular to a control and readout circuit, sensor and camera for a large-scale pixel array. Background Technology

[0002] Image sensors are optoelectronic imaging devices widely used in machine vision, target reconnaissance, security monitoring, and medical testing. Due to their advantages of low cost and high integration, image sensor chips can integrate more camera system functions, thereby reducing the peripheral circuitry of the camera and realizing the miniaturization and functional diversification of cameras.

[0003] Currently, the pixel array of an image sensor requires control and readout circuits to read the pixel charge quantization results line by line under different exposure times. As pixel size increases, the corresponding scale of control and readout circuits also increases, but the frame rate requirement continues to increase. This makes it increasingly difficult for back-end tools in the chip to analyze large-scale control and readout circuits, and it is also difficult to meet the frame rate requirement while increasing the scale of control and readout circuits. This poses a challenge to traditional implementation structures. Utility Model Content

[0004] In this section, as well as in the abstract and title of this application, some simplifications or omissions may be made to avoid obscuring the purpose of this section, the abstract, and the title of this application. Such simplifications or omissions shall not be used to limit the scope of this utility model.

[0005] To address the shortcomings of existing technologies, one objective of this invention is to provide a control and reading circuit for an ultra-large-scale pixel array.

[0006] To achieve the above objectives, this utility model adopts the following technical solution: a control and reading circuit for an ultra-large-scale pixel array, comprising four pixel array control units 1-4 and four pixel data reading units 5-8. When these eight units are in operation, they respectively act on four sub-parts of the entire pixel array. Each of the four pixel array control units is configured to control one of the four sub-parts of the entire pixel array, and each of the four pixel reading units is configured to read data from one of the four sub-parts of the entire pixel array. Wherein:

[0007] 1) Of the four pixel array control units 1-4, pixel array control unit 1 controls the pixels in rows 1, 3, 5...y / 2-1 of the upper half, pixel array control unit 3 controls the pixels in rows 2, 4, 6...y / 2 of the upper half, pixel array control unit 2 controls the pixels in rows y / 2+1, y / 2+3, y / 2+5...y-1 of the lower half, and pixel array control unit 4 controls the pixels in rows y / 2+2, y / 2+4, y / 2+6...y of the lower half, and...

[0008] 2) Of the four pixel data reading units 5-8, pixel data reading unit 5 outputs the 1st, 2nd, 3rd...x / 2nd pixels of each row in the upper half; pixel reading unit 7 outputs the x / 2+1th, x / 2+2th, x / 2+3rd...xth pixels of each row in the upper half; pixel reading unit 6 outputs the 1st, 2nd, 3rd...x / 2nd pixels of each row in the lower half; and pixel reading unit 8 outputs the x / 2+1th, x / 2+2th, x / 2+3rd...xth pixels of each row in the lower half.

[0009] 3) The operation timing of the four pixel array control units 1-4 is set such that the operation of pixel array control unit 1 and pixel array control unit 3 is performed sequentially, and the operation of pixel array control unit 2 and pixel array control unit 4 is performed sequentially.

[0010] In a preferred embodiment of the control and reading circuit for the ultra-large-scale pixel array described in this utility model, pixel array control unit 1 and pixel array control unit 2 are configured to operate simultaneously, and pixel array control unit 3 and pixel array control unit 4 are configured to operate simultaneously.

[0011] Another objective of this invention is to provide a sensor for sensing video signals, including the control and reading circuit of the ultra-large-scale pixel array.

[0012] Another objective of this invention is to provide a camera that includes the aforementioned sensor.

[0013] The beneficial effects of this invention are as follows: By dividing the control and data reading circuit of the image sensor into four regions, each region includes a pixel array control unit and a pixel data reading unit. The four regions operate independently, with the upper and lower regions starting simultaneously. Only the separated circuitry needs to be analyzed to perform exposure control and data reading for the pixel array separately. This greatly simplifies the circuitry required for analysis and significantly shortens the project cycle. Furthermore, it only takes half the time of traditional methods to process the control and data reading of all rows of pixels, thus improving the frame rate. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the control and organization of pixel arrays in existing image sensors.

[0016] Figure 2 This is a schematic diagram of the pixel array control and organization of the image sensor of this utility model.

[0017] Figure 3 This is a schematic diagram of the data reading timing after pixel exposure according to this utility model. Detailed Implementation

[0018] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.

[0019] Reference Figures 1-3 The following example, using a pixel array with y rows and x pixels in each row, will be used to illustrate the technical solution of this utility model in detail.

[0020] Traditional circuit structure is shown in the attached figure. Figure 1 As shown, the overall circuit mainly includes a pixel array section, a pixel array control unit, a data reading and processing module, a system control unit, and a configuration and output interface. The pixel array control unit performs exposure timing control on the pixels row by row from row 1 to row y. The data reading and processing module outputs the data of the first pixel to the xth pixel in each row in sequence. For ultra-large-scale pixel arrays, the pixel array control unit and the data reading and processing module will become very large, and the analysis time of the back-end tools will be greatly increased.

[0021] Specifically, this solution divides the pixel array control unit and data reading and processing module into four parts. For ease of description, x and y are assumed to be even numbers in this solution. The pixel array control unit 1 controls the pixels in rows 1, 3, 5...y / 2-1 of the upper half, and the pixel array control unit 3 controls the pixels in rows 2, 4, 6...y / 2 of the upper half. The pixel array control unit 2 controls the pixels in rows y / 2+1, y / 2+3, y / 2+5...y-1 of the lower half, and the pixel array control unit 3 controls the pixels in rows y / 2+2, y / 2+4, y / 2+6...y of the lower half. The pixel reading unit 1 outputs the 1st, 2nd, 3rd...x / 2nd pixels of each row in the upper half, and the pixel reading unit 3 outputs the x / 2+1, x / 2+2, x / 2+3...xth pixels of each row in the upper half. The pixel reading unit 2 outputs the 1st, 2nd, 3rd...x / 2nd pixels of each row in the lower half, and the pixel reading unit 3 outputs the x / 2+1, x / 2+2, x / 2+3...xth pixels of each row in the lower half. The circuit structure is shown in the attached figure. Figure 2 As shown.

[0022] This distribution method helps optimize the signal transmission path and reduce signal interference. Furthermore, the staggered arrangement of adjacent positions helps improve control precision and efficiency, ensuring that each pixel row can be exposed and reset under optimal conditions.

[0023] It should be noted that the entire pixel array is divided into four parts. The upper left and upper right parts can be grouped together for simultaneous operation, and the lower left and lower right parts can be grouped together for simultaneous operation; alternatively, the upper left and lower left parts can be grouped together for simultaneous operation, and the upper right and lower right parts can be grouped together for simultaneous operation. These division methods are all consistent with the purpose of this utility model.

[0024] Preferably, after the image sensor starts working, the upper and lower halves work together. That is, the first row and the y / 2+1th row simultaneously reset, expose, and read data row by row of the pixel array. Then, the second row and the y / 2+2th row simultaneously reset, expose, and read data row by row of the pixel array, until the y / 2th row and the yth row simultaneously reset, expose, and read data row by row of the pixel array. The control and reading timing is as follows. Figure 3 As shown.

[0025] In this structure, the control and data reading circuits of the four parts are completely identical and reusable. The chip back-end tool only needs to perform timing analysis on one part of the circuit (corresponding to the pixel array to be processed as y / 4 rows x / 2 columns) to obtain the final usable circuit, and then reuse it four times, which greatly shortens the project cycle.

[0026] As can be seen from the above, it only takes half the time of the traditional method to process the control and data reading of all row pixels.

[0027] Furthermore, this invention also provides a sensor, including a control and readout circuit for a very large pixel array, used for sensing video signals and adaptable to very large pixel arrays. The output of this image sensor is connected to a digital signal processor (DSP), which is responsible for further processing and analysis of the pixel data output by the sensor. Through this connection, efficient image processing can be achieved, meeting the requirements of high-resolution image processing.

[0028] After the sensor starts working, the upper and lower halves work together. That is, rows 1 and y / 2+1 simultaneously reset, expose, and read data row by row of the pixel array. Then, rows 2 and y / 2+2 simultaneously reset, expose, and read data row by row, until rows y / 2 and y simultaneously reset, expose, and read data row by row. The control and readout timing is as shown in the attached figure. Figure 3 As shown.

[0029] Furthermore, this invention also provides a camera that uses the aforementioned sensor, is adaptable to ultra-large pixel size, and has high control and readout efficiency. The camera includes a video camera.

[0030] It should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and are not intended to limit it. Although this utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications or substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A control and read circuit for a very large pixel array, characterized by It includes four pixel array control units 1-4 and four pixel data reading units 5-8. When operating, these eight units act on four sub-parts of the entire pixel array. Each of the four pixel array control units is configured to control one of the four sub-parts of the entire pixel array, and each of the four pixel reading units is configured to read data from one of the four sub-parts of the entire pixel array. 1) Of the four pixel array control units 1-4, pixel array control unit 1 controls the pixels in rows 1, 3, 5...y / 2-1 of the upper half, pixel array control unit 3 controls the pixels in rows 2, 4, 6...y / 2 of the upper half, pixel array control unit 2 controls the pixels in rows y / 2+1, y / 2+3, y / 2+5...y-1 of the lower half, and pixel array control unit 4 controls the pixels in rows y / 2+2, y / 2+4, y / 2+6...y of the lower half, and... 2) Of the four pixel data reading units 5-8, pixel data reading unit 5 outputs the 1st, 2nd, 3rd...x / 2nd pixels of each row in the upper half; pixel reading unit 7 outputs the x / 2+1th, x / 2+2th, x / 2+3rd...xth pixels of each row in the upper half; pixel reading unit 6 outputs the 1st, 2nd, 3rd...x / 2nd pixels of each row in the lower half; and pixel reading unit 8 outputs the x / 2+1th, x / 2+2th, x / 2+3rd...xth pixels of each row in the lower half. 3) The operation timing of the four pixel array control units 1-4 is set such that the operation of pixel array control unit 1 and pixel array control unit 3 is performed sequentially, and the operation of pixel array control unit 2 and pixel array control unit 4 is performed sequentially.

2. The control and readout circuit for the ultra-large-scale pixel array as described in claim 1, characterized in that: Pixel array control unit 1 and pixel array control unit 2 are configured to operate simultaneously, and pixel array control unit 3 and pixel array control unit 4 are configured to operate simultaneously.

3. A sensor for sensing video signals, characterized in that... Includes the control and readout circuitry for the ultra-large-scale pixel array as described in claim 1 or 2.

4. A camera, characterized in that... Including the sensor as described in claim 3.

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