A trench-type IGBT power semiconductor device

Abstract

The utility model relates to IGBT semiconductor technology especially relates to a trench type IGBT power semiconductor device, and it is formed with horizontal direction's second type buffer area and first conductive type buffer area through control ion injection in the bottom of first conductive type drift region, is formed with horizontal direction's second conductive type base area and first conductive type buffer area through control different impurity, injection control ion in the top of first conductive type drift region, is formed with several grooves in the front etching of first conductive type drift region top. The utility model information is according to the process ability to reduce or increase mesa2 width near the false gate groove, and the switching characteristic and the on characteristic of IGBT are flexibly adjusted.

Description

Technical Field

[0001] This utility model relates to IGBT semiconductor technology, and more particularly to a trench-type IGBT power semiconductor device. Background Technology

[0002] Trench IGBTs are an important type of power semiconductor device, widely used in industrial frequency conversion, consumer electronics, rail transportation, and new energy fields. In traditional trench IGBT structures, to reduce the on-state voltage drop, it's necessary to increase the carrier concentration on the front side of the chip during conduction. Therefore, a dummy gate and floating P-region design are introduced, concentrating the emitter N+ region within a limited grounded Pwell region, such as... Figure 1 As shown. However, this design only uses the channel on one side of the true gate, while the other side is a floating dummy P region, which will cause uneven cell current during the chip turn-on process. Macroscopically, this manifests as current oscillation during the turn-on process, and in severe cases, it can cause the chip to fail and burn out during the switching process.

[0003] On the other hand, in the trench IGBT structure, Mesa1 is the width of the mesa including the channel, and Mesa2 is the width of the mesa near the true gate trench. Reducing its width is limited by process limitations, and excessive reduction of the PPLUS injection will affect the threshold voltage. Mesa2 is the width of the mesa without the channel, and Mesa2 is the width of the mesa near the dummy gate trench. It is formed by the dummy gate used to adjust the capacitance and switching characteristics and does not affect the channel characteristics. The emitter contact is generally located in the middle of Mesa. When the Mesa width is too small, the emitter contact is prone to short-circuiting with the gate. Furthermore, the PPLUS and contact share a single photomask; if the PPLUS injection is too close to the channel, it can easily affect the device's conduction characteristics.

[0004] For example, prior art 1, CN114975620A, discloses a trench-type IGBT device with low input capacitance and its fabrication method. This patent involves setting several in-trench emitter conductive polysilicon wafers within a trench. These in-trench emitter conductive polysilicon wafers extend from the trench opening towards the bottom of the trench, and are insulated by gate conductive polysilicon wafers in the region where the inter-polysilicon dielectric layer is located. First conductivity type source regions are set on adjacent outer walls between the trenches, distributed along the length of the trench. The bottom of the in-trench emitter conductive polysilicon wafers within the trench is located below the bottom of the first conductivity type source regions. This reduces the input capacitance without affecting the Miller capacitance, effectively reducing the device's switching losses. However, this patent does not provide a solution for further optimizing the mesa width near the dummy gate trench, making it impossible to flexibly adjust the IGBT's switching and conduction characteristics according to process capabilities.

[0005] For example, prior art 2, CN111384149A, discloses a trench-type IGBT and its fabrication method. This patent, by setting a first trench, a second trench, and a third trench, as well as a first gate, a second gate, and a third gate in each cell, where the first and second gates can be considered true gates and the third gate can be considered a dummy gate, enables the trench-type IGBT to have smaller Miller capacitance and better switching characteristics, while also exhibiting better reverse withstand voltage, better EAS capability, and lower conduction loss. However, this patent does not provide a scheme for adjusting the width of the dummy gate trench, making it impossible to flexibly adjust the switching and conduction characteristics of the IGBT according to process capabilities. Utility Model Content

[0006] This invention addresses the problem in existing trench-type IGBT power semiconductor devices that cannot flexibly adjust the width of the mesa near the dummy gate trench according to process capabilities, thus failing to optimize the switching and conduction characteristics of the IGBT. It provides a trench-type IGBT power semiconductor device.

[0007] To solve the above-mentioned technical problems, the present invention provides a solution through the following technical method:

[0008] A trench-type IGBT power semiconductor device includes a semiconductor substrate, with an emitter metal layer and a collector electrode respectively disposed on the top and bottom of the semiconductor substrate; the semiconductor substrate also has a first conductivity type drift region.

[0009] At the bottom of the first conductivity type drift region, a horizontal second type buffer and a first conductivity type buffer are formed by controlled ion implantation.

[0010] At the top of the first conductivity type drift region, by controlling different impurities, control ions are injected to form a horizontal second conductivity type base region and a first conductivity type buffer region;

[0011] Several trenches are formed on the front side of the first conductivity type drift region by etching.

[0012] The IGBT device designed in this invention can flexibly adjust the switching and conduction characteristics of the IGBT to achieve optimal performance.

[0013] Preferably, the gate dielectric layer is generated in the trench by thermal oxidation or deposition, and the thickness of the gate dielectric is 100nm to 500nm.

[0014] Preferably, the depth of the trench is 4µm-10µm.

[0015] Preferably, the gate dielectric layer is filled with a first gate, a second gate, and a third gate.

[0016] Preferably, the first gate, the second gate, and the third gate are located on the sidewall and bottom wall of the trench; mesa1 is formed between the first gate and the second gate; mesa2 is formed between the second gates; and mesa2 is formed between the second gate and the third trench.

[0017] Preferably, Mesa1 and Mesa2 are provided with metal contact holes 109, and a second conductive type emission area is provided below the metal contact holes.

[0018] Preferably, the second conductivity type emission region is located below the metal contact hole, and the depth of the metal contact hole is greater than the depth of the first conductivity type emission region; the width of the contact hole is 0.2μm to 1.0μm.

[0019] Preferably, the width of Mesa1 is 0.5μm to 1.5μm, and the width of Mesa2 is 0.3μm to 1.0μm.

[0020] This utility model, by adopting the above technical solution, has the following significant technical effects:

[0021] This invention allows for flexible adjustment of the switching and conduction characteristics of the IGBT under existing process capabilities by reducing or increasing the width of the mesa2 near the dummy gate trench while keeping the width of the mesa1 near the true gate trench constant, based on process capabilities. This achieves optimal performance.

[0022] This invention connects the emitter contact hole within the Mesa and the dummy gate, eliminating the need for excessively small contact widths. This increases process compatibility, prevents short circuits between the emitter contact and the gate, and solves the problem of easy short circuits between the emitter contact and the gate in the prior art.

[0023] Because the emitter contact hole is connected within the Mesa and the dummy gate, the PPLUS injection is closer to the dummy gate side, which can improve the conduction characteristics of the IGBT.

[0024] This invention can reduce the negative impact of excessive reduction in the width of Mesa1 on the conduction characteristics of IGBT by adjusting the width of the mesa2 near the dummy gate trench.

[0025] Because the Mesa width can be further reduced, this invention is beneficial for improving the integration of IGBTs and reducing costs. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a traditional trench gate IGBT device.

[0027] Figure 2 This is a schematic diagram of the structure of the trench gate IGBT device according to the present invention;

[0028] Figure 3 This is a schematic diagram showing the location of the drift region of the IGBT device substrate and buffer layer of this utility model.

[0029] Figure 4 This is a schematic diagram showing the location of the front buffer layer and base region of the IGBT device of this utility model.

[0030] Figure 5 This is a schematic diagram showing the location of the trenches formed in the IGBT device of this utility model.

[0031] Figure 6 This is a schematic diagram of the IGBT device of this utility model, showing the filling of the isolation medium and the gate medium in the trench.

[0032] Figure 7 This is a schematic diagram of the formation of the front emitter of the IGBT device of this utility model.

[0033] Figure 8 This is a schematic diagram showing the formation of the front contact hole of the IGBT device of this utility model; Figure 9 This utility model is a schematic diagram of another IGBT structure implemented according to the present invention.

[0034] Figure 10 This is a top view of the trench gate IGBT device of this utility model.

[0035] Among them, 100—second type buffer, 101—first type of conductivity buffer, 102—first type of conductivity drift region, 103—first type of conductivity buffer, 104—second type of conductivity base region, 105—first type of conductivity emitter region, 106—second type of conductivity emitter region, 107—first gate, 108—second gate, 109—metal contact hole, 110—emitter metal layer, 111—collector, 112—third gate, 201—trench, 202—gate dielectric layer, 203—deposited dielectric layer. Detailed Implementation

[0036] The following is in conjunction with the appendix Figure 1-10 The present invention will be further described in detail with reference to the embodiments.

[0037] Example 1

[0038] A trench-type IGBT power semiconductor device includes a semiconductor substrate, with an emitter metal layer 110 and a collector 111 respectively disposed at the top and bottom of the semiconductor substrate; a first conductivity type drift region 102 is also disposed on the semiconductor substrate.

[0039] A horizontal second-type buffer 100 and a first-type buffer 101 are formed at the bottom of the first conductivity type drift region 102 by controlled ion implantation.

[0040] At the top of the first conductivity type drift region 102, by controlling different impurities, control ions are injected to form a horizontal second conductivity type base region 104 and a first conductivity type buffer region 103;

[0041] Several trenches 201 are formed by etching on the front side of the first conductivity type drift region 102.

[0042] The IGBT device designed in this invention can flexibly adjust the switching and conduction characteristics of the IGBT to achieve optimal performance.

[0043] A gate dielectric layer 202 is formed within the trench 201 by thermal oxidation or deposition, and the thickness of the gate dielectric layer 202 is 100 nm. The depth of the trench 201 is 4 μm.

[0044] The gate dielectric layer 202 is filled with a first gate 107, a second gate 108 and a third gate 112.

[0045] The first gate 107, the second gate 108 and the third gate 112 are located on the sidewall and bottom wall of the trench 201; a mesa1 is formed between the first gate 107 and the second gate 108; a mesa2 is formed between the second gates 108 and the third gate 112.

[0046] Mesa1 and Mesa2 are provided with metal contact holes 109, and a second conductivity type emission area 106 is provided below the metal contact holes 109.

[0047] A metal contact hole 109 is etched on the deposition medium layer 203; a second conductivity type emission region 106 is located below the metal contact hole 109, and the depth of the metal contact hole 109 is greater than the depth of the first conductivity type emission region 105; the width of the contact hole is 0.2 μm.

[0048] Mesa1 has a width of 0.5 μm, and Mesa2 has a width of 0.3 μm.

[0049] Example 2

[0050] Based on Example 1, in this example, a gate dielectric layer 202 is formed in the trench 201 by thermal oxidation or deposition, and the thickness of the gate dielectric layer 202 is 300 nm. The depth of the trench 201 is 6 μm.

[0051] The gate dielectric layer 202 is filled with a first gate 107, a second gate 108 and a third gate 112.

[0052] The first gate 107, the second gate 108 and the third gate 112 are located on the sidewall and bottom wall of the trench 201; a mesa1 is formed between the first gate 107 and the second gate 108; a mesa2 is formed between the second gates 108 and the third gate 112.

[0053] Mesa1 and Mesa2 are provided with metal contact holes 109, and a second conductivity type emission area 106 is provided below the metal contact holes 109.

[0054] The second conductivity type emission region 106 is located below the metal contact hole 109, and the depth of the metal contact hole 109 is greater than the depth of the first conductivity type emission region 105; the width of the contact hole is 0.6 μm.

[0055] Mesa1 has a width of 1 μm, and Mesa2 has a width of 0.7 μm.

[0056] Example 3

[0057] Based on Example 1, the difference is that a gate dielectric layer 202 is formed in the trench 201 by thermal oxidation or deposition, and the thickness of the gate dielectric layer 202 is 500 nm. The depth of the trench 201 is 10 μm. The gate dielectric layer 202 is filled with a first gate 107, a second gate 108, and a third gate 112. The first gate 107, the second gate 108, and the third gate 112 are located on the sidewalls and bottom wall of the trench 201; a mesa1 is formed between the first gate 107 and the second gate 108; a mesa2 is formed between each other of the second gate 108; and a mesa2 is formed between the second gate 108 and the third gate 112.

[0058] Mesa1 and Mesa2 are provided with metal contact holes 109, and a second conductivity type emission area 106 is provided below the metal contact holes 109.

[0059] The second conductivity type emission region 106 is located below the metal contact hole 109, and the depth of the metal contact hole 109 is greater than the depth of the first conductivity type emission region 105; the width of the metal contact hole 109 is 1.0 μm.

[0060] Mesa1 has a width of 1.5 μm, and Mesa2 has a width of 1.0 μm.

[0061] Example 4

[0062] The trench-type IGBT in this embodiment includes a semiconductor substrate. Figure 3The process includes a semiconductor substrate, wherein the semiconductor substrate and a buffer layer of a first conductivity type are formed by controlled ion implantation within a first conductivity type drift region 102. A base region of a second conductivity type (i.e., Pabse) and a buffer layer of the first conductivity type 101 are formed by controlled ion implantation of different impurities within the first conductivity type drift region 102, such as... Figure 4 As shown. Figure 5 In order to be in Figure 4 Based on this, a gate trench 201 is formed by etching the drift region within the first conductivity type drift region 102 through an etching process.

[0063] Figure 6 In the middle, the gate trench 201 is filled with isolation dielectric and gate dielectric. Figure 7 In the middle, a first conductivity type emitter region 105, namely an N+ emitter region, is defined on both sides of a portion of the gate trench 201, formed by ion implantation, such as... Figure 7 As shown.

[0064] exist Figure 7 Based on this, a dielectric layer is deposited, and then contact holes are etched to form them. These contact holes need to penetrate the dielectric layer and extend into the first conductivity type drift region 102. Then, a second conductivity type emitter region 106 is formed through ion implantation. Figure 8 As shown, a metal layer is deposited on the region, and the metal is connected to the metal contact hole 109.

[0065] In this trench IGBT, the gate structure includes multiple true gate units and multiple dummy gate units. The first gate 107 is a true gate unit, and the second gate 108 and the third gate 112 are dummy gate units. At least two second gates 108 and at least one third gate 112 are disposed between adjacent true gate units, and the dummy gate units are disposed between two second gates 108. Each true gate unit and each second gate 108 is provided with a corresponding metal contact hole 109. Metal contact holes 109 are also provided between each true gate unit and an adjacent second gate 108, and between each second gate 108 and a third gate 112. Furthermore, the metal contact hole 109 between a true gate unit and an adjacent second gate 108 is also connected and merged with the metal contact hole 109 in the adjacent second gate 108.

[0066] The ratio between the true gate cell (107) and the adjacent second gate 108 and third gate 112 is variable and can be flexibly adjusted according to switching and conduction characteristics. The size of the emitter metal contact hole 109 is flexibly adjustable according to the width of mesa2, such as... Figure 6 As shown, one could consider including Figure 2The emitter metal contact holes 109 on both sides of the second gate are merged, using a single metal hole to achieve contact between two mesa and one dummy gate, further increasing the adjustment space for the mesa width. Specifically, a metal contact hole 109 is provided between the true gate unit and the adjacent second gate 108, and a metal contact hole 109 is provided within the adjacent second gate 108. After merging, the metal contact holes 109... Figure 2 The middle can be uniformly connected to the emitter; in addition, the metal contact hole 109 in the true gate unit and the third gate 112 can be connected to the gate respectively.

[0067] The novel microgroove 201 IGBT structure proposed in this embodiment can be manufactured using the existing microgroove IGBT process without the need for additional processes, thus avoiding increased production costs due to process improvements.

[0068] The position layout diagram of the contact hole in the novel microgroove 201IGBT structure proposed in this embodiment of the utility model.

[0069] The width of the cell trench 201 is 1.5 μm, and the depth of the cell trench 201 is 8 μm; within the cell, the spacing between two cell trenches 201 is 5 μm. The thickness of the insulating medium of the trench 201 is 100 nm to 500 nm.

[0070] In the embodiments, for N-type IGBT devices, the first conductivity type refers to N-type and the second conductivity type refers to P-type; for P-type IGBT devices, the types referred to by the first conductivity type and the second conductivity type are exactly the opposite of those of N-type semiconductor devices.

Claims

1. A trench type IGBT power semiconductor device comprising a semiconductor substrate, a top and a bottom of the semiconductor substrate being provided with an emitter metal layer and a collector, respectively; characterized in that, The semiconductor substrate also has a drift region of the first conductivity type; At the bottom of the first conductivity type drift region, a horizontal second type buffer and a first conductivity type buffer are formed by controlled ion implantation. At the top of the first conductivity type drift region, by controlling different impurities, control ions are injected to form a horizontal second conductivity type base region and a first conductivity type buffer region; Several trenches are formed on the front side of the first conductivity type drift region by etching.

2. The trench IGBT power semiconductor device according to claim 1, wherein The gate dielectric layer is generated in the trench by thermal oxidation or deposition, and the thickness of the gate dielectric is 100nm to 500nm.

3. The trench IGBT power semiconductor device according to claim 1, wherein The depth of the trench is 4um-10um.

4. The trench IGBT power semiconductor device according to claim 2, wherein The gate dielectric layer is filled with a first gate, a second gate, and a third gate.

5. A trench-type IGBT power semiconductor device according to claim 4, characterized in that, The first gate, the second gate, and the third gate are located on the sidewall and bottom wall of the trench; mesa1 is formed between the first gate and the second gate; mesa2 is formed between the second gates; and mesa2 is formed between the second gate and the third trench.

6. The trench IGBT power semiconductor device according to claim 5, wherein Mesa1 and Mesa2 are provided with metal contact holes (109), and a second conductive type emission area is provided below the metal contact holes.

7. The trench IGBT power semiconductor device according to claim 6, wherein The second conductivity type emitter region is located below the metal contact hole, and the depth of the metal contact hole is greater than the depth of the first conductivity type emitter region; the width of the contact hole is 0.2μm to 1.0μm.

8. The trench IGBT power semiconductor device according to claim 1, wherein Mesa1 has a width of 0.5μm to 1.5μm, and Mesa2 has a width of 0.3μm to 1.0μm.

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