Semiconductor structure

Abstract

A semiconductor structure is provided. A semiconductor structure includes a first gate and a second gate spaced apart from each other in a first direction, wherein each gate extends in a second direction perpendicular to the first direction. An insulating feature is spaced apart from the first gate and the second gate in the first direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the second direction. A first contact is located between the first gate and the insulating feature, and a second contact is located between the second gate and the insulating feature, wherein the first contact and the second contact extend along the second direction and terminate at a first contact endpoint and a second contact endpoint, respectively. The first contact endpoint defines a first vertical plane intersecting the insulating feature, and the second contact endpoint defines a second vertical plane intersecting the insulating feature.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Utility Model Content

[0004] Some embodiments disclosed herein provide a semiconductor structure including a first gate structure and a second gate structure, a first vertically extending dielectric structure and a second vertically extending dielectric structure, and an insulating feature. The first gate structure and the second gate structure are spaced apart from each other along a transverse X direction, wherein the first gate structure and the second gate structure extend along a transverse Y direction, the transverse X direction being perpendicular to the transverse Y direction. The first vertically extending dielectric structure and the second vertically extending dielectric structure are spaced apart from each other along the transverse Y direction and extend along the transverse X direction. The insulating feature is spaced apart from the first gate structure and the second gate structure along the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction, wherein the first line endpoint contacts the first vertically extending dielectric structure, and wherein the second line endpoint contacts the second vertically extending dielectric structure.

[0005] Some embodiments disclosed herein provide a semiconductor structure including a first gate structure and a second gate structure, an insulating feature, a first conductive contact and a second conductive contact, and at least one vertically extending dielectric structure. The first gate structure and the second gate structure are spaced apart from each other along a transverse X direction, wherein the first gate structure and the second gate structure extend along a transverse Y direction, the transverse X direction being perpendicular to the transverse Y direction. The insulating feature is spaced apart from the first gate structure and the second gate structure along the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction. A first conductive contact is located between the first gate structure and the insulating feature, and a second conductive contact is located between the second gate structure and the insulating feature. At least one vertically extending dielectric structure extends along the transverse X direction, wherein the first line endpoint of the insulating feature is spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance.

[0006] Some embodiments disclosed herein provide a semiconductor structure including a first gate structure and a second gate structure spaced apart from each other along a transverse X direction, wherein the first gate structure and the second gate structure extend along a transverse Y direction, and the transverse X direction is perpendicular to the transverse Y direction. An insulating feature is spaced apart from the first gate structure and the second gate structure along the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction, and a first conductive contact is located between the first gate structure and the insulating feature, and a second conductive contact is located between the second gate structure and the insulating feature, wherein the first conductive contact and the second conductive contact extend along the transverse Y direction and terminate at a first contact endpoint and a second contact endpoint, respectively. The first contact endpoint defines a first vertical plane, which intersects with the insulating feature, and the second contact endpoint defines a second vertical plane, which also intersects with the insulating feature. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, the following detailed description will provide the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a top-down schematic layout of a semiconductor structure;

[0009] Figure 2 According to some embodiments Figure 1 A schematic layout diagram of a portion of the semiconductor structure from top to bottom;

[0010] Figures 3 to 30 It is based on some embodiments at various stages of manufacturing. Figure 2 Partial semiconductor structure;

[0011] Figure 31 It is used to form according to some embodiments Figure 2 A flowchart of the structural method;

[0012] Figure 32 According to some embodiments Figure 1 A schematic layout diagram of a portion of the semiconductor structure from top to bottom;

[0013] Figures 33 to 60 It is based on some embodiments at various stages of manufacturing. Figure 32 Partial semiconductor structure;

[0014] Figure 61 It is used to form according to some embodiments Figure 32 A flowchart of the structural method;

[0015] Figure 62 and Figure 63 According to some embodiments Figure 38 A focused view of a portion of the semiconductor structure;

[0016] Figure 64 According to some embodiments Figure 2 Transmission electron microscope (TEM) images of some semiconductor devices;

[0017] Figure 65 According to some embodiments Figure 2 Transmission electron microscope (TEM) images of some semiconductor devices.

[0018] [Symbol Explanation]

[0019] 99:Substrate

[0020] 100: Structure / Semiconductor Structure / Semiconductor Device

[0021] 100': Part

[0022] 100”: Part

[0023] 109: Top surface

[0024] 190: Cavity protrusion

[0025] 200: Fins

[0026] 240: STI / STI Features

[0027] 250: Virtual Fins

[0028] 280: Cavity / Opening

[0029] 300: Gate / Gate Structure

[0030] 301: First gate

[0031] 302: Second gate

[0032] 310: Gate section

[0033] 311: Gate section

[0034] 312: Gate section

[0035] 321: First endpoint

[0036] 322: Second endpoint

[0037] 350: Gate capping layer

[0038] 351: Dielectric layer segment / segment

[0039] 352: Dielectric layer segment / segment

[0040] 380: Opening

[0041] 390: Opening

[0042] 400: Dielectric structure / dielectric pillar

[0043] 401: First vertically extending dielectric structure / dielectric structure / first dielectric post

[0044] 402: Second vertically extending dielectric structure / dielectric structure / second dielectric post

[0045] 421: Inner surface / inner sidewall

[0046] 422: Inner surface / inner sidewall

[0047] 423: Bottom Endpoint

[0048] 424: Top Endpoint

[0049] 499: Excess dielectric material

[0050] 500: Insulation Characteristics

[0051] 511: First line endpoint

[0052] 512: Second line endpoint

[0053] 521: First sidewall

[0054] 522: Second sidewall

[0055] 541: Upper part

[0056] 542: Upper part

[0057] 590: Insulating materials / Dielectric materials

[0058] 599: Redundant part

[0059] 600: Source / Drain Contacts / Conductive Contacts

[0060] 601: First source / drain contact / first conductive contact

[0061] 602: Second source / drain contact / second conductive contact

[0062] 610: Conductive materials

[0063] 611: First contact end point

[0064] 612: Second contact end point

[0065] 620: Mask

[0066] 650: Source / Drain Characteristics

[0067] 660: ILD structure / ILD layer / dielectric layer

[0068] 665: Sidewall gasket

[0069] 669: Cavity

[0070] 670: Dielectric top cover

[0071] 678: Sidewall

[0072] 679: Location

[0073] 701: Carbon substrate layer

[0074] 702: Oxide-based intermediate layer

[0075] 703: Top layer of photoresist

[0076] 710: Opening

[0077] 800: Additional dielectric material / dielectric material

[0078] 962: Outer Frame

[0079] 963: Outer frame

[0080] 965: Area

[0081] 999: Top surface

[0082] 1000: Method

[0083] 2000: Method

[0084] 6110: First vertical plane

[0085] 6120: Second vertical plane

[0086] A1: Interior angle / angle

[0087] A2:Inner angle / angle

[0088] D1: Distance

[0089] D2: Distance

[0090] H1: Interface height

[0091] S1010: Operation

[0092] S1020: Operation

[0093] S1030: Operation

[0094] S1040: Operation

[0095] S1050: Operation

[0096] S1060: Operation

[0097] S1070: Operation

[0098] S1080: Operation

[0099] S1090: Operation

[0100] S2010: Operation

[0101] S2020: Operation

[0102] S2030: Operation

[0103] S2040: Operation

[0104] S2050: Operation

[0105] S2060: Operation

[0106] S2070: Operation

[0107] S2080: Operation

[0108] S2090: Operation

[0109] W1: Width

[0110] W2: Width

[0111] X: Direction

[0112] Y: direction Detailed Implementation

[0113] The following disclosure provides numerous different embodiments or examples for implementing various features of the subject matter of the application. Specific examples of components and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or above a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or words may be repeated in various examples. This repetition is for simplicity and clarity and is not, in itself, merely a relationship between the various embodiments and / or configurations discussed.

[0114] Furthermore, the spatially related terms used herein, such as “above,” “on top of,” “on,” “on,” “top,” “below,” “under,” “below,” “below,” “below,” “below,” “bottom,” “face,” etc., are for descriptive purposes to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, these spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0115] In some embodiments herein, a “material structure” is one comprising at least 50 wt% identifiable material, such as at least 60 wt% identifiable material, at least 75 wt% identifiable material, at least 90 wt% identifiable material, at least 95 wt% identifiable material, or at least 100 wt% identifiable material, and a structure formed from the material comprises at least 50 wt% identifiable material, such as at least 60 wt% identifiable material, at least 75 wt% identifiable material, at least 90 wt% identifiable material, at least 95 wt% identifiable material, or at least 100 wt% identifiable material. For example, in some embodiments, each of the tungsten structure and the structure formed from tungsten is a structure comprising at least 50 wt%, at least 60 wt%, at least 75 wt%, at least 90 wt%, at least 95 wt%, or at least 100 wt% tungsten.

[0116] For the sake of brevity, this document will not describe in detail the common techniques associated with semiconductor device manufacturing. Furthermore, the various operations and processes described herein can be incorporated into more comprehensive processes or techniques with additional functionalities not described in detail herein. Specifically, various processes in semiconductor device manufacturing are well known; therefore, for the sake of brevity, many common processes will be mentioned only briefly or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon a full reading of this disclosure that the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include a varying number of components, and a single component shown in the figures may represent multiple components.

[0117] This document presents embodiments of semiconductor devices and methods for manufacturing such devices. The methods described herein can be readily integrated into current process flows. Furthermore, the methods described herein relate to the formation of insulating structures, such as a continuous polysilicon on diffusion edge (CPODE) structure or a continuous metal on diffusion edge (CMODE) structure, dividing the fins into two and / or dividing the gate into two. In some embodiments, a selected portion of the fin structure is removed and replaced with an insulating material.

[0118] In the embodiments described herein, a CMODE process method is provided, in which insulating features are formed after the metal gate is formed, or a CPODE process method is provided, in which insulating features are formed before the metal gate is formed. In some embodiments, dielectric structures such as cut-poly gate dielectric structures, cut-metal gate dielectric structures, or dummy fin dielectric structures are formed on the sidewalls of cavities etched during the CMODE or CPODE process. Therefore, insulating features are formed to contact the dielectric structures. In other embodiments, insulating features directly contact the retained gate segments.

[0119] The embodiments disclosed herein provide advantages over the prior art. Although it should be understood that other embodiments may provide different advantages, not all advantages are necessarily discussed herein, and not all embodiments need to have specific advantages.

[0120] Figure 1 A top-down schematic layout diagram of a semiconductor device or structure 100, such as a FinFET semiconductor device, is shown according to some embodiments. In other embodiments, a gate-all-around (GAA) semiconductor device may be formed as structure 100. Figure 1 As shown, structure 100 may include a semiconductor substrate 99, a semiconductor structure such as a fin 200 formed from the substrate 99, and a gate 300 formed above the fin 200. Figure 1 The dielectric structure 400 that cuts through the two gates 300 is also shown, as well as the insulating feature 500 that divides a fin 200 into two that intersects with and is adjacent to the dielectric structure 400 and a gate 300.

[0121] As shown in the figure, fins 200 extend along the transverse X direction and are spaced apart from each other in the transverse Y direction perpendicular to the transverse X direction. Furthermore, gates 300 extend along the transverse Y direction and are spaced apart from each other in the transverse X direction perpendicular to the transverse Y direction. Additionally, dielectric structures 400 extend along the transverse X direction and are spaced apart from each other in the transverse Y direction perpendicular to the transverse X direction. As shown in the figure, insulating features 500 extend in the transverse Y direction.

[0122] It should be noted that structure 100 may include any appropriate number of fins 200 to form a desired semiconductor device. Furthermore, any appropriate number of gates 300, dielectric structures 400, and insulating features 500 may be formed to form the desired semiconductor device 100.

[0123] Figure 2 It is shown that, according to some embodiments, such as Figure 1 A schematic top-to-bottom layout of a portion 100' of a semiconductor structure 100. Figure 2 A schematic diagram of portion 100' of structure 100 shows an insulating feature 500 extending along the Y direction from a first wire endpoint 511 to a second wire endpoint 512. Each first wire endpoint 511 and second wire endpoint 512 abuts a separate dielectric structure 400. Specifically, the first wire endpoint 511 abuts a first vertically extending dielectric structure 401, and the second wire endpoint 512 abuts a second vertically extending dielectric structure 402. In some embodiments, each first wire endpoint 511 and second wire endpoint 512 extends along the X direction. As shown, the insulating feature 500 has a first sidewall 521 and a second sidewall 522 each extending along the Y direction. The first vertically extending dielectric structure 401 and the second vertically extending dielectric structure 402 extend along the X direction and are spaced apart from each other in the Y direction.

[0124] An insulating feature 500 is located between the first gate 301 and the second gate 302. Each of the first gate 301 and the second gate 302 extends between the first vertically extending dielectric structure 401 and the second vertically extending dielectric structure 402 and is interrupted by the first vertically extending dielectric structure 401 and the second vertically extending dielectric structure 402.

[0125] As further shown, source / drain contacts 600 are formed in lateral adjacent insulating features 500. Specifically, a first source / drain contact 601 is located between a first gate 301 and insulating feature 500, and a second source / drain contact 602 is located between a second gate 302 and insulating feature 500.

[0126] Each source / drain contact 600 extends along the Y direction and terminates at a first contact endpoint 611 and a second contact endpoint 612. Further, the first contact endpoint 611 defines a first vertical plane 6110, which is perpendicular to the plane defined by the X and Y axes. As shown, the first vertical plane 6110 intersects the insulating feature 500. Similarly, the second contact endpoint 612 defines a second vertical plane 6120, which is perpendicular to the plane defined by the X and Y axes. As shown, the second vertical plane 6120 intersects the insulating feature 500. More specifically, each of the first vertical plane 6110 and the second vertical plane 6120 intersects with a first sidewall 521 and a second sidewall 522 of the insulating feature 500.

[0127] In some embodiments, the first vertical plane 6110 is spaced apart from the first line endpoint 511 by a selected distance D1 in the Y direction, and the second vertical plane 6120 is spaced apart from the second line endpoint 512 by a selected distance D2 in the Y direction. Not limited to the described dimensions, in some embodiments, each selected distance D1 and D2 may independently be at least 0.1 nm, for example at least 0.2, at least 0.3, at least 0.4, at least 0.5, at least 0.6, at least 0.7, at least 0.8, at least 0.9, at least 1, at least 1.1, at least 1.2, at least 1.3, at least 1.4, at least 1.5, at least 1.6, at least 1.7, at least 1.8, at least 1.9, at least 2, at least 2.25, at least 2.5, at least 2.75, at least 3, at least 3.25, at least 3.5, at least 3.75, at least 4, at least 4.25, at least 4.5, at least 4.75, at least 5, at least 6, at least 7, at least 8, at least 9, at least 10, or at least 12 nm. Furthermore, not limited to the described dimensions, in some embodiments, each selected distance D1 and D2 may be independently up to 0.1 nm, such as up to 0.2, up to 0.3, up to 0.4, up to 0.5, up to 0.6, up to 0.7, up to 0.8, up to 0.9, up to 1, up to 1.1, up to 1.2, up to 1.3, up to 1.4, up to 1.5, up to 1.6, up to 1.7, up to 1.8, up to 1.9, up to 2, up to 2.25, up to 2.5, up to 2.75, up to 3, up to 3.25, up to 3.5, up to 3.75, up to 4, up to 4.25, up to 4.5, up to 4.75, up to 5, up to 6, up to 7, up to 8, up to 9, up to 10, up to 12, or up to 15 nm. The values ​​of the selected distances D1 and D2 can depend on the technology node, generation, and / or application.

[0128] Generally, increasing the distance D1 or D2 improves the prevention of current leakage around the insulating feature 500. In some embodiments, distances D1 and D2 may be selected such that the first wire endpoint 511 and the second wire endpoint 512 are located at the midpoints of the first vertically extending dielectric structure 401 and the second vertically extending dielectric structure 402, respectively. Therefore, in such embodiments, each distance D1 and D2 should be greater than half the width (in the Y direction) of the corresponding dielectric structure 400. In some embodiments, each distance D1 and D2 is greater than the distance (in the Y direction) from the first vertical plane 6110 or the second vertical plane 6120 to the corresponding dielectric structure 400.

[0129] Figures 3 to 30 It shows that according to Figure 31 The method shown is a portion 100' of the semiconductor structure 100 at various manufacturing stages.

[0130] like Figure 31 As shown, method 1000 can begin in operation S1010 to form semiconductor structure 100, such as Figures 3 to 5 As shown. Figure 3 This is a perspective view of semiconductor structure 100. Figure 4 This is an X-section cross-sectional view along fin 200, and Figure 5 This is a Y-section cross-sectional view along gate 300. It is worth noting that the perspective view presented herein may have certain features removed to allow viewing of other internal features or for other purposes of providing clarity. While some embodiments are described with respect to the formation of a GAA structure, the embodiments herein are not limited to such structures. For example, semiconductor structure 100 may be provided as a FinFET device.

[0131] Structure 100 can be formed according to conventional semiconductor processes. For example, operation S1010 may include providing a substrate 99. In some embodiments, substrate 99 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 99 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. As is known in the art, substrate 99 may include various doping configurations depending on design requirements. For example, different doping profiles (e.g., p-wells, n-wells) may be formed in regions on substrate 99 designed for different device types (e.g., n-type field-effect transistors (NFETs), p-type field-effect transistors (PFETs)). Suitable doping may include doping ion implantation and / or diffusion processes, such as boron (B) for p-wells and phosphorus (P) for n-wells. In some embodiments, substrate 99 includes a single-crystal semiconductor layer at least on its surface portion. Substrate 99 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 99 may comprise compound semiconductors and / or alloy semiconductors. In the illustrated embodiment, substrate 99 is made of crystalline Si.

[0132] Operation S1010 may include forming one or more epitaxial layers over substrate 99. In some embodiments, an epitaxial stack is formed over substrate 99. The epitaxial stack includes a first epitaxial layer of a first component with a second epitaxial layer of a second component interposed therein. The first and second components may be different. Possible embodiments include those providing a first component and a second component with different oxidation rates and / or etch selectivity. In an embodiment, the first epitaxial layer is silicon-germanium (SiGe) and the second epitaxial layer is silicon. In embodiments where the first epitaxial layer comprises SiGe and the second epitaxial layer comprises silicon, the silicon oxidation rate is less than the SiGe oxidation rate.

[0133] In some embodiments, operation S1010 includes masking and patterning the epitaxial stack to form semiconductor fins 200, such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. Additionally, a portion of the substrate 99 may be patterned such that a mesa portion of the substrate 99 forms the lower portion of the fins 200. In various embodiments, each fin 200 includes an upper portion of staggered epitaxial layers and a bottom portion formed by the etched substrate 99. The fins 200 project upward from the substrate 99 in the Z direction, extend longitudinally in the X direction, and are spaced apart in the Y direction. The fins 200 may have the same width or different widths. In addition to forming the fins 200, operation S1010 may include forming dummy fins 250.

[0134] Operation S1010 may also include forming a shallow trench isolation (STI) feature 240 in a trench adjacent to each fin 200. Furthermore, operation S1010 may include forming a sacrificial (dummy) gate structure. The sacrificial gate structure protrudes upward from the substrate 99 in the Z direction, extends longitudinally in the Y direction, and is spaced apart along the X direction.

[0135] A sacrificial gate structure is formed over a portion of the fin 200 that will become a channel region. The sacrificial gate structure may extend over some adjacent fins 200. The sacrificial gate structure is directly over and defines the channel region of the semiconductor device to be formed. Each sacrificial gate structure includes a sacrificial gate dielectric and a sacrificial gate electrode above the sacrificial gate dielectric. The sacrificial gate structure can be formed by first depositing a sacrificial gate dielectric layer over the fin 200 in a blanket manner. Then, a sacrificial gate electrode layer is deposited over the sacrificial gate dielectric layer and the fin 200 in a blanket manner. The sacrificial gate electrode layer includes silicon oxide, silicon nitride, or a combination thereof. The sacrificial gate electrode layer includes silicon, such as polycrystalline silicon or amorphous silicon. The sacrificial gate dielectric layer and the sacrificial gate electrode layer can be deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. These layers are then masked and patterned into a sacrificial gate structure. After the sacrificial gate structure is formed, each fin 200 is partially exposed or exposed on opposite sides of the sacrificial gate structure, thereby defining a source / drain (S / D) region. In this disclosure, the “source / drain region” or “source / drain feature” may be referred to as the source or drain individually or as a whole, depending on the context.

[0136] Operation S1010 may further include forming sidewall spacers on the sidewalls of the sacrificial gate structure and the sidewalls of the fin 200 by depositing spacer material, followed by etching. The sidewall spacers may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each spacer may include multiple layers, such as a liner and a primary spacer layer on the liner. For example, the sidewall spacers can be formed by depositing spacer material comprising a pad material layer and a dielectric material layer over the sacrificial gate structure using processes such as subatmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes.

[0137] Operation S1010 may include etching-back (e.g., anisotropically) to expose and remove portions of fin 200 adjacent to and not covered by the sacrificial gate structure (e.g., source / drain regions). In some embodiments, the etching-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof.

[0138] Operation S1010 may further include forming internal spacers by laterally etching the first epitaxial layer. In an example embodiment, a SiGe etch-back process is performed to laterally recess the first epitaxial layer. As a result, a pocket is formed. Material for forming the internal spacers is then deposited. For example, the internal spacers may be formed from silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxide carbide, silicon carbonitride, and / or other suitable dielectric materials. The internal spacers may be formed by ALD or any other suitable method. After depositing the material forming the internal spacers, the material may be trimmed from the sidewalls of the second epitaxial layer.

[0139] Operation S1010 further includes forming source / drain features 650. In an example embodiment, the source / drain features 650 are formed by epitaxial growth. In an example embodiment, the source / drain features 650 are strained source / drain features 650. In some embodiments, the source / drain features 650 may include n-type epitaxial material source / drain features and p-type epitaxial material source / drain features. For an n-type channel FET, the epitaxial material may include one or more layers of Si, SiP, SiC, and SiCP, or for a p-type channel FET, the epitaxial material may include one or more layers of Si, SiGe, and Ge. For a p-type channel FET, the source / drain may also contain boron (B). The source / drain epitaxial layers may be formed by epitaxial growth methods using CVD, ALD, or molecular beam epitaxy (MBE).

[0140] Operation S1010 may further include forming a dielectric layer 660 over the source / drain feature 650. Specifically, a dielectric pad may be formed over the source / drain feature 650 and along the sidewalls of the spacers (not shown in the figure). Further, a dielectric material may be formed over the pad on the source / drain feature 650. In an example embodiment, the dielectric material is a first interlayer dielectric layer (ILD). The dielectric material may be silicon oxide or other suitable dielectric materials. In some embodiments, the ILD dielectric and the sidewall spacers are the same material. In some embodiments, the dielectric pad is silicon nitride or another suitable material. The dielectric pad and the material form the ILD layer 660. Furthermore, operation S1010 may form dielectric caps 670 over the ILD layer 660. For example, the dielectric caps 670 may be formed of silicon nitride and may protect the ILD layer 660 during subsequent processes.

[0141] Operation S1010 may further include performing a replacement gate process that includes opening and removing the sacrificial gate structure. Specifically, a chemical mechanical planarization (CMP) process may be performed to remove the capping layer and expose the sacrificial gate structure. The sacrificial gate structure is then removed to form a gate cavity defined by sidewall spacers and located between the ILD layers 660.

[0142] In operation S1010, the interposer of the first epitaxial layer can be removed. As a result, gaps are formed between the second epitaxial layers. In this way, the second epitaxial layers are formed as vertically spaced semiconductor nanosheets.

[0143] The gate replacement process is then completed by forming a gate 300 in the gate cavity. In some embodiments, the metal gate replacement process includes forming a gate dielectric layer in the gate cavity and the gap beneath the nanosheet, and forming a gate electrode material over the gate dielectric layer to fill the gate cavity and the gap. An example gate dielectric layer is conformally deposited. The gate dielectric can be formed on the semiconductor nanosheet, and the gate electrode material can be formed on the gate dielectric layer. Thus, each semiconductor nanosheet is encapsulated in the gate dielectric and surrounded by the gate electrode material. In some embodiments, a Si-based interface layer, such as silicon oxide or hafnium silicate, is formed between the semiconductor nanosheet and the gate dielectric. According to some embodiments, the gate dielectric layer is formed of silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer is a high-k dielectric material, and in these embodiments, the gate dielectric layer may have a k value greater than about 7.0, and may include metal oxides or silicates such as Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer may include molecular-beam deposition (MBD), ALD, PECVD, etc.

[0144] Gate electrode material is deposited over the gate dielectric layer and fills the reserved portion of the gate cavity. The gate electrode material can be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiples thereof. For example, any number of work function tuning layers can be deposited.

[0145] The gate replacement process includes removing excess portions of the gate dielectric layer and gate electrode material located above the top surface of the ILD structure 660. For example, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer and gate electrode material. The remaining portions of the gate dielectric layer and gate electrode material thus form the replacement metal gate structure 300 of the resulting semiconductor device 100. The gate dielectric layer and gate electrode material may be collectively referred to as a “gate,” “gate stack,” or “gate structure.” Each gate structure 300 may extend along the sidewalls of the channel region of the fin 200.

[0146] Operation S1010 may further include forming a gate capping layer 350 over the gate 300. The gate capping layer 350 can be formed by first depositing a dielectric material over the gate 300. In some embodiments, the gate capping layer 350 is formed using a dielectric material such as amorphous silicon, silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), etc. The gate capping layer 350 can be formed using a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), combinations thereof, etc. However, any suitable material and deposition process can be used. After deposition, a planarization process such as chemical mechanical polishing can be used to planarize the gate capping layer 350.

[0147] According to some embodiments, operation S1010 may include forming an opening 390 in the gate 300. After the gate capping layer 350 has been planarized, a mask may be deposited and patterned to expose the material beneath the gate capping layer 350 and the gate 300 at the desired location where the dielectric structure 400 will be formed. For example, as shown, a dummy fin 250 may be aligned with the opening 390.

[0148] After patterning the mask, the underlying material is etched to form openings 390. In the etching process, an anisotropic etching process is used to etch the material of the gate cap layer 350 and the gate 300. The openings 390 may cut through one or more gates 300. According to some embodiments, two openings 390 are formed to cut through two adjacent gates 300 and on opposite sides of one or more fins 200.

[0149] According to some embodiments, operation S1010 may further include forming a dielectric structure 400, such as dielectric pillars 400, in the opening 390. After forming the opening 390, the dielectric pillars 400 are formed by first depositing dielectric material to fill and overfill the opening 390. According to some embodiments, any dielectric material and a deposition process suitable for forming the gate capping layer 350 are used to form the dielectric material. In some embodiments, the dielectric material is the same as the dielectric material used to form the gate capping layer 350, although the dielectric material may be different. For example, silicon nitride (SiN) may be used in a deposition process such as atomic layer deposition (ALD) to form the dielectric structure 400. However, any suitable dielectric material and deposition process may be used. According to some embodiments, the dielectric pillars 400...

[0150] like Figure 5 As shown, dielectric pillars 400 extend into the dummy fin 250 and divide the relatively long gate 300 into a plurality of relatively short gate segments 310. Dielectric pillars 400 can be used to isolate the gate segments 310 from each other. For example, selected gate segment 311 is separated from adjacent gate segment 312 via a first dielectric pillar 401 and a second dielectric pillar 402. Similarly, the gate cap layer 350 is divided into segments 351 and 352 via dielectric pillars 400. Excess dielectric material 499 of the dielectric pillars 400 outside the opening 390 can be retained and used as a masking layer during subsequent etching.

[0151] Therefore, as Figures 3 to 5 As shown, operation S1010 forms structure 100, which includes a substrate 99, a fin 200 covering the substrate 99, a gate segment 311 covering the fin 200 and extending along the Y direction from a first endpoint 321 to a second endpoint 322, a dielectric layer segment 351 covering the gate segment 311 and contacting the gate segment 311 at an interface height H1 above the substrate 99 and defining a horizontal gate top plane, a first vertically extending dielectric structure 401 having an inner surface or sidewall 421 adjacent to the first endpoint 321 of the gate segment 311, and a second vertically extending dielectric structure 402 having an inner surface or sidewall 422 adjacent to the second endpoint 322 of the gate segment 311. As shown, the inner surfaces 421 and 422 are inclined or parallel to each other from the bottom endpoint 423 of each dielectric structure 400 to the top endpoint 424 of each dielectric structure 400.

[0152] As shown, the source / drain feature 650 is spaced apart from the gate segment 310 in the X direction, the interlayer dielectric (ILD) structure 660 is located above the source / drain feature 650, and the dielectric cap 670 is located above the ILD structure 660. As shown, an ILD structure 660 can be formed having sidewall pads 665 along the sides of each ILD structure 660. Furthermore, although not shown, the sidewall pads 665 may be located above the top surface of the source / drain feature 650.

[0153] like Figure 31 As shown, method 1000 includes performing an etching process at operation S1020 to remove dielectric layer segment 351. Figures 6 to 8 The initial structure 100 during operation S1020 is shown. Figure 6 This is a perspective view of semiconductor structure 100. Figure 7 This is an X-section cross-sectional view along fin 200, and Figure 8 This is a Y-section cross-sectional view along gate 300.

[0154] Cross-reference Figures 6 to 8 Operation S1020 can be included in Figures 3 to 5A carbon substrate layer 701, an oxide-based intermediate layer 702, and an extreme ultraviolet (EUV) photoresist top layer 703 are formed on top of the structure 100. The etching process may include performing EUV photoresist exposure technology to pattern the photoresist top layer 703 to form an opening 710. As shown, the opening 710 has a width W1 in the X direction and a width W2 in the Y direction. Widths W1 and W2 can be selected to remove a single gate segment 311 from the single gate 300.

[0155] Operation S1020 further includes performing an etching process through opening 710 to remove dielectric layer segment 351, such as Figures 9 to 11 As shown. Figure 9 This is a perspective view of semiconductor structure 100. Figure 10 This is an X-section cross-sectional view along fin 200, and Figure 11 This is a Y-section cross-sectional view along gate 300.

[0156] like Figures 9 to 11 As shown, the etching process removes all dielectric layer segments 351 and lands on the gate segment 311. Thus, opening 380 is formed.

[0157] In some embodiments, an etching process etches the inner surface 421 of the first vertically extending dielectric structure 401 and the inner surface 422 of the second vertically extending dielectric structure 402, such that a minimum distance D1 in the Y direction is established between the first vertically extending dielectric structure 401 and the second vertically extending dielectric structure 402 at an interface height H1. Specifically, at the bottom endpoint 423, dielectric structures 401 and 402 are spaced apart from each other in the Y direction by a distance greater than the minimum distance D1. As dielectric structures 401 and 402 extend vertically upward to the interface height H1, the inner surfaces 421 and 422 of dielectric structures 401 and 402 converge toward each other. Then, as dielectric structures 401 and 402 extend vertically upward from the interface height H1 toward the top endpoint 424, the inner surfaces 421 and 422 of dielectric structures 401 and 402 either move vertically upward or diverge from each other. As a result, the distance in the Y direction between the inner surfaces 421 and 422 at the top endpoint 424 is equal to or greater than the minimum distance D1.

[0158] As shown in the figure, inner sidewall 421 forms an interior angle A1 with the top plane of the horizontal gate at interface height H1, and inner sidewall 422 forms an interior angle A2 with the top plane of the horizontal gate at interface height H1. In some embodiments, each interior angle A1 and A2 is independently at least 90 degrees.

[0159] In some embodiments, each interior angle A1 and A2 is 90 degrees, and the inner surfaces 421 and 422 are perpendicular as the dielectric structures 401 and 402 extend upward from the interface height H1. In other embodiments, at least one of angles A1 and A2 is greater than 90 degrees, and the distance between the inner surfaces 421 and 422 of the dielectric structures 401 and 402 increases as the dielectric structures 401 and 402 extend upward from the interface height H1. In some embodiments, each of angles A1 and A2 is greater than 90 degrees, and the inner surfaces 421 and 422 diverge from each other as the dielectric structures 401 and 402 extend upward from the interface height H1.

[0160] refer to Figure 31 Method 1000 can continue in operation S1030, removing the gate segment 311 and the fin 200 located below the gate segment 311 to form a cavity 280, as shown. Figures 12 to 14 As shown. Figure 12 This is a perspective view of semiconductor structure 100. Figure 13 This is an X-section cross-sectional view along fin 200, and Figure 14 This is a Y-section cross-sectional view along gate 300.

[0161] like Figures 12 to 14 As shown, removing gate segment 311 forms cavity 280 and includes selectively removing gate segment 311, including gate material and gate dielectric. Gate segment 311 can be removed by dry or wet etching. In some embodiments, this process can remove all gate segments 311 between dielectric structures 401 and 402 and above STI 240. Furthermore, the etching process can remove nanostructures, etch sidewall spacers, and recess selected fins 200 into substrate 99 to form cavity protrusions 190 extending downward from cavity 280 through STI 240 and into substrate 99.

[0162] As a result, the cavity 280 is defined or defined by the substrate 99, STI 240, dummy fins 250, and dielectric structure 400. In some embodiments, the etching process is plasma etching and may be followed by a wet clean process.

[0163] Although Figure 13 This illustrates that all gate segments 311 are removed; in some embodiments, the etching process removes only substantially all gate segments 311. For example, a small retained portion of the gate segment 311 may exist at location 679 on the sidewall 678, location 679 being below a portion of the sidewall 678 formed by the dielectric cap 670, as shown. Figure 13 As shown. If present, the reserved portion of the gate segment 311 has a lateral thickness of less than 3 nanometers (nm) in the X direction, for example, less than 2.5, less than 2, less than 1.5, or less than 1 nm.

[0164] In addition, although Figure 13 The diagram shows a location 679 on the sidewall 678 where the sidewall liner 665 is not present. Location 679 is located below a portion of the sidewall 678 formed by the dielectric top cap 670. In some embodiments, a small retained portion of the sidewall liner 665 may be present at location 679. If present, the retained portion of the sidewall liner 665 at location 679 in the X direction has a lateral thickness of less than 3 nanometers (nm), for example, less than 2.5, less than 2, less than 1.5, or less than 1 nm.

[0165] In some embodiments, the sidewall liner 665 remains intact and extends upward from the source / drain feature 650 to the dielectric cap 670, such that no portion of the sidewall 678 of the opening 280 is formed by the ILD structure 660. In other words, the sidewall liner 665 separates the ILD structure 660 from the opening 280.

[0166] like Figure 31 As shown, method 1000 can continue in operation S1040, forming an insulating feature 500 in cavity 280, such as... Figure 15 and Figure 16 As shown. Figure 15 This is an X-section cross-sectional view along fin 200, and Figure 16 This is a Y-section cross-sectional view along gate 300.

[0167] like Figure 15 and Figure 16 As shown, forming an insulating feature 500 in cavity 280 may include depositing an insulating material 590 in cavity 280. The insulating material 590 may include a liner and filler material lining cavity 280. In some embodiments, the insulating material 590 may include silicon oxide, oxide nitride, a dielectric material with a dielectric constant (k) lower than silicon oxide (hence referred to as a low-k dielectric layer), and / or other suitable dielectric material layers. In some embodiments, the insulating material 590 may include a filler material comprising silicon nitride, oxide nitride, and / or other suitable dielectric material layers. In some embodiments, a refill process may be used to deposit the filler material. In one example, the dielectric material may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), spin-on coating, or other suitable techniques. As shown, the dielectric material 590 may be first formed as a blanket layer and may form an overburden portion 599.

[0168] In operation S1040, forming the insulating feature 500 may further include performing a planarization process to remove excess portions 599 of the insulating material 590, such as Figure 17 and Figure 18 As shown. Figure 17 This is an X-section cross-sectional view along fin 200. Figure 18 This is a Y-section cross-sectional view along gate 300.

[0169] like Figure 17 and Figure 18 As shown, the planarization process for removing excess portion 599 of insulating material 590 can remove excess dielectric material 499 from above the retained dielectric layer section 352 located above the retained gate section 312. As a result, as... Figure 18 As shown, the top surface 109 of structure 100 is defined and formed by insulating feature 500, dielectric structure 400, and retained dielectric layer segment 352. As illustrated, no portion of the dielectric layer segment 351 exists at the top surface 109 (e.g., Figure 8 (As shown).

[0170] Figure 31 Method 1000 is shown to continue in operation S1050, removing the retained gate cap layer 350, including the retained dielectric layer segment 352. As a result, the retained gate 300 and the retained gate segment 312 are exposed. Figure 19 and Figure 20 The structure 100 after the execution of operation S1050 is shown. Figure 19 This is an X-section cross-sectional view along fin 200. Figure 20 This is a Y-section cross-sectional view along gate 300.

[0171] like Figure 20 As shown, after the retained dielectric layer segment 352 is removed, the insulating feature 500 and the vertically extending dielectric structure 400 remain in direct contact at the top surface 109.

[0172] like Figure 31 As shown, method 1000 can be further continued in operation S1060 by depositing additional dielectric material 800 on top of structure 100. Figure 21 and Figure 22 This manufacturing stage is shown. Figure 21 This is an X-section cross-sectional view along fin 200. Figure 22 This is a Y-section cross-sectional view along gate 300.

[0173] In some embodiments, the additional dielectric material 800 is silicon nitride.

[0174] Method 1000 can continue in operation S1070, and the flattened structure 100 is as follows: Figure 31 , Figure 23 and Figure 24 As shown. Figure 23 This is an X-section cross-sectional view along fin 200. Figure 24This is a Y-section cross-sectional view along the gate 300. As shown, the planarization structure 100 may include a dielectric cap 670 removed from above the ILD structure 660. As shown, a retained portion of the additional dielectric material 800 remains above the retained gate 300, including a retained gate segment 312.

[0175] Method 1000 can continue in operation S1080, forming a conductive contact 600 that contacts the source / drain feature 650, such as... Figure 31 As shown.

[0176] Various patterning methods can be used to form conductive contacts, such as metals, on source / drain features. For example, one method may include depositing a silicon nitride-based pad over an ILD structure 660 and depositing an additional interlayer dielectric (ILD) over that pad. Patterning and etching processes can then be performed to remove the additional ILD, the silicon nitride-based pad, and exposed areas of the ILD structure 660 to expose selected source / drain features 650. A deposition process is then performed to form conductive contacts 600. For example, a pad selected to prevent metal migration to adjacent dielectric material may be deposited first, followed by a metal filler to fill the trench. A CMP process can then be used to planarize the surface. The embodiments described herein are not limited to any particular process for forming conductive contacts.

[0177] In the illustrated embodiment, the initial phase of operation S1080 is in Figure 25 and Figure 26 As shown. Figure 25 This is an X-section cross-sectional view along fin 200. Figure 26 This is a Y-section cross-sectional view along gate 300.

[0178] Operation S1080 may include removing the ILD structure 660, such as Figure 25 and Figure 26 As shown in the figure, removing the ILD structure 660 forms a cavity 669 above the source / drain feature 650. The cavity 669 may be adjacent to the insulating feature 500, such as... Figure 25 As shown.

[0179] Operation S1080 may further include depositing conductive material 610 over structure 100 and contacting source / drain features 650, such as Figure 27 and Figure 28 As shown. Figure 27 This is an X-section cross-sectional view along fin 200. Figure 28 This is a Y-section cross-sectional view along gate 300. For example, metal can be deposited.

[0180] like Figure 27 and Figure 28As shown, operation S1080 may include forming and patterning a mask 620 over structure 100. The patterned mask 620 exposes source / drain features 650. Next, conductive material 610 is deposited to contact the source / drain features 650. For example, conductive material 610 may fill cavity 669.

[0181] Operation S1080 may further include a planarization structure 100 to define a conductive contact 600 in a cavity 669 above the source / drain feature 650, such as Figure 29 and Figure 30 As shown. Figure 29 This is an X-section cross-sectional view along fin 200. Figure 30 This is a Y-section cross-sectional view along gate 300.

[0182] like Figure 31 As shown, method 1000 can continue further processes in operation S1090. For example, various lithography, patterning, and passivation processes can be performed to form dielectric and metallization layers, as well as to form desired interconnect structures, such as in typical back-end-of-line (BEOL) processes.

[0183] Cross-reference Figure 2 and Figure 29 The insulating feature 500 is located between two conductive contacts 600 (i.e., the first conductive contact 601 and the second conductive contact 602). According to the process provided herein, the first conductive contact 601 and the second conductive contact 602 are completely isolated from each other. Furthermore, the process described herein prevents accidental connection of the first conductive contact 601 and the second conductive contact 602 around the insulating feature 500.

[0184] Cross-reference Figure 2 and Figure 30 At the upper surface 999 of structure 100, insulating feature 500 extends in the Y direction from first wire endpoint 511 to second wire endpoint 512. First wire endpoint 511 contacts first vertically extending dielectric structure 401, and second wire endpoint 512 contacts second vertically extending dielectric structure 402. Furthermore, the upper portion 541 of the first wire endpoint 511 of insulating feature 500 is surrounded by the first vertically extending dielectric structure 401, and the upper portion 542 of the second wire endpoint 512 of insulating feature 500 is surrounded by the second vertically extending dielectric structure 402.

[0185] like Figures 2 to 31The dielectric structure 400 is etched during the removal of gate segments 311. As a result, after the etching process, no gate segments 311 are retained due to the protection of the overhang of the dielectric structure 400. A process that cannot etch the dielectric structure 400 may not be able to remove all gate segments 311 because the ends of gate segments 311 of adjacent dielectric structures 400 can be protected from the etchant by the sloping surface covering the dielectric structure 400. The overhang of the dielectric structure 400 is removed. As used herein, the overhang has an upper width greater than the lower width, such that the vertical anisotropic etching process is blocked by the upper width.

[0186] As described herein, no portion of the gate segment 311 is directly beneath and protected by a portion of the dielectric structure 400. Instead, the dielectric structure 400 is etched such that the inner surfaces 421 and 422 are perpendicular to each other or at an angle away from each other.

[0187] Although Figures 2 to 31 One embodiment is presented for reducing or eliminating leakage current from the first source / drain contact 601 to the adjacent second source / drain contact 602 around the insulating feature 500, but another embodiment is provided.

[0188] Figure 32 A semiconductor structure 100 according to some embodiments is shown (e.g. Figure 1 A schematic top-down layout of a portion 100” of structure 100. In some embodiments, portion 100” may be located at a different position on the same structure 100 as portion 100’.

[0189] exist Figure 32 In the diagram, a portion 100 of structure 100 shows an insulating feature 500 extending along the Y direction from a first wire endpoint 511 to a second wire endpoint 512. In some embodiments, each first wire endpoint 511 and second wire endpoint 512 extends along the X direction. As shown, the insulating feature 500 has a first sidewall 521 and a second sidewall 522 each extending along the Y direction. Figure 32 In the middle, the insulating feature 500 does not adjoin or otherwise contact the dielectric structure 400 in this portion 100 of the structure 100.

[0190] Insulating feature 500 is located between the first gate 301 and the second gate 302. Figure 32 In the structure 100, the first gate 301 and the second gate 302 are not adjacent to or otherwise contact the dielectric structure 400 in this portion of the structure 100.

[0191] As further shown, source / drain contacts 600 are formed in lateral adjacent insulating features 500. Specifically, a first source / drain contact 601 is located between a first gate 301 and insulating feature 500, and a second source / drain contact 602 is located between a second gate 302 and insulating feature 500.

[0192] Each source / drain contact 600 extends along the Y direction and terminates at a first contact endpoint 611 and a second contact endpoint 612. Further, the first contact endpoint 611 defines a first vertical plane 6110, which is perpendicular to the plane defined by the X and Y axes. As shown, the first vertical plane 6110 intersects the insulating feature 500. Similarly, the second contact endpoint 612 defines a second vertical plane 6120, which is perpendicular to the plane defined by the X and Y axes. As shown, the second vertical plane 6120 intersects the insulating feature 500. More specifically, each of the first vertical plane 6110 and the second vertical plane 6120 intersects with a first sidewall 521 and a second sidewall 522 of the insulating feature 500.

[0193] In some embodiments, a first vertical plane 6110 is spaced apart from the first line endpoint 511 by a selected distance D1 in the Y direction, and a second vertical plane 6120 is spaced apart from the second line endpoint 512 by a selected distance D2 in the Y direction. Each selected distance D1 and D2 may independently be at least 0.1 nm, for example at least 0.2, at least 0.3, at least 0.4, at least 0.5, at least 0.6, at least 0.7, at least 0.8, at least 0.9, at least 1, at least 1.1, at least 1.2, at least 1.3, at least 1.4, at least 1.5, at least 1.6, at least 1.7, at least 1.8, at least 1.9, at least 2, at least 2.25, at least 2.5, at least 2.75, at least 3, at least 3.25, at least 3.5, at least 3.75, at least 4, at least 4.25, at least 4.5, at least 4.75, or at least 5 nm. Furthermore, each selected distance D1 and D2 can be independently up to 0.1 nm, such as up to 0.2, up to 0.3, up to 0.4, up to 0.5, up to 0.6, up to 0.7, up to 0.8, up to 0.9, up to 1, up to 1.1, up to 1.2, up to 1.3, up to 1.4, up to 1.5, up to 1.6, up to 1.7, up to 1.8, up to 1.9, up to 2, up to 2.25, up to 2.5, up to 2.75, up to 3, up to 3.25, up to 3.5, up to 3.75, up to 4, up to 4.25, up to 4.5, up to 4.75, or up to 5 nm.

[0194] Generally, increasing the distance D1 or D2 improves the prevention of current leakage around the insulation feature 500. The minimum value of distance D1 or distance D2 can depend on the technology node, generation, and / or application.

[0195] Figures 33 to 60 It shows that according to Figure 61 The method shown is a portion 100 of the semiconductor structure 100 at various manufacturing stages.

[0196] like Figure 61 As shown, method 2000 can begin in operation S2010 to form semiconductor structure 100, such as... Figures 33 to 35 As shown. Figure 33 The semiconductor structure 100 has a perspective view showing that certain features have been removed or made transparent for clarity. Figure 34 This is an X-section cross-sectional view along fin 200, and Figure 35 This is a Y-section cross-sectional view along gate 300.

[0197] Structure 100 can be formed according to conventional semiconductor processes, as described with respect to operation S1010.

[0198] like Figure 35 As shown, there is no dielectric pillar 400 in part 100” of structure 100. The excess dielectric material 499 can be retained and used as a masking layer during subsequent etching.

[0199] Therefore, as Figures 33 to 35 As shown, operation S2010 forms structure 100, which includes a substrate 99, fins 200 covering the substrate 99, and a gate segment 311 covering the fins and extending along the Y direction from a first endpoint 321 to a second endpoint 322. Figure 35 In the process, the gate 300 is not interrupted by the first endpoint 321 and the second endpoint 322, the dielectric layer segment 351 covers the gate segment 311 and contacts the gate segment 311 at the interface height H1 above the substrate 99.

[0200] As shown in the figure, the source / drain feature 650 is separated from the gate segment 310 in the X direction, the interlayer dielectric (ILD) structure 660 is located above the source / drain feature 650, and the dielectric cap 670 is located above the ILD structure 660.

[0201] like Figure 61 As shown, method 2000 includes performing an etching process at operation S2020 to remove dielectric layer segment 351. Figures 36 to 38 The initial structure 100 during operation S2020 is shown. Figure 36 This is a perspective view of semiconductor structure 100. Figure 37 This is an X-section cross-sectional view along fin 200, and Figure 38 This is a Y-section cross-sectional view along gate 300.

[0202] Cross-reference Figures 36 to 38 Operation S2020 can include in Figures 33 to 35 A carbon substrate layer 701, an oxide-based intermediate layer 702, and an extreme ultraviolet (EUV) photoresist top layer 703 are formed on top of the structure 100. The etching process may include performing EUV photoresist exposure technology to pattern the photoresist top layer 703 to form an opening 710. As shown, the opening 710 has a width W1 in the X direction and a width W2 in the Y direction. Widths W1 and W2 can be selected to remove a single gate segment 311 from the single gate 300.

[0203] Operation S2020 further includes performing an etching process through opening 710 to remove dielectric layer segment 351, such as Figures 39 to 41 As shown. Figure 39 This is a perspective view of semiconductor structure 100. Figure 40 This is an X-section cross-sectional view along fin 200, and Figure 41 This is a Y-section cross-sectional view along gate 300.

[0204] like Figures 39 to 41 As shown, the etching process removes all dielectric layer segments 351 and lands on the gate segment 311. Thus, opening 380 is formed.

[0205] refer to Figure 61 Method 2000 can continue in operation S2030, removing the gate segment 311 and the fin 200 located below the gate segment 311 to form a cavity 280, as shown. Figures 42 to 44 As shown. Figure 42 This is a perspective view of semiconductor structure 100. Figure 43 This is an X-section cross-sectional view along fin 200, and Figure 44 This is a Y-section cross-sectional view along gate 300.

[0206] like Figures 42 to 44As shown, removing gate segment 311 forms cavity 280 and includes selectively removing gate segment 311, including gate material and gate dielectric. Gate segment 311 is primarily removed by anisotropic plasma etching, followed by a wet cleaning process to avoid damage near gate segment 312 (unlike method 1000, there are no dielectric pillars in method 2000 to protect the vicinity of gate segment 312). In some embodiments, the anisotropic etching process for removing gate segment 311 can create a substantial recess in STI 240. In some embodiments, this process can remove all gate segments 311 located below dielectric layer segment 351 and above STI 240. Furthermore, the etching process can remove nanostructures, etch sidewall spacers, and recess selected fins 200 into substrate 99 to form cavity protrusion 190 extending downward from cavity 280 through STI 240 and into substrate 99. In some embodiments, a notched etch profile will be obtained due to the different etch rates of the STI 240, the channel material, and the gate segment 311.

[0207] As a result, the cavity 280 is defined or defined by the substrate 99, STI 240, the retained gate segment 312, and the retained dielectric layer segment 352. In some embodiments, the etching process is plasma etching and may be followed by a wet cleaning process.

[0208] Although Figure 43 This illustrates that all gate segments 311 are removed; in some embodiments, the etching process removes only substantially all gate segments 311. For example, a small retained portion of the gate segment 311 may exist at location 679 on the sidewall 678, location 679 being below a portion of the sidewall 678 formed by the dielectric cap 670, as shown. Figure 43 As shown. If present, the reserved portion of the gate segment 311 has a lateral thickness of less than 3 nanometers (nm) in the X direction, for example, less than 2.5, less than 2, less than 1.5, or less than 1 nm.

[0209] In addition, although Figure 43 The diagram shows a location 679 on the sidewall 678 where the sidewall liner 665 is not present. Location 679 is located below a portion of the sidewall 678 formed by the dielectric top cap 670. In some embodiments, a small retained portion of the sidewall liner 665 may be present at location 679. If present, the retained portion of the sidewall liner 665 at location 679 in the X direction has a lateral thickness of less than 3 nanometers (nm), for example, less than 2.5, less than 2, less than 1.5, or less than 1 nm.

[0210] In some embodiments, the sidewall liner 665 remains intact and extends upward from the source / drain feature 650 to the dielectric cap 670, such that no portion of the sidewall 678 of the opening 280 is formed by the ILD structure 660. In other words, the sidewall liner 665 separates the ILD structure 660 from the opening 280.

[0211] like Figure 61 As shown, method 2000 can continue in operation S2040, forming insulating feature 500 in cavity 280, such as Figure 45 and Figure 46 As shown. Figure 45 This is an X-section cross-sectional view along fin 200, and Figure 46 This is a Y-section cross-sectional view along gate 300.

[0212] like Figure 45 and Figure 46 As shown, forming an insulating feature 500 in cavity 280 may include depositing an insulating material 590 in cavity 280. The insulating material 590 may include a liner and filler material lining cavity 280. In some embodiments, the insulating material 590 may include silicon oxide, oxide nitride, a dielectric material with a dielectric constant (k) lower than silicon oxide (hence referred to as a low-k dielectric layer), and / or other suitable dielectric material layers. In some embodiments, the insulating material 590 may include a filler material comprising silicon nitride, oxide nitride, and / or other suitable dielectric material layers. In some embodiments, a refill process may be used to deposit the filler material. In one example, the dielectric material may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, or other suitable techniques. As shown, the dielectric material 590 may first be formed as a blanket layer and may form excess portions 599.

[0213] In operation S2040, forming the insulating feature 500 may further include performing a planarization process to remove excess portions 599 of the insulating material 590, such as Figure 47 and Figure 48 As shown. Figure 47 This is an X-section cross-sectional view along fin 200. Figure 48 This is a Y-section cross-sectional view along gate 300.

[0214] like Figure 47 and Figure 48 As shown, the planarization process for removing excess portion 599 of insulating material 590 can remove excess dielectric material 499 from above the retained dielectric layer section 352 located above the retained gate section 312. As a result, as... Figure 48 As shown, the top surface 109 of structure 100 is defined and formed by insulating features 500 and retained dielectric layer segments 352.

[0215] Figure 61 Method 2000 is shown to continue in operation S2050, removing the retained gate cap layer 350, including the retained dielectric layer segment 352. As a result, the retained gate 300 and the retained gate segment 312 are exposed. Figure 49 and Figure 50 The structure 100 after the execution of operation S2050 is shown. Figure 49 This is an X-section cross-sectional view along fin 200. Figure 50 This is a Y-section cross-sectional view along gate 300.

[0216] like Figure 50 As shown, after the retained dielectric layer segment 352 is removed, the insulating feature 500 and the retained gate segment 312 remain in direct contact.

[0217] like Figure 61 As shown, method 2000 can be further continued in operation S2060 by depositing additional dielectric material 800 on top of structure 100. Figure 51 and Figure 52 This manufacturing stage is shown. Figure 51 This is an X-section cross-sectional view along fin 200. Figure 52 This is a Y-section cross-sectional view along gate 300.

[0218] In some embodiments, the additional dielectric material 800 is silicon nitride.

[0219] Method 2000 can continue in operation S2070, flattening structure 100 as follows Figure 61 , Figure 53 and Figure 54 As shown. Figure 53 This is an X-section cross-sectional view along fin 200. Figure 54 This is a Y-section cross-sectional view along the gate 300. As shown, the planarization structure 100 may include a dielectric cap 670 removed from above the ILD structure 660. As shown, a retained portion of the additional dielectric material 800 remains above the retained gate 300, including a retained gate segment 312.

[0220] Method 2000 can continue in operation S2080 to form a conductive contact 600 that contacts the source / drain feature 650.

[0221] Various patterning methods can be used to form conductive contacts, such as metals, on source / drain features. For example, one method may include depositing a silicon nitride-based pad over an ILD structure 660 and depositing an additional interlayer dielectric (ILD) over that pad. Patterning and etching processes can then be performed to remove the additional ILD, the silicon nitride-based pad, and exposed areas of the ILD structure 660 to expose selected source / drain features 650. A deposition process is then performed to form conductive contacts 600. For example, a pad selected to prevent metal migration to adjacent dielectric material may be deposited first, followed by a metal filler to fill the trench. A CMP process can then be used to planarize the surface. The embodiments described herein are not limited to any particular process for forming conductive contacts.

[0222] In the illustrated embodiment, the initial phase of operation S2080 is in Figure 55 and Figure 56 As shown. Figure 55 This is an X-section cross-sectional view along fin 200. Figure 56 This is a Y-section cross-sectional view along gate 300.

[0223] Operation S2080 may include removing ILD structure 660, such as Figure 55 and Figure 56 As shown in the figure, removing the ILD structure 660 forms a cavity 669 above the source / drain feature 650. The cavity 669 may be adjacent to the insulating feature 500, such as... Figure 55 As shown.

[0224] Operation S2080 may further include depositing conductive material 610 over structure 100 and contacting source / drain features 650, such as Figure 57 and Figure 58 As shown. Figure 57 This is an X-section cross-sectional view along fin 200. Figure 58 This is a Y-section cross-sectional view along gate 300. For example, metal can be deposited.

[0225] like Figure 57 and Figure 58 As shown, operation S2080 may include forming and patterning a mask 620 over structure 100. The patterned mask 620 exposes source / drain features 650. Next, conductive material 610 is deposited to contact the source / drain features 650. For example, conductive material 610 may fill cavity 669.

[0226] Operation S2080 may further include a planarization structure 100 to define a conductive contact 600 in a cavity 669 above the source / drain feature 650, such as Figure 59 and Figure 60 As shown. Figure 59This is an X-section cross-sectional view along fin 200. Figure 60 This is a Y-section cross-sectional view along gate 300.

[0227] like Figure 61 As shown, method 2000 can continue with further processes in operation S2090. For example, various lithography, patterning, and passivation processes can be performed to form dielectric and metallization layers, as well as to form desired interconnect structures, such as in typical back-end process (BEOL) processes.

[0228] Cross-reference Figure 32 and Figure 59 The insulating feature 500 is located between two conductive contacts 600 (i.e., the first conductive contact 601 and the second conductive contact 602). According to the process provided herein, the first conductive contact 601 and the second conductive contact 602 are completely isolated from each other. Furthermore, the process described herein prevents accidental connection of the first conductive contact 601 and the second conductive contact 602 around the insulating feature 500.

[0229] Cross-reference Figure 32 and Figure 60 At the upper surface 999 of structure 100, an insulating feature 500 extends in the Y direction from a first wire endpoint 511 to a second wire endpoint 512. The first wire endpoint 511 contacts the dielectric material 800, and the second wire endpoint 512 contacts the dielectric material 800. Furthermore, the upper portion 541 of the first wire endpoint 511 of the insulating feature 500 is surrounded by the dielectric material 800, and the upper portion 542 of the second wire endpoint 512 of the insulating feature 500 is also surrounded by the dielectric material 800.

[0230] like Figures 32 to 61 The first wire endpoint 511 and the second wire endpoint 512 are located away from the first source / drain contact 601 and the second source / drain contact 602 to avoid leakage from the first source / drain contact 601 to the adjacent second source / drain contact 602 around the insulating feature 500.

[0231] Figure 62 Is Figure 38 A focused view of the manufacturing stage of Method 2000, according to one embodiment, the material to be etched above STI 240 is indicated by outline 962. Figure 62 This is a Y-section cross-sectional view along gate 300.

[0232] Figure 63 Is Figure 38 A focused view of the manufacturing stage of Method 2000, according to another embodiment, the material to be etched above STI 240 is indicated by outline 963. Figure 63 This is a Y-section cross-sectional view along gate 300.

[0233] Cross-reference Figure 62 and Figure 63 As can be seen, since method 2000 does not include forming the CMODE / CPODE insulating feature 500 adjacent to the dielectric structure 400, method 2000 is not limited to using the minimum light shield opening width W2 (in the Y direction), which is limited by the position of the dielectric structure 400. Instead, the width W2 can be reduced to remove only selected fins, such as... Figure 62 A larger width W2 can also be used, such as... Figure 63 As expected.

[0234] Figure 64 It is a transmission electron microscope (TEM) image of a portion 100' of the semiconductor device 100 formed according to method 1000. Figure 64 The interior angles A1 and A2 of the inner sidewalls 421 and 422 at the top plane of the gate at interface height H1 are shown. Angles A1 and A2 can be determined using TEM analysis.

[0235] In some embodiments, each angle A1 and A2 is independently 90 degrees or greater. For example, either or both angles may be at least 90.5, at least 91, at least 91.5, at least 92, at least 92.5, at least 93, at least 93.5, at least 94, at least 94.5, at least 95, at least 95.5, at least 96, at least 96.5, at least 97, at least 97.5, at least 98, at least 98.5, at least 99, at least 99.5, at least 100, or at least 100.5 degrees. In addition, any two or any angles may be at most 90.5, at most 91, at most 91.5, at most 92, at most 92.5, at most 93, at most 93.5, at most 94, at most 94.5, at most 95, at most 95.5, at most 96, at most 96.5, at most 97, at most 97.5, at most 98, at most 98.5, at most 99, at most 99.5, at most 100 degrees or at most 100.5 degrees.

[0236] When angle A1 or angle A2 is at least 90 degrees, no portion of gate 300 (i.e., a portion of the selected gate segment 311) is shielded by the dielectric structure or directly beneath the dielectric structure 400. In other words, when both angles A1 and A2 are at least 90 degrees, no portion of the selected gate segment 311 is hidden by the dielectric structure 400 during the directional etching process used to remove the selected gate segment 311. As a result, the selected gate segment 311 can be completely removed. Therefore, the risk of current leakage is substantially reduced. For example, after the etching process used to remove the selected gate segment 311, the remaining portion of the selected gate segment 311 remains in the trench, and then the remaining portion is removed during a subsequent process, forming a void. During a subsequent process, metal will fill the void, thus creating a leakage pathway. Therefore, maintaining angles A1 and A2 at 90 degrees or greater prevents the formation of voids that could lead to current leakage pathways.

[0237] Figure 65 It is a transmission electron microscope (TEM) image of a portion 100' of the semiconductor device 100 formed according to method 1000. Figure 65 Region 965 is shown located at the gate top plane at interface height H1 and above the gate top plane at interface height H1. Insulating feature 500 is located in region 965. In some embodiments, no gate capping layer 350 is retained in region 965.

[0238] In one embodiment, a method of forming a semiconductor structure includes forming a structure comprising a substrate, fins covering the substrate, a gate segment covering the fins and extending from a first endpoint to a second endpoint in a first lateral direction, a dielectric layer segment covering and contacting the gate segment at an interface height, a first vertically extending dielectric structure having a first inner surface adjacent to the first endpoint of the gate segment, and a second vertically extending dielectric structure having a second inner surface adjacent to the second endpoint of the gate segment, wherein the first inner surface and the second inner surface are inclined or parallel to each other from a bottom endpoint to a top endpoint. An etching process is performed to remove the dielectric layer segment, wherein the etching process etches the first inner surface of the first vertically extending dielectric structure and the second inner surface of the second vertically extending dielectric structure, such that a minimum distance is established between the vertically extending dielectric structures at the interface height. The gate segment and the fins located below the gate segment are removed to form a cavity, and an insulating feature is formed in the cavity, wherein the insulating feature extends from a first line endpoint to a second line endpoint in a first lateral direction, wherein the first line endpoint contacts the first vertically extending dielectric structure, and wherein the second line endpoint contacts the second vertically extending dielectric structure.

[0239] In some embodiments of the method, forming an insulating feature in the cavity includes depositing insulating material in the cavity and performing a planarization process to remove excess portions of the insulating material.

[0240] In some embodiments of the method, a planarization process is used to remove excess portions of insulating material to form the upper surface of the substrate, wherein there are no portions of dielectric layer segments at the upper surface.

[0241] In some embodiments of the method, a reserved gate segment is located near an insulating feature. A reserved dielectric layer segment is located above the reserved gate segment. The upper surface of the structure is formed by the insulating feature and the reserved dielectric layer segment. The method further includes removing the reserved dielectric layer segment. After removing the reserved dielectric layer segment, the insulating feature and the vertically extending dielectric structure remain in direct contact on the upper surface.

[0242] In some embodiments of the method, after the structure is formed, the source / drain features are spaced apart from the gate segment in a second lateral direction perpendicular to the first lateral direction, an interlayer dielectric structure is located above the source / drain features, and a cap is located above the ILD structure. The method further includes depositing additional dielectric material over the substrate after removing the retained dielectric layer segment. An additional planarization process is performed to remove the cap, wherein a retained portion of the additional dielectric material remains above the retained gate segment. The ILD structure is removed, and conductive contacts are formed to contact the source / drain features.

[0243] In some embodiments of the method, the etching process forms each inner surface at an interface height that is at an interior angle to the horizontal line, when each interior angle is at least 90 degrees.

[0244] In some embodiments of the method, an insulating feature with an upper portion is formed. The upper portion has a strip shape, which has a lower end, a middle portion, and an upper end in a first transverse direction. The lower end has a low thickness, the middle portion has an intermediate thickness, and the upper end has a high thickness. The intermediate thickness is less than the low thickness and the high thickness.

[0245] In some embodiments of the method, the insulating feature has a top surface. The insulating feature has a first thickness in a first lateral direction of the interface height. The insulating feature has a second thickness in the first lateral direction of the top surface. The second thickness is greater than the first thickness.

[0246] In some embodiments of the method, an etching process is performed to remove dielectric layer segments by etching the first inner surface of the first vertically extending dielectric structure and the second inner surface of the second vertically extending dielectric structure, such that the first inner surface and the second inner surface are perpendicular.

[0247] In another embodiment, the method of forming a semiconductor structure includes forming a structure comprising a substrate, fins covering the substrate and extending in a transverse X direction, a gate structure covering the fins and extending in a transverse Y direction, a dielectric layer covering the gate structure with the transverse Y direction perpendicular to the transverse X direction, and at least one vertically extending dielectric structure cutting through the dielectric layer and the gate structure. An etching process is performed to remove selected portions of the dielectric layer to form an opening, wherein the opening does not contact the at least one vertically extending dielectric structure. A portion of the gate structure and fins below the opening is removed to form a cavity, and an insulating feature is formed in the cavity.

[0248] In some embodiments of the method, the insulating feature is at a non-zero distance from each of at least one vertically extending dielectric structure.

[0249] In some embodiments of the method, forming an insulating feature in the cavity includes depositing insulating material in the cavity and performing a planarization process to remove excess portions of the insulating material.

[0250] In some embodiments of the method, the upper surface of the structure is formed by the retained portions of the insulating feature and the dielectric layer. The method further includes removing the retained portions of the dielectric layer and, after removing the retained portions of the dielectric layer, exposing the upper portion of the sidewall of the insulating feature.

[0251] In some embodiments of the method, after the structure is formed, the source / drain features are spaced apart from the gate structure in the lateral X direction, an interlayer dielectric structure is located above the source / drain features, and a capping layer is located above the ILD structure. The method further includes depositing additional dielectric material over the substrate after removing a retained portion of the dielectric layer. An additional planarization process is performed to remove the capping layer, wherein a retained portion of the additional dielectric material remains above a retained portion of the gate structure. The ILD structure is removed, and conductive contacts are formed to contact the source / drain features.

[0252] In some embodiments of the method, the insulating feature extends from a first wire endpoint to a second wire endpoint along the transverse Y direction, wherein the first wire endpoint contacts a first portion of the additional dielectric material, and wherein the second wire endpoint contacts a second portion of the additional dielectric material.

[0253] In another embodiment, the semiconductor structure includes a first gate structure and a second gate structure spaced apart from each other in the transverse X direction, wherein each gate structure extends in the transverse Y direction, and the transverse X direction is perpendicular to the transverse Y direction. An insulating feature is spaced apart from the first and second gate structures in the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction. A first conductive contact is located between the first gate structure and the insulating feature, and a second conductive structure is located between the second gate structure and the insulating feature. Each conductive contact extends in the transverse Y direction and terminates at a first contact endpoint and a second contact endpoint, respectively. The first contact endpoint defines a first vertical plane that intersects the insulating feature. The second contact endpoint defines a second vertical plane that intersects the insulating feature.

[0254] In some embodiments of the method, the semiconductor structure further includes a first vertically extending dielectric structure and a second vertically extending dielectric structure, the first and second vertically extending dielectric structures extending in the transverse X direction and spaced apart from each other in the transverse Y direction. The upper portion of the first wire endpoint of the insulating feature is surrounded by the first vertically extending dielectric structure, and the upper portion of the second wire endpoint of the insulating feature is surrounded by the second vertically extending dielectric structure.

[0255] In some embodiments of the semiconductor structure, a first gate structure and a second gate structure extend vertically upward to a top surface defining a gate top plane, the vertical direction being perpendicular to the transverse Y-direction and the transverse X-direction. Each of the first and second vertically extending dielectric structures has a top surface. Both the first and second vertically extending dielectric structures have a first thickness in the transverse Y-direction of the gate top plane. Each of the first and second vertically extending dielectric structures has a second thickness in the transverse Y-direction of its respective top surface. For each vertically extending dielectric structure, the second thickness is greater than the first thickness.

[0256] In some embodiments of the semiconductor structure, a first gate structure and a second gate structure extend vertically upward to a top surface defining a gate top plane, the vertical direction being perpendicular to the transverse Y-direction and the transverse X-direction. An insulating feature has a top surface. The insulating feature has a first thickness in the transverse Y-direction of the gate top plane. The insulating feature has a second thickness in the transverse Y-direction of the top surface. The second thickness is greater than or equal to the first thickness.

[0257] In some embodiments of the semiconductor structure, the semiconductor structure further includes at least one vertically extending dielectric structure, each of the at least one vertically extending dielectric structure extending in the lateral X direction. A first line endpoint of the insulating feature is spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance. A second line endpoint of the insulating feature is also spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance.

[0258] In another embodiment, the semiconductor structure includes a first gate structure and a second gate structure, a first vertically extending dielectric structure and a second vertically extending dielectric structure, and an insulating feature. The first gate structure and the second gate structure are spaced apart from each other along a transverse X direction, wherein the first gate structure and the second gate structure extend along a transverse Y direction, the transverse X direction being perpendicular to the transverse Y direction. The first vertically extending dielectric structure and the second vertically extending dielectric structure are spaced apart from each other along the transverse Y direction and extend along the transverse X direction. The insulating feature is spaced apart from the first gate structure and the second gate structure along the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction, wherein the first line endpoint contacts the first vertically extending dielectric structure, and wherein the second line endpoint contacts the second vertically extending dielectric structure.

[0259] In some embodiments of the semiconductor structure, the semiconductor structure further includes source / drain features spaced apart from the first gate structure and the second gate structure in the lateral X direction, an interlayer dielectric structure located above the source / drain features, and a top cap located above the interlayer dielectric structure.

[0260] In some embodiments of the semiconductor structure, the insulating feature includes an upper portion. The upper portion has a strip shape having a lower end, a middle portion, and an upper end in the transverse Y direction. The lower end has a low thickness, the middle portion has an intermediate thickness, and the upper end has a high thickness. The intermediate thickness is less than the low thickness and the high thickness.

[0261] In another embodiment, the semiconductor structure includes a first gate structure and a second gate structure, an insulating feature, a first conductive contact and a second conductive contact, and at least one vertically extending dielectric structure. The first gate structure and the second gate structure are spaced apart from each other along a transverse X direction, wherein the first gate structure and the second gate structure extend along a transverse Y direction, the transverse X direction being perpendicular to the transverse Y direction. The insulating feature is spaced apart from the first gate structure and the second gate structure along the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction. A first conductive contact is located between the first gate structure and the insulating feature, and a second conductive contact is located between the second gate structure and the insulating feature. At least one vertically extending dielectric structure extends along the transverse X direction, wherein the first line endpoint of the insulating feature is spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance.

[0262] In some embodiments of the semiconductor structure, the semiconductor structure further includes source / drain features spaced apart from the gate structure along the lateral X direction, an interlayer dielectric structure located above the source / drain features, and a top cap located above the interlayer dielectric structure.

[0263] In some embodiments of the semiconductor structure, the second wire endpoint of the insulating feature is spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance.

[0264] The features of many embodiments outlined above will enable those skilled in the art to better understand the viewpoint of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same benefits as the embodiments described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized by, include: A first gate structure and a second gate structure are spaced apart from each other along a transverse X direction, wherein the first gate structure and the second gate structure extend along a transverse Y direction, and the transverse X direction is perpendicular to the transverse Y direction; A first vertically extending dielectric structure and a second vertically extending dielectric structure are spaced apart from each other along the transverse Y direction and extend along the transverse X direction; and An insulating feature is spaced apart from the first gate structure and the second gate structure along the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction, wherein the first line endpoint contacts the first vertically extending dielectric structure, and wherein the second line endpoint contacts the second vertically extending dielectric structure.

2. The semiconductor structure of claim 1, wherein, Further includes: A source / drain feature is separated from the first gate structure and the second gate structure in the lateral X direction; A dielectric structure is located above the source / drain feature; and A cover is located above the interlayer dielectric structure.

3. The semiconductor structure of claim 1, wherein, The insulation feature includes: An upper portion having a strip-shaped portion having a lower end, a middle portion, and an upper end in the transverse Y direction, the lower end having a low thickness, the middle portion having an intermediate thickness, and the upper end having a high thickness; and The intermediate thickness is less than the low thickness and the high thickness.

4. A semiconductor structure, characterized by include: A first gate structure and a second gate structure are spaced apart from each other along a transverse X direction, wherein the first gate structure and the second gate structure extend along a transverse Y direction, and the transverse X direction is perpendicular to the transverse Y direction; An insulating feature is spaced apart from the first gate structure and the second gate structure along the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction; A first conductive contact is located between the first gate structure and the insulating feature, and a second conductive contact is located between the second gate structure and the insulating feature; as well as At least one vertically extending dielectric structure extends along the transverse X direction, wherein the first line endpoint of the insulating feature is spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance.

5. The semiconductor structure of claim 4, wherein, Further includes: A source / drain feature is separated from the first gate structure and the second gate structure along the lateral X direction; A dielectric structure is located above the source / drain feature; and A cover is located above the interlayer dielectric structure.

6. The semiconductor structure as described in claim 4, characterized in that, The second wire endpoint of the insulating feature is spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance.

7. A semiconductor structure, characterized in that, include: A first gate structure and a second gate structure are spaced apart from each other along a transverse X direction, wherein the first gate structure and the second gate structure extend along a transverse Y direction, and the transverse X direction is perpendicular to the transverse Y direction; An insulating feature is spaced apart from the first gate structure and the second gate structure along the transverse X direction, wherein the insulating feature extends from a first line endpoint to a second line endpoint in the transverse Y direction; and A first conductive contact is located between the first gate structure and the insulating feature, and a second conductive contact is located between the second gate structure and the insulating feature; wherein: The first conductive contact and the second conductive contact extend along the transverse Y direction and terminate at a first contact end point and a second contact end point, respectively. The first contact endpoint defines a first vertical plane, which intersects with the insulating feature; and The second contact endpoint defines a second vertical plane that intersects with the insulating feature.

8. The semiconductor structure as described in claim 7, characterized in that, It further includes a first vertically extending dielectric structure and a second vertically extending dielectric structure, wherein: The first vertically extending dielectric structure and the second vertically extending dielectric structure extend along the transverse X direction and are spaced apart from each other along the transverse Y direction; The upper portion of the first wire endpoint of the insulation feature is surrounded by the first vertically extending dielectric structure; and The upper portion of the second wire endpoint of the insulating feature is surrounded by the second vertically extending dielectric structure.

9. The semiconductor structure as described in claim 8, characterized in that, in: The first gate structure and the second gate structure extend upward along a vertical direction to a plurality of top surfaces defining a gate top plane, the vertical direction being perpendicular to the lateral Y direction and the lateral X direction; The first vertically extended dielectric structure and the second vertically extended dielectric structure each have a top surface; The first vertically extended dielectric structure and the second vertically extended dielectric structure each have a first thickness in the transverse Y direction of the top plane of the gate; The first vertically extending dielectric structure and the second vertically extending dielectric structure have a second thickness in the transverse Y direction of each of the top surfaces; and For the first vertically extended dielectric structure and the second vertically extended dielectric structure, the second thickness is greater than the first thickness.

10. The semiconductor structure as claimed in claim 7, characterized in that, It further includes at least one vertically extending dielectric structure, wherein: Each of the at least one vertically extending dielectric structure extends along the transverse X direction; The first wire endpoint of the insulating feature is spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance; and The second wire endpoint of the insulating feature is spaced apart from each of the at least one vertically extending dielectric structure by a non-zero distance.

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