Top-gate igzo transistor with stacked gate dielectric
By using a stacked gate dielectric structure, yttrium oxide was prepared by electron beam deposition and hafnium oxide was grown by combining it with ALD process. This solved the interface state defects and leakage current problems in the top gate structure of IGZO, and enabled the fabrication of high-performance and low-cost IGZO transistors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIANGTAN UNIV
- Filing Date
- 2025-03-25
- Publication Date
- 2026-06-19
Smart Images
Figure CN224386020U_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of MOS transistor (MOSFET) technology, and in particular to fourth-generation IGZO devices, specifically to a top-gate IGZO transistor with a stacked gate dielectric. Background Technology
[0002] A MOSFET (Metal-Oxide-Semiconductor Transistor) is a voltage-controlled field-effect transistor based on a metal-oxide-semiconductor structure. It regulates the drain-source current by adjusting the gate voltage. Its core structure includes a gate (isolated by an insulating layer), source, drain, and substrate. MOSFETs are classified as enhancement-mode (requiring an external voltage to form a conductive channel) and depletion-mode (with a channel present by default). During operation, the gate voltage controls the formation of an inversion layer (similar to electron accumulation in an N-channel), enabling conduction and cutoff. MOSFETs feature high input impedance, low quiescent power consumption, and high-frequency characteristics, and are widely used in digital circuits (such as CMOS logic), analog amplification, and power switching.
[0003] Current integrated circuit systems primarily use transistors based on silicon-based CMOS (Complementary Metal-Oxide-Semiconductor) technology. IGZO (Indium Gallium Zinc Oxide), as an indium-based oxide semiconductor, plays a complementary role in current CMOS devices, exhibiting unique advantages, particularly in low-power, high-density integration, and novel computing architectures.
[0004] In 8K OLEDs, the mobility of the top-gate IGZO TFT (typically 10-30 cm⁻¹) is... 2 The / Vs) technology supports pixel charging time reduction to below 1μs and aperture ratio increase to 85%. For example, Sharp's mass-produced 6th generation IGZO panels use a top-gate etched barrier structure, reducing power consumption by 40%. While dual-gate design can further reduce leakage current (<10-22A / μm), the increased gate signal delay in large-size panels leads to a decrease in dynamic response speed. In the field of memory computing, the 2T0C DRAM cell developed by the Institute of Microelectronics utilizes the low leakage current characteristics of top-gate IGZO (achieving off-state current <10Vs). -21 A / μm), achieving non-volatile memory cycles exceeding 10. 14 Secondly, while the dual-gate all-around structure can improve cell density, the threshold voltage drift caused by hydrogen doping needs to be addressed, and it is currently only in the laboratory verification stage.
[0005] IGZO top-gate structures offer significant advantages over back-gate and dual-gate designs in display and memory applications due to their high process compatibility, controllable interface defects, and 3D integration potential. For example, top-gate structures can directly grow the gate dielectric layer on top of the channel using ALD (atomic layer deposition) technology, precisely controlling oxygen vacancies and hydrogen doping at the interface. Although dual-gate structures theoretically have superior electrical performance, their complex fabrication process and high cost limit large-scale commercial applications. In comparison, top-gate devices offer lower process complexity and cost, better electrical performance stability, and greater stability in 3D integration compared to dual-gate devices.
[0006] In the traditional IGZO top-gate device manufacturing process, such as single-layer gate dielectric devices or multi-layer ALD gate dielectric device designs, the direct growth of a single-layer hafnium oxide gate dielectric layer using the ALD process will form interface states at the hafnium oxide and IGZO channel, improving ohmic contact. At the same time, the precursor source used in ALD will cause irreversible damage to the active layer IGZO. This damage comes from the erosion of the active layer IGZO by the precursors (hafnium precursor source (dimethylaminohafnium) and oxygen precursor source (water)) during the ALD growth of hafnium oxide, generating oxygen and metal-related defects and hydroxyl groups, increasing leakage current. This defect-filled channel / GI interface will affect transistor characteristics. Utility Model Content
[0007] The purpose of this invention is to provide a top-gate IGZO transistor with a multilayer gate dielectric, which improves the quality of the gate dielectric, obtains a high-k value yttrium oxide and hafnium oxide multilayer gate dielectric structure, and at the same time reduces the interface states formed on the surface of the IGZO channel material through process optimization, reduces lattice defects on the surface of the IGZO channel material, improves the on-state current and carrier mobility, reduces gate leakage current, and improves device performance.
[0008] According to a first aspect of the present invention, a top-gate IGZO transistor having a multilayer gate dielectric is provided, comprising:
[0009] A Si / SiO2 structure is formed by depositing a SiO2 dielectric layer on a silicon substrate.
[0010] An IGZO semiconductor thin film channel layer covers the upper surface of the SiO2 dielectric layer;
[0011] A source electrode layer and a drain electrode layer are respectively disposed on the upper surface of the IGZO semiconductor thin film channel layer and on both sides;
[0012] A yttrium oxide gate dielectric is disposed on the upper surface of the source electrode layer and the drain electrode layer, and on the upper surface of the IGZO semiconductor thin film channel layer, and at the middle position between the source electrode layer and the drain electrode layer.
[0013] A hafnium oxide gate dielectric grown on the upper surface of a yttrium oxide gate dielectric, the hafnium oxide gate dielectric extending from the yttrium oxide gate dielectric at the midpoint between the source and drain electrode layers to cover the yttrium oxide gate dielectric on the upper surface of the source and drain electrode layers; and
[0014] A gate metal layer deposited on the surface of the hafnium oxide gate dielectric;
[0015] Among them, the hafnium oxide gate dielectric and the hafnium oxide gate dielectric 106 on the upper surface of the IGZO semiconductor thin film channel layer constitute a high-k stacked gate dielectric layer.
[0016] The yttrium oxide gate dielectric is prepared by electron beam deposition and attached to the upper surface of the IGZO semiconductor thin film channel layer to form a repair / isolation structure.
[0017] The hafnium oxide gate dielectric is grown on the surface of the yttrium oxide gate dielectric by an ALD process. During the growth process, the yttrium oxide gate dielectric isolates the precursor source used in the ALD process from the contact between the IGZO semiconductor thin film channel layer and the gate dielectric.
[0018] As an optional embodiment, the yttrium oxide gate dielectric is configured to be fabricated in the following manner:
[0019] A layer of yttrium is deposited on the upper surface of the IGZO semiconductor thin film channel layer by electron beam deposition, and then a high-k oxide layer is formed on the IGZO semiconductor thin film channel layer by annealing oxidation.
[0020] As an optional embodiment, the yttrium metal attached to the upper surface of the IGZO semiconductor thin film channel layer repairs the lattice damage of the IGZO semiconductor thin film channel layer during the annealing and oxidation process.
[0021] As an optional embodiment, both the source electrode layer and the drain electrode layer are Ti / Au electrode layers with the same thickness, both controlled within 60-80 nm.
[0022] As an optional embodiment, the thickness of the IGZO semiconductor thin film channel layer is controlled to be 10-20 nm.
[0023] As an optional embodiment, the thickness of the yttrium oxide gate dielectric is less than the thickness of the hafnium oxide gate dielectric.
[0024] As an optional embodiment, the thickness of the yttrium oxide gate dielectric is 1 to 2 nm; the thickness of the hafnium oxide gate dielectric is 8 to 10 nm.
[0025] As an optional embodiment, the gate metal layer is an Au metal layer with a thickness controlled between 50 and 70 nm.
[0026] The top-gate IGZO transistor with stacked gate dielectric and its fabrication method according to the above embodiments of the present invention can improve the quality of the gate dielectric, enhance the quality of the material, reduce the interface states between the material and the gate dielectric, and improve the manufacturing yield. Since monolayer yttrium oxide is prepared using an electron beam deposition apparatus, it lacks step coverage, which increases the requirements for exposure accuracy and dosage during the manufacturing process. Furthermore, the low k of monolayer yttrium oxide cannot adequately meet the requirements of two-dimensional devices for high-k gate dielectrics. If monolayer hafnium oxide is grown using ALD, interface states will form between the hafnium oxide and the IGZO channel, increasing ohmic contact. Additionally, the precursor source used in ALD growth can damage the IGZO, increasing surface defects and leakage current. The device design proposed in this invention prepares a multilayer gate dielectric. First, Y is deposited above the IGZO channel using electron beam deposition to form a yttrium oxide gate dielectric, which serves as an isolation and protection mechanism, reducing the contact between the precursor and the conductive channel layer in the subsequent ALD process. Then, a hafnium oxide thin film gate dielectric is grown using the ALD method. Due to the excellent step coverage of ALD growth, this not only reduces ohmic contact and interface states but also improves the yield rate and lowers the requirements for the process.
[0027] Compared with existing technologies, the top-gate IGZO transistor with a stacked gate dielectric of this invention, based on traditional IGZO devices (single-layer gate dielectric devices or multi-layer ALD gate dielectric devices), proposes to first prepare a yttrium oxide gate dielectric using an electron beam deposition apparatus, and then combine it with a hafnium oxide gate dielectric grown in an ALD to form a stacked gate dielectric layer, successfully fabricating a top-gate IGZO transistor with a yttrium oxide and hafnium oxide stacked gate dielectric. The significant advantages of this invention compared with existing technologies are:
[0028] 1) First, a layer of yttrium is deposited on the active layer by electron beam deposition, and then a dense high-k oxide layer is formed on the active layer by annealing oxidation. This not only acts as a "passivation layer" to isolate the active layer and prevent precursor source erosion during ALD growth of hafnium oxide, thus protecting the active layer channel (yttrium oxide can adhere to the surface of the IGZO active layer, reducing the contact between the precursor source and the active layer during ALD growth of hafnium oxide, reducing damage to the active layer), but also repairs lattice defects in the active layer and improves the on-state current. This is because when the coating instrument sputters Y to the active layer, given the active properties of metallic Y, the annealing oxidation of Y to yttrium oxide will repair the lattice damage of the active layer. At the same time, yttrium oxide can also act as an oxygen source, taking oxygen atoms from the surface of the active layer, resulting in an increase in oxygen vacancies on the surface of the IGZO channel. This is beneficial to the electron enrichment ability of the channel surface, thereby improving the on-state current and carrier mobility.
[0029] 2) Building upon the yttrium oxide (YO) gate dielectric, a hafnium oxide (YO) gate dielectric is further grown using the ALD (Alternating Deposition) process. Since monolayer YO is produced by electron beam evaporation, it lacks step coverage. Furthermore, IGZO, being an oxide, cannot be thinned into a two-dimensional material due to current instrument limitations. Therefore, a thicker YO film is needed to reduce gate leakage current, which contradicts the initial goals of improving device performance and thinning the gate dielectric. Additionally, the relatively low k-value of YO results in weak gate control capability for monolayer YO. Considering the lack of step coverage and relatively low k-value of electron beam-deposited YO, a high-k gate dielectric, hafnium oxide, is grown using ALD on top of the YO gate dielectric. Leveraging the step coverage and high-k properties of ALD-grown hafnium oxide not only reduces the risk of gate leakage current but also improves gate control capability. YO can adhere to the surface of the IGZO active layer, reducing contact between the precursor source and the active layer during ALD growth and minimizing damage to the active layer.
[0030] 3) In post-process annealing, under the same conditions (200°C annealing in air for 30 min), the yttrium oxide hafnium oxide multilayer gate dielectric IGZO transistor has an order of magnitude higher on-state current and a positive threshold voltage closer to 0 compared to the hafnium oxide single-layer gate dielectric top-gate IGZO transistor.
[0031] It should be understood that all combinations of the foregoing concepts and the additional concepts described in more detail below may be considered part of the utility model subject matter of this disclosure, provided that such concepts do not contradict each other. Furthermore, all combinations of the claimed subject matter are considered part of the utility model subject matter of this disclosure.
[0032] The foregoing and other aspects, embodiments, and features of the present invention will be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as features and / or beneficial effects of exemplary embodiments, will become apparent from the following description or may be learned through practice of specific embodiments according to the teachings of the present invention. Attached Figure Description
[0033] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings.
[0034] Figure 1 This is a schematic diagram of the structure of a top-gate IGZO transistor with a stacked gate dielectric according to an embodiment of the present invention.
[0035] Figure 2This is a front view of the structure of a top-gate IGZO transistor with a stacked gate dielectric according to an embodiment of the present invention.
[0036] Figure 3 This is a schematic flowchart illustrating a method for fabricating a top-gate IGZO transistor with a multilayer gate dielectric according to an embodiment of the present invention.
[0037] Figure 4 This is an example of a test comparison between a top-gate IGZO transistor with a multilayer gate dielectric and a single-layer hafnium oxide top-gate IGZO device according to an embodiment of the present invention.
[0038] Figure 5 It is based on Figure 4 V extracted from the test comparison chart ds Comparison of transfer characteristic curves between a yttrium oxide-hafnium oxide multilayer gate dielectric top-gate IGZO device and a single-layer hafnium oxide top-gate IGZO device at 1V. Detailed Implementation
[0039] To better understand the technical content of this utility model, specific embodiments are provided below in conjunction with the accompanying drawings.
[0040] Various aspects of the present invention are described in this disclosure with reference to the accompanying drawings, which illustrate numerous illustrative embodiments. The embodiments disclosed herein are not necessarily intended to include all aspects of the present invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the present invention can be used alone or in any suitable combination with other aspects disclosed herein.
[0041] {Example 1}
[0042] Combination Figure 1 , Figure 2 The example shown is a top-gate IGZO transistor with stacked gate dielectrics, including a silicon substrate 100, a SiO2 dielectric layer 101, an IGZO semiconductor thin film channel layer 102, a source electrode layer 103, a source electrode layer 104, a yttrium oxide gate dielectric 105, a hafnium oxide gate dielectric 106, and a gate metal layer 107.
[0043] like Figure 1 , Figure 2 As shown, a SiO2 dielectric layer 101 is deposited on a silicon substrate 100 to form a Si / SiO2 structure. The SiO2 dielectric layer 101 serves as a deposition substrate for the IGZO thin film and also provides electrical insulation between the IGZO thin film and the silicon substrate 100.
[0044] An IGZO semiconductor thin film channel layer 102 is applied to the upper surface of the SiO2 dielectric layer.
[0045] Source electrode layers 103 and 104 are respectively disposed on the upper surface of the IGZO semiconductor thin film channel layer 102 and located on both sides, and are symmetrically distributed on both sides.
[0046] A yttrium oxide gate dielectric 105 is disposed on the upper surface of the source electrode layer 103 and the drain electrode layer 104, and on the upper surface of the IGZO semiconductor thin film channel layer 102, and located at the middle position between the source electrode layer 103 and the drain electrode layer 104.
[0047] Hafnium oxide gate dielectric 106 is further grown on the upper surface of yttrium oxide gate dielectric 105, such as... Figure 1 , 2 As shown, the hafnium oxide gate dielectric 106 is particularly preferably grown by an ALD process, extending from the yttrium oxide gate dielectric 105 located between the source electrode layer 103 and the drain electrode layer 104 to cover the upper surface of the source electrode layer 103 and the drain electrode layer 104.
[0048] like Figure 1 , 2 As shown, a gate metal layer 107 is deposited on the upper surface of the hafnium oxide gate dielectric 106.
[0049] In an embodiment of this invention, the hafnium oxide gate dielectric 106 on the upper surface of the IGZO semiconductor thin film channel layer 102 forms a high-k stacked gate dielectric layer.
[0050] The aforementioned yttrium oxide gate dielectric 105 is prepared by an electron beam deposition process and attached to the upper surface of the IGZO semiconductor thin film channel layer 102 to form a repair / isolation structure.
[0051] The aforementioned hafnium oxide gate dielectric 106 is obtained by growing on the surface of yttrium oxide gate dielectric 105 through an ALD process. During the growth process, the yttrium oxide gate dielectric 105 isolates the precursor source used in the ALD process from the contact between the IGZO semiconductor thin film channel layer 102.
[0052] It should be understood that the aforementioned source electrode layer 103, drain electrode layer 104, and gate metal layer 107 can all be led to their respective output electrodes via their respective metal leads to achieve signal output. In particular, the metal leads are insulated and encapsulated to prevent them from being transmitted to conductive parts during detection. The output electrodes can be electrically connected to external devices, such as computer systems or servers, to output signals for external signal analysis.
[0053] In a preferred embodiment, the yttrium oxide gate dielectric 105 is configured to be fabricated as follows:
[0054] A layer of yttrium is deposited on the upper surface of the IGZO semiconductor thin film channel layer 102 by electron beam deposition, and then a high-k oxide layer is formed on the IGZO semiconductor thin film channel layer 102 by annealing oxidation. The yttrium adhering to the upper surface of the IGZO semiconductor thin film channel layer 102 repairs the lattice damage of the IGZO semiconductor thin film channel layer 102 during the annealing oxidation process.
[0055] As an optional embodiment, both the source electrode layer 103 and the drain electrode layer 104 are Ti / Au electrode layers with the same thickness, both controlled within 60-80 nm.
[0056] As an optional embodiment, the thickness of the IGZO semiconductor thin film channel layer 102 is controlled to be 10-20 nm.
[0057] As an optional embodiment, the thickness of the yttrium oxide gate dielectric 105 is less than the thickness of the hafnium oxide gate dielectric 106.
[0058] As an optional embodiment, the thickness of the yttrium oxide gate dielectric 105 is 1 to 2 nm; the thickness of the hafnium oxide gate dielectric 106 is 8 to 10 nm.
[0059] As an optional embodiment, the gate metal layer 107 is an Au metal layer with a thickness controlled between 50 and 70 nm.
[0060] {Example 2}
[0061] Combination Figure 1 , Figure 2 ,like Figure 3 The fabrication process of the top-gate IGZO transistor with stacked gate dielectric shown includes the following steps:
[0062] Step 1: Deposit a SiO2 dielectric layer on a silicon substrate to form a Si / SiO2 structure;
[0063] Step 2: Sputter an IGZO thin film onto the surface of the SiO2 dielectric layer using magnetron sputtering, with the thickness controlled between 10 and 20 nm.
[0064] Step 3: Spin coat the Si / SiO2 structure surface with sputtered IGZO film using a spin coater, expose the corresponding pattern using photolithography, and etch the IGZO film to obtain the IGZO channel layer.
[0065] Step 4: Spin the photoresist again, expose the source and drain electrodes using a photolithography machine, and deposit a certain thickness of metal using an electron beam deposition process to form the source and drain electrodes.
[0066] Step 5: After the first spin coating, expose the gate dielectric layer of the device. First, use an electron beam coating machine to prepare yttrium oxide gate dielectric, and then grow hafnium oxide gate dielectric layer on the basis of yttrium oxide gate dielectric through ALD process.
[0067] Step 6: Spin coat the coating again, expose the gate metal layer of the device, and then deposit the gate metal layer using an electron beam deposition process.
[0068] As an optional specific embodiment, the fabrication process of a top-gate IGZO transistor with a multilayer gate dielectric includes the following steps:
[0069] Step 1: Deposit a certain thickness of SiO2 on a silicon substrate as a dielectric layer to form a Si / SiO2 structure with a total thickness of 300-400 nm.
[0070] Step 2: Sputter an IGZO thin film onto the surface of the SiO2 dielectric layer using magnetron sputtering, with the thickness controlled between 10 and 20 nm.
[0071] Step 3: Spin coat the Si / SiO2 structure surface with sputtered IGZO film using a spin coater, expose the corresponding pattern using photolithography, and etch the IGZO film to obtain the IGZO channel layer.
[0072] Specifically, on a Si / SiO2 two-layer structure substrate with sputtered IGZO thin film, two layers of photoresist, LOR and S1813, are uniformly coated by a spin coater. Then, the IGZO thin film is etched by a laser direct writing machine and dilute hydrochloric acid etching to form an IGZO channel layer, so that IGZO becomes the channel region. Finally, it is heated and annealed on a heating stage at 300°C for 30 minutes.
[0073] Step 4: Spin the photoresist again, expose the source and drain electrodes using a photolithography machine, and deposit a certain thickness of metal using an electron beam deposition process to form the source and drain electrodes;
[0074] Specifically, two layers of photoresist, LOR and S1813, are uniformly coated on the etched substrate using a spin coater. The source and drain electrodes are exposed using a laser direct writing machine, and a 20nm thick Ti and a 50nm thick Au are deposited using an electron beam deposition machine to form the source and drain electrodes.
[0075] Step 5: Spin coat again and expose the gate dielectric layer of the device. First, deposit yttrium oxide gate dielectric using an electron beam coating machine, and then grow hafnium oxide gate dielectric based on ALD process.
[0076] Specifically, two layers of photoresist, LOR and S1813, are uniformly coated on the substrate forming the source and drain using a spin coater. Then, the gate insulating layer is exposed using a laser direct writing machine. First, a 2nm thick yttrium oxide gate dielectric is deposited under an electron beam coating machine, and then an 8nm thick hafnium oxide gate dielectric is grown under ALD.
[0077] Step 6: Spin coat again, expose the gate metal layer of the device, and then use electron beam deposition to form the gate metal layer;
[0078] Specifically, the process involves uniformly coating two layers of photoresist, LOR and S1813, onto a substrate with grown gate dielectric using a spin coater, then exposing the gate metal layer using a laser direct writing machine, and finally depositing a 60nm thick Au layer using an electron beam deposition machine to form the gate metal layer.
[0079] As an optional embodiment, the SiO2 dielectric layer can be deposited using existing semiconductor micro / nano processes, with the Si / SiO2 two-layer structure controlled at 300-400 nm.
[0080] The sputtering length of IGZO is 10μm to 80μm, the width is 5 to 20μm, and the thickness is 10 to 20nm.
[0081] As an example, the length of the source and drain electrode layers is controlled to be at least 10 μm, the width is controlled to be at least 2 μm, and the thickness is at least 60 nm.
[0082] As an example, the source and drain electrodes are made of Ti / Au metal electrodes with a thickness of 60-80 nm.
[0083] As an example, the gate dielectric layer is a stack composed of a yttrium oxide gate dielectric layer and a hafnium oxide gate dielectric layer, with a length of 30 to 90 μm, a width of 15 to 35 μm, a yttrium oxide thickness of 2 nm, and a hafnium oxide thickness of 10 nm.
[0084] As an example, the gate electrode is an Au metal electrode with a length of 20–80 μm, a width of 5–20 μm, and a thickness of 50–60 nm.
[0085] like Figure 1 , 2 As shown in the figure, the parameters of the IGZO transistor prepared by this invention are as follows:
[0086] Active layer: 60μm long, 30μm wide, and 17nm thick;
[0087] Source and drain electrodes: 70 μm long, 10 μm wide, and 60 nm thick;
[0088] Gate dielectric: 2nm thick yttrium oxide dielectric layer, 8nm thick hafnium oxide dielectric layer, with length and width dimensions of 90μm*30μm;
[0089] Gate metal: 80μm long, 20μm wide, 60nm thick;
[0090] Output electrode (pad): 150μm*150μm in size and 80nm in thickness.
[0091] {Example 3}
[0092] In this embodiment, while fabricating a prototype top-gate IGZO transistor with a multilayer gate dielectric according to the aforementioned process, we also fabricated a top-gate IGZO transistor with a hafnium oxide single-layer gate dielectric. The electrical parameters of the two devices were measured using a semiconductor analyzer, and the performance indicators were compared by data processing.
[0093] The testing method is as follows: a semiconductor analyzer is used to measure the voltage between the source and drain, a positive voltage is set between the source and drain, and a voltage is set at the gate. The current between the source and drain is controlled by the gate voltage.
[0094] Result analysis is performed using the transfer characteristic curve and output curve: I can be obtained from the transfer characteristic curve. on I on / I off V th SS, μ n g m I was extracted by analyzing data using Origin data analysis software. on I on / I off SS and g are obtained through partial differential equations. m and D it (The subthreshold swing method is suitable for rapid device-level evaluation), and then μ is extracted using the maximum transconductance method. n The contact resistance can be obtained from the output curve.
[0095] Combination Figure 4 As shown in the figure, Figure a on the left represents the test results of a 10nm monolayer hafnium oxide gate dielectric top-gate IGZO device with an aspect ratio of W / L = 60 / 20μm. The V values were tested separately. ds =0.5V~3V, V gs Transfer characteristic curve from -3 to 3V.
[0096] Figure b on the right shows the test results of top-gate IGZO devices with 2nm yttrium oxide and 8nm hafnium oxide multilayer gate dielectrics, with aspect ratios W / L = 60 / 20μm. The V1 and V2 parameters were tested respectively. gs From -3 to 3V, V ds Transfer characteristic curves from 0.5V to 3V.
[0097] contrast Figure 4 The test results for the two different devices show that, compared to the test results in Figure a, the ΔV in Figure b is lower. th The threshold voltage drift increases to some extent because of minute defects between the multilayer gate dielectrics, but ΔV thBoth results are within acceptable ranges and can be improved through subsequent annealing. Furthermore, when the threshold voltages are similar, the on-state current in Figure b is increased by 1 to 2 orders of magnitude. This is because during the yttrium oxide coating process, yttrium oxide acts as an oxygen source, taking oxygen atoms from the active layer surface, leading to an increase in oxygen vacancies on the IGZO channel surface. This enhances the electron enrichment capacity of the channel surface, thereby improving the on-state current.
[0098] exist Figure 4 Based on the comparison of test results, V was extracted from the graph. ds The transfer characteristic curves of a yttrium oxide-hafnium oxide multilayer gate dielectric top-gate IGZO device and a single-layer hafnium oxide top-gate IGZO device at 1V are compared as follows:
[0099] Test results of multilayer gate dielectric devices:
[0100] Ion=292μA, SS=98mV / dec, Vth=-0.7V, Ion / Ioff=0.87E+6,
[0101] Gm is 141 μS, and the mobility μn = 29.5 cm. 2 / (V*s).
[0102] Test results of single-layer gate dielectric devices:
[0103] Ion=2.78μA, SS=199mV / dec, Vth=-1.1V, Ion / Ioff=0.68E+4
[0104] Gm is 1.51 μS, and the mobility μn = 4.9 cm. 2 / (V*s).
[0105] Based on the comparison of the above test results, such as Figure 5 As shown, the SS of a single-layer hafnium oxide device is 199 mV / dec, while the SS of the multilayer gate dielectric device designed in this invention is 98 mV / dec. This is due to the damage to IGZO (single-layer hafnium oxide device) by the precursor source during the ALD growth of hafnium oxide. This includes oxygen and metal-related defects as well as some hydroxyl groups, which increases roughness and leads to a decrease in gate control capability.
[0106] Meanwhile, the threshold voltage of the multilayer gate dielectric increases by 1 to 2 orders of magnitude relative to the positive shift of the single-layer hafnium oxide and the on-state current, which together confirm the enhancement and advantages of yttrium oxide for the active layer material in the multilayer gate dielectric. As Y is sputtered onto the active layer by the coating machine, due to the metal activity of Y, the annealing oxidation of Y into yttrium oxide will repair the lattice damage of the active layer. At the same time, yttrium oxide can also act as an oxygen source, taking oxygen atoms from the surface of the active layer, resulting in an increase in oxygen vacancies on the surface of the IGZO channel. This is beneficial to the electron enrichment ability of the channel surface, thereby increasing the on-state current and significantly improving the device performance.
[0107] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the claims.
Claims
1. A top-gate IGZO transistor with a multilayer gate dielectric, characterized in that, include: A SiO2 dielectric layer (101) is deposited on a silicon substrate (100) to form a Si / SiO2 structure; An IGZO semiconductor thin film channel layer (102) covers the upper surface of the SiO2 dielectric layer; A source electrode layer (103) and a drain electrode layer (104) are respectively disposed on the upper surface of the IGZO semiconductor thin film channel layer (102) and on both sides. A yttrium oxide gate dielectric (105) is disposed on the upper surface of the source electrode layer (103) and the drain electrode layer (104), and on the upper surface of the IGZO semiconductor thin film channel layer (102), and located at the middle position between the source electrode layer (103) and the drain electrode layer (104). A hafnium oxide gate dielectric (106) is grown on the upper surface of a yttrium oxide gate dielectric (105), the hafnium oxide gate dielectric (106) extending from the yttrium oxide gate dielectric (105) located between the source electrode layer (103) and the drain electrode layer (104) to cover the yttrium oxide gate dielectric (105) on the upper surface of the source electrode layer (103) and the drain electrode layer (104); and A gate metal layer (107) is deposited on the upper surface of the hafnium oxide gate dielectric (106). Among them, the hafnium oxide gate dielectric (106) on the upper surface of the IGZO semiconductor thin film channel layer (102) and the hafnium oxide gate dielectric (106) constitute a high-k stacked gate dielectric layer; The yttrium oxide gate dielectric is attached to the upper surface of the IGZO semiconductor thin film channel layer (102) to form a repair / isolation structure; The hafnium oxide gate dielectric (106) is formed by growing a layer on the surface of the yttrium oxide gate dielectric (105). During the growth process, the yttrium oxide gate dielectric (105) isolates the contact between the precursor source used in the ALD process and the IGZO semiconductor thin film channel layer (102). The source electrode layer (103), drain electrode layer (104) and gate metal layer (107) are all led to the corresponding output electrode through their respective metal leads to realize signal output; the metal leads are insulated and encapsulated to be mutually insulated from the conductive parts during detection.
2. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that, The yttrium oxide gate dielectric (105) is configured to be fabricated in the following manner: A layer of yttrium metal is deposited on the upper surface of the IGZO semiconductor thin film channel layer (102) by electron beam deposition, and then a high-k oxide layer is formed on the IGZO semiconductor thin film channel layer (102) by annealing oxidation.
3. The top-gate IGZO transistor with a stacked gate dielectric according to claim 2, characterized in that, The yttrium metal attached to the upper surface of the IGZO semiconductor thin film channel layer (102) repairs the lattice damage of the IGZO semiconductor thin film channel layer (102) during the annealing and oxidation process.
4. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that, Both the source electrode layer (103) and the drain electrode layer (104) are Ti / Au electrode layers with the same thickness, which is controlled at 60~80nm.
5. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that, The thickness of the IGZO semiconductor thin film channel layer (102) is controlled at 10~20nm.
6. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that, The thickness of the yttrium oxide gate dielectric (105) is less than the thickness of the hafnium oxide gate dielectric (106).
7. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that, The thickness of the yttrium oxide gate dielectric (105) is 1~2 nm; the thickness of the hafnium oxide gate dielectric (106) is 8~10 nm.
8. The top-gate IGZO transistor with a stacked gate dielectric according to claim 1, characterized in that, The gate metal layer (107) is an Au metal layer with a thickness controlled between 50 and 70 nm.