integrated chip

Abstract

The integrated chip of this embodiment includes an active layer. A first source / drain and a second source / drain are located on the upper surface of the active layer. A gate is located on a first side of the active layer and between the first source / drain and the second source / drain. A gate dielectric layer is located between the gate and the active layer. A first barrier layer is located on a second side of the active layer and spaced apart from the active layer, the second side being opposite to the first side of the active layer. A second barrier layer is located on the first side of the active layer and spaced apart from the active layer, and extends along the gate.

Description

Technical Field

[0001] This utility model relates to an integrated chip. Background Technology

[0002] Many electronic devices contain numerous metal-oxide-semiconductor field-effect transistors (MOSFETs). A MOSFET includes a gate located between the source and drain. Depending on the voltage applied to the gate to turn on the MOSFET, MOSFETs can be classified as high-voltage (HV), medium-voltage (MV), or low-voltage (LV) devices. The structural design parameters of each MOSFET in an electronic device vary depending on the required electrical characteristics. Utility Model Content

[0003] The integrated chip of this embodiment includes an active layer. A first source / drain and a second source / drain are located on the upper surface of the active layer. A gate is located on a first side of the active layer and between the first source / drain and the second source / drain. A gate dielectric layer is located between the gate and the active layer. A first barrier layer is located on a second side of the active layer and spaced apart from the active layer, the second side being opposite to the first side of the active layer. A second barrier layer is located on the first side of the active layer and spaced apart from the active layer, and extends along the gate.

[0004] The integrated chip of this embodiment includes a first dielectric layer. A first barrier layer is located on the first dielectric layer. A second dielectric layer is located on the first barrier layer. An active layer is located on the second dielectric layer. A first source / drain and a second source / drain are located on the active layer. A gate is located on the active layer and between the first source / drain and the second source / drain. A gate dielectric layer is located between the gate and the active layer. A second barrier layer is spaced apart from the active layer and extends along the gate. Attached Figure Description

[0005] This disclosure can be better understood when read in conjunction with the accompanying drawings in the following detailed description. It should be emphasized that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion. Furthermore, it should be emphasized that the drawings only show typical embodiments of the present invention and should not be considered as limiting the scope of the claim, as the present invention can be equally applied to other embodiments.

[0006] Figure 1 A cross-sectional view of a transistor device including a barrier layer surrounding an active layer is shown in some embodiments.

[0007] Figure 2 , 4 6, 8, and 10 show Figure 1Cross-sectional views of various embodiments of a transistor device, wherein the gate is on the active layer.

[0008] Figure 3 , 5 7, 9, and 11 respectively show Figure 2 , 4 Top view of some embodiments of transistor devices of types 6, 8, and 10.

[0009] Figure 12 Cross-sectional views of some embodiments of an integrated chip are shown. The integrated chip includes interconnect structures disposed on a substrate. Figure 10 Transistor devices.

[0010] Figure 13 It shows Figure 1 Cross-sectional views of some embodiments of a transistor device, wherein the gate is below the active layer.

[0011] Figure 14 Cross-sectional views of some embodiments of an integrated chip are shown. The integrated chip includes interconnect structures disposed on a substrate. Figure 13 Transistor devices.

[0012] Figure 15 It shows Figure 1 Cross-sectional views of some embodiments of a transistor device, wherein the transistor device is configured along a substrate.

[0013] Figure 16 Cross-sectional views of some embodiments of integrated chips are shown. The integrated chip includes... Figure 15 Transistor devices.

[0014] Figure 17-22 , Figure 23-29 , Figures 30-33 , Figure 34-37 and Figure 38-41 A cross-sectional view of a method for forming a transistor device is shown. The transistor device includes a gate located on an active layer and a barrier layer surrounding the active layer.

[0015] Figure 42 A flowchart illustrating some embodiments of a method for forming a transistor device is shown. The transistor device includes a gate located on an active layer and a barrier layer surrounding the active layer.

[0016] Figures 43-47 A cross-sectional view of a method for forming a transistor device is shown. The transistor device includes a gate located under an active layer and a barrier layer surrounding the active layer.

[0017] Figure 48 A flowchart illustrating some embodiments of a method for forming a transistor device is shown. The transistor device includes a gate located under an active layer and a barrier layer surrounding the active layer.

[0018] Figures 49-53 A cross-sectional view of a method for forming a transistor device along a substrate is shown, the transistor device including a barrier layer surrounding an active layer of the substrate.

[0019] Figure 54 A flowchart of a method for forming a transistor device along a substrate is shown, the transistor device including a barrier layer surrounding an active layer of the substrate. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of this utility model. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these or similar examples are merely illustrative and not intended to be limiting. For instance, in the following description, the formation of a first feature on or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatial relative terms such as "underlying," "below," "lower," "overlying," "upper," and similar terms may be used herein to describe the relationship between one component or feature and another, as shown in the figures. Besides the orientations depicted in the figures, the spatial relative terms are also intended to cover different orientations of components during use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0022] The integrated chip includes a transistor device. The transistor device includes a first source / drain and a second source / drain along an active layer, a gate between the first source / drain and the second source / drain, and a gate dielectric layer between the gate and the active layer. A channel region of the active layer extends from the first source / drain to the second source / drain.

[0023] In some cases, processes performed during manufacturing (e.g., material deposition and / or etching processes) can negatively impact the active layer of a transistor device. For example, process gases used in the manufacturing process may permeate into the active layer. In some cases, the permeation of process gas particles into the active layer may alter the charge carrier concentration in the channel regions of the active layer. This alteration in the charge carrier concentration in the channel regions of the active layer may negatively impact the operation of the transistor device and / or potentially reduce the reliability of the transistor assembly.

[0024] In the present disclosure of various embodiments, a barrier layer surrounds the active layer to prevent process gases from reaching the active layer. For example, a first barrier layer is located below the active layer, and a second barrier layer is located above the active layer. The barrier layer can prevent process gas particles from reaching the active layer. By preventing process gas atoms from reaching the active layer, the carrier concentration stability in the channel region of the active layer can be improved. As a result, the operation and / or reliability of the transistor device can be improved.

[0025] Figure 1 A cross-sectional view 100 of a transistor device including a barrier layer surrounding an active layer 106 is shown in some embodiments.

[0026] A second dielectric layer 104 is located on the first dielectric layer 102. An active layer 106 is located on the second dielectric layer 104. A third dielectric layer 112 is located on the active layer 106. A first source / drain 108 and a second source / drain 110 extend to the active layer 106 through the third dielectric layer 112. In some embodiments, the active layer 106 comprises silicon, amorphous silicon, polycrystalline silicon, copper oxide, tin oxide, indium oxide, indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), or some other suitable material.

[0027] Gate 116 is located on a first side of active layer 106 (e.g., on active layer 106). Gate dielectric layer 114 is located directly between gate 116 and active layer 106. Gate 116 and gate dielectric layer 114 are located directly between first source / drain 108 and second source / drain 110. In some embodiments, a channel region (not labeled) of active layer 106 extends from first source / drain 108 to second source / drain 110.

[0028] The transistor device includes a barrier layer 120 on a second side of the active layer 106 (e.g., below the active layer 106). For example, the barrier layer 120 is located directly between the first dielectric layer 102 and the second dielectric layer 104. The transistor device includes another barrier layer (e.g., barrier layer 122 and / or barrier layer 124) on a first side of the active layer 106 (e.g., on the active layer 106). For example, in some embodiments, the transistor device includes a barrier layer 122 on a first side of the gate 116 (e.g., below the gate 116) and directly located between the gate 116 and the gate dielectric layer 114. In some embodiments, the transistor device optionally includes a barrier layer 124 on a second side of the gate 116 (e.g., on the gate 116). In some embodiments, the transistor device includes both barrier layers 122 and 124.

[0029] Barrier layers 120, 122, and 124 can prevent process gas atoms from reaching the active layer 106. Therefore, the stability of carrier concentration in the channel region (unlabeled) or the active layer 106 can be improved. Consequently, the operation and / or reliability of the transistor device can be improved.

[0030] In some embodiments, the active layer 106 comprises a semiconductor (e.g., silicon or some other suitable material), and the transistor device comprises a first source / drain region 126 and a second source / drain region 128 located directly beneath a first source / drain 108 and a second source / drain 110, respectively, in the active layer 106. Depending on the context, the source / drain region may refer individually or collectively to a source or a drain. The source / drain regions 126, 128 are doped regions of the active layer 106, wherein the source / drain regions 126, 128 have a first doping type (e.g., n-type or p-type), and the active layer 106 has a second doping type (e.g., p-type or n-type) different from the first doping type. In such embodiments, a channel region (not labeled) of the active layer 106 extends from the first source / drain region 126 to the second source / drain region 128.

[0031] In some embodiments, the transistor device optionally includes a gate 132 (shown in dashed form) on a second side of the active layer 106 (e.g., under the active layer 106) and no gate 116. The gate 132 is located between a sidewall and a first dielectric layer 102. A second dielectric layer 104 forms a gate dielectric layer between the gate 132 and the active layer 106. A third dielectric layer 112 extends between source / drain electrodes 108, 110 (e.g., replacing the gate 116). A barrier layer 124 is on a first side of the active layer 106 (e.g., on the active layer 106) and extends along the third dielectric layer 112. The transistor device includes another barrier layer (e.g., barrier layer 120 and / or barrier layer 134) on a second side of the active layer 106 (e.g., under the active layer 106). For example, in some embodiments, the transistor device includes a barrier layer 120 on the first side or gate 132 and directly between the gate 132 and the second dielectric layer 104 (e.g., the gate dielectric layer). In some embodiments, the transistor device includes a barrier layer 134 on the second side or gate 132. In some embodiments, the transistor device includes both barrier layer 120 and barrier layer 134.

[0032] Figure 2 , 4 Numbers 6, 8, and 10 respectively show Figure 1 Cross-sectional views 200, 400, 600, 800, 1000 of various embodiments of the transistor device, wherein the gate 116 is on the active layer 106. Figure 3 , 5 Numbers 7, 9, and 11 respectively show Figure 2 , 4 The corresponding top views of transistor devices 6, 8, and 10 are 300, 500, 700, 900, 1100, 500, 700, 900, and 1100. In some embodiments, Figure 2 The sectional view 200 can be along Figure 3 The line A-A', Figure 4 The sectional view 400 can be along Figure 5 The line B-B', Figure 6 The sectional view 600 can be along Figure 7 The line C-C', Figure 8 The sectional view 800 can be along Figure 9 The line D-D', and Figure 10 The sectional view 1000 can be along Figure 11 The line E-E'. To clearly illustrate the layers below, the third dielectric layer 112 is not shown. Figure 3 , 5 As shown in 7, 9, and 11. The barrier layer 120 is... Figure 3 , 57, 9, and 11 are displayed with "dashed lines" (e.g., dashed lines).

[0033] exist Figure 2-11 In the illustrated embodiment, a barrier layer 120 is located between a first dielectric layer 102 and a second dielectric layer 104. The barrier layer 120 is perpendicularly spaced from the active layer 106 (e.g., along direction 101z). The barrier layer 120 has a width (e.g., along direction 101x) and length (e.g., along direction 101y) similar to the active layer 106. Source / drain electrodes 108, 110 and gate electrode 116 extend along direction 101y.

[0034] In some embodiments (e.g., such as) Figure 2 Sectional view 200 and Figure 3 As shown in the corresponding top view 300, the transistor device includes a barrier layer 122 directly located between a gate 116 and a gate dielectric layer 114. The barrier layer 122 extends laterally along the bottom surface 116a of the gate 116 to a second sidewall 116c of the gate 116 (e.g., along direction 101x). A third dielectric layer 112 extends along the sidewalls 116b, 116c of the gate 116 and the sidewall of the barrier layer 122 to the sidewall of the gate dielectric layer 114. The barrier layer 122 is perpendicularly spaced from the active layer 106 (e.g., along direction 101z). The barrier layer 122 has a width similar to the width of the gate 116 (e.g., along direction 101x). The barrier layer 122 has a length similar to the length of the active layer 106 (e.g., along direction 101y). The barrier layer 122 in… Figure 3 Displayed as a "dashed line".

[0035] In some embodiments (e.g., such as) Figure 4 Sectional view 400 and Figure 5 As shown in the corresponding top view 500, the barrier layer 122 extends laterally (e.g., along direction 101x) along the bottom surface 116a of the gate 116 and vertically (e.g., along direction 101z) along the first sidewall 116b and the second sidewall 116c of the gate 116. A portion of the barrier layer 122 is located in… Figure 5 Displayed as a "dashed line".

[0036] In some embodiments (e.g., such as) Figure 6 Sectional view 600 and Figure 7As shown in the corresponding top view 700, the transistor device includes a barrier layer 124 on a gate 116. The barrier layer 124 extends laterally (e.g., along direction 101x) along the top surface 116d of the gate 116 and along the top surface 112a of the third dielectric layer 112. Source / drain electrodes 108, 110 extend through the barrier layer 124. The transistor device does not have a barrier layer 122, such that the gate 116 directly contacts the gate dielectric layer 114. The barrier layer 124 has a width (e.g., along direction 101x) and length (e.g., along direction 101y) similar to the width and length of the active layer 106. The barrier layer 124... Figure 7 It is displayed in the form of a "dashed line".

[0037] In some embodiments (e.g., such as) Figure 8 800 sectional view and Figure 9 As shown in the corresponding top view 900, the barrier layer 124 extends laterally along the top surface 116d of the gate 116, extends vertically along the sidewalls 116b and 116c of the gate 116 (directly located between the gate 116 and the third dielectric layer 112), extends vertically along the sidewalls 114a and 114b of the gate dielectric layer 114 (directly located between the gate dielectric layer 114 and the third dielectric layer 112), and extends laterally along the top surface 106a of the active layer 106 (directly located between the third dielectric layer 112 and the active layer 106). Source / drain electrodes 108 and 110 extend through the barrier layer 124 to the active layer 106. A portion of the barrier layer 124 is located in… Figure 9 Displayed as a "dashed line".

[0038] In some embodiments (e.g., such as) Figure 10 Sectional view 1000 and Figure 11 As shown in the corresponding top view 1100, the transistor device includes both a barrier layer 122 and a barrier layer 124. The barrier layer 124 extends along the sidewalls 122a and 122b of the barrier layer 122. A portion of the barrier layer 122 and the barrier layer 124 are located in… Figure 11 It is shown in the middle with a "dashed line".

[0039] exist Figure 2-11In the illustrated embodiments, barrier layer 122 comprises a material different from barrier layers 120 and 124. For example, in some embodiments, barrier layer 120 comprises a first oxide, barrier layer 124 comprises a second oxide, and barrier layer 122 comprises a third oxide different from the first and second oxides. In some embodiments, barrier layer 122 comprises indium oxide, indium tin oxide, indium zinc oxide, or some other suitable material. In some embodiments, barrier layer 120 and / or barrier layer 124 comprises any one of silicon nitride, aluminum oxide, hafnium alumina, zirconium alumina, or some other suitable material. In some embodiments, the thickness (e.g., along direction 101z) of barrier layer 120, barrier layer 122, and barrier layer 124 ranges from about 1 nanometer to about 10 nanometers, from about 2 nanometers to about 9 nanometers, less than 10 nanometers, or some other suitable range.

[0040] In some embodiments, the active layer 106 comprises silicon, amorphous silicon, polycrystalline silicon, copper oxide, tin oxide, indium oxide, indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), or some other suitable material and has a thickness ranging from about 1 nanometer to about 10 nanometers, about 2 nanometers to about 9 nanometers, or some other suitable range (e.g., along direction 101z).

[0041] In some embodiments, the gate 116 comprises polysilicon, silicide, metal (e.g., copper, tungsten, tungsten nitride, titanium nitride or similar), or some other suitable material, and has a width of less than 50 (e.g. along direction 101x), less than 30 nanometers, or some other suitable width.

[0042] In some embodiments, the first dielectric layer 102 and / or the second dielectric layer 104 comprises silicon oxide, silicon nitride, aluminum oxide, silicon carbide, silicon carbide, or some other suitable material. In some embodiments, the first dielectric layer 102 and / or the second dielectric layer 104 has a thickness (e.g., along direction 101z) greater than the thickness of the barrier layers 120, 122, 124. In some embodiments, the thickness of the first dielectric layer 102 and / or the second dielectric layer 104 ranges from about 10 nanometers to about 100 nanometers, from about 20 nanometers to about 80 nanometers, or some other suitable range.

[0043] In some embodiments, the gate dielectric layer 114 comprises silicon oxide, aluminum oxide, hafnium oxide, a composite of hafnium oxide and zirconium oxide, a composite of hafnium oxide and aluminum oxide, a composite of hafnium oxide and lanthanum oxide, a composite of hafnium oxide and silicon oxide, a composite of hafnium oxide and strontium oxide, or some other suitable material. In some embodiments, the gate dielectric layer 114 has a thickness greater than the thickness of the barrier layers 120, 122, 124 (e.g., along direction 101z). In some embodiments, the thickness of the gate dielectric layer 114 ranges from about 10 nanometers to about 100 nanometers, from about 20 nanometers to about 80 nanometers, or some other suitable range.

[0044] Figure 12 A cross-sectional view 1200 of some embodiments of an integrated chip is shown, the integrated chip including interconnect structures 1206 disposed on a semiconductor substrate 1202. Figure 10 Transistor devices.

[0045] Multiple front-end transistor devices 1204 are arranged along a semiconductor substrate 1202. Interconnect structures 1206 are located on the semiconductor substrate 1202. Interconnect structures 1206 include multiple dielectric layers 1208 and multiple conductive interconnects (e.g., conductive contacts 1216, wires 1218, vias 1220, etc.) extending through the dielectric layers 1208. Some of the conductive interconnects of interconnect structures 1206 are coupled to the front-end transistor devices 1204.

[0046] The interconnecting structure 1206 also includes forming Figure 10 The transistor device comprises dielectric layers 102, 104, 112, 114, an active layer 106, source / drain layers 108, 110, a gate layer 116, and barrier layers 120, 122, 124. A contact 1216 of an interconnect structure 1206 contacts the source / drain layers 108, 110, and the gate layer 116 of the transistor assembly. Vias 1220 and wires 1218 of the interconnect structure 1206 couple some transistor devices to the front end of the transistor device 120.

[0047] Figure 13 It shows Figure 1 A cross-sectional view 1300 of some embodiments of a transistor device, wherein the gate 312 is under the active layer 106. Figure 14 A cross-sectional view 1400 is shown for some embodiments of an integrated chip, which includes interconnect structures 1206 disposed on a semiconductor substrate 1202. Figure 13 Transistor devices.

[0048] A gate 132 is located below the active layer 106, and a second dielectric layer 104 (e.g., a gate dielectric layer) is located between the gate 132 and the active layer 106. A barrier layer 124 is located on the active layer 106. Another barrier layer (e.g., barrier layer 120 and / or barrier layer 134) is located below the active layer 106. In some embodiments, the transistor device includes a barrier layer 120 (e.g., a gate dielectric layer) located directly between the gate 132 and the second dielectric layer 104. In some embodiments, the transistor device includes a barrier layer 134 extending below the gate 132 along the bottom surface of the gate 132 and the bottom surface of the first dielectric layer 102. In some embodiments, the transistor device includes both barrier layer 120 and barrier layer 134.

[0049] In some embodiments, the barrier layer 120 extends laterally along the top surface of the gate 132 and along the top surface of the first dielectric layer 102. In some other embodiments, the barrier layer 120 extends laterally along the top surface of the gate 132, extends vertically along the sidewalls of the gate 132, and extends laterally along the bottom surface of the first dielectric layer 102 (e.g., as shown in the dashed region 1302). In some such embodiments, the barrier layer 120 extends along the top surface of the barrier layer 134.

[0050] exist Figure 13 and 14 In the illustrated embodiments, barrier layer 120 comprises a material different from barrier layers 124 and 134. For example, in some embodiments, barrier layer 124 comprises a first oxide, barrier layer 134 comprises a second oxide, and barrier layer 120 comprises a third oxide different from the first and second oxides. In some embodiments, barrier layer 120 comprises indium oxide, indium tin oxide, indium zinc oxide, or some other suitable material. In some embodiments, barrier layer 124 and / or barrier layer 134 comprises any one of silicon nitride, aluminum oxide, hafnium alumina, zirconium alumina, or some other suitable material.

[0051] Figure 15 It shows Figure 1 A cross-sectional view 1500 of some embodiments of a transistor device, wherein the transistor device is configured along a substrate 1502. Figure 16 A cross-sectional view 1600 is shown for some embodiments of an integrated chip, which includes... Figure 15 Transistor devices.

[0052] Substrate 1502 comprises a base semiconductor layer 1504, a base dielectric layer 1506 on the base semiconductor layer 1504, and an active layer 106 on the base dielectric layer 1506. Active layer 106 comprises a semiconductor (e.g., silicon or some other suitable material). In some embodiments, base dielectric layer 1506 comprises a first dielectric layer 102, a second dielectric layer 104, and a barrier layer 120. In some cases, substrate 1502 may be referred to as a semiconductor-on-insulator (SOI) substrate. Barrier layer 122 and / or barrier layer 124 are located on active layer 106.

[0053] The source / drain regions are located in the substrate 1502. For example, the first source / drain region 126 and the second source / drain region 128 are located in the active layer 106 directly below the first source / drain region 108 and the second source / drain region 110, respectively. The source / drain regions 126 and 128 have a first doping type (e.g., n-type or p-type), and the active layer 106 has a second doping type (e.g., p-type or n-type) different from the first doping type.

[0054] In some embodiments, Figure 10 transistor devices (and / or Figure 13 The transistor device is disposed within the interconnect structure 1206 and coupled to the conductive interconnect of the interconnect structure 1206. Figure 15 Transistor devices.

[0055] exist Figure 15 and 16 In the illustrated embodiments, barrier layer 122 comprises a material different from barrier layers 120 and 124. For example, in some embodiments, barrier layer 120 comprises a first oxide, barrier layer 124 comprises a second oxide, and barrier layer 122 comprises a third oxide different from the first and second oxides. In some embodiments, barrier layer 122 comprises indium oxide, indium tin oxide, indium zinc oxide, or some other suitable material. In some embodiments, barrier layer 120 and / or barrier layer 124 comprises any one of silicon nitride, aluminum oxide, hafnium alumina, zirconium alumina, or some other suitable material.

[0056] Figure 17-22 Cross-sectional views 1700-2200 show a method of forming a transistor device, which includes a gate located on an active layer 106 and barrier layers 120, 122 surrounding the active layer. Although Figure 17-22 It is described in relation to the method, but it should be understood that... Figure 17-22 The structures disclosed in the document are not limited to such methods, but can exist independently of the methods.

[0057] like Figure 17As shown in the cross-sectional view 1700, a barrier layer 120 is deposited on the first dielectric layer 102, a second dielectric layer 104 is deposited on the barrier layer 120, and an active layer 106 is deposited on the second dielectric layer 104.

[0058] In some embodiments, the first dielectric layer 102 and / or the second dielectric layer 104 comprise silicon dioxide, silicon nitride, aluminum oxide, silicon carbide, silicon carbide, or some other suitable material, and are deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic deposition.

[0059] In some embodiments, the barrier layer 120 comprises silicon nitride, aluminum oxide, hafnium alumina, zirconium alumina, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0060] In some embodiments, the active layer 106 includes silicon, amorphous silicon, polycrystalline silicon, copper oxide, tin oxide, indium oxide, indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), or some other suitable material and is deposited through a CVD process, a PVD process, an ALD process, or some other suitable process.

[0061] like Figure 18 As shown in the cross-sectional view 1800, a gate dielectric layer 114 is deposited on the active layer 106, a barrier layer 122 is deposited on the gate dielectric layer 114, and a gate layer 1802 is deposited on the barrier layer 122.

[0062] In some embodiments, the gate dielectric layer 114 comprises silicon oxide, aluminum oxide, hafnium oxide, a composite of hafnium oxide and zirconium oxide, a composite of hafnium oxide and aluminum oxide, a composite of hafnium oxide and lanthanum oxide, a composite of hafnium oxide and silicon oxide, a composite of hafnium oxide and strontium oxide, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0063] In some embodiments, the barrier layer 122 comprises indium oxide, indium tin oxide, indium zinc oxide, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0064] In some embodiments, the gate layer 1802 comprises polysilicon, silicide, metal (e.g., copper, tungsten, tungsten nitride, titanium nitride or similar), or some other suitable material and is deposited via a CVD process, PVD process, ALD process, or some other suitable process.

[0065] like Figure 19As shown in the cross-sectional view 1900, the gate layer 1802, the barrier layer 122, and the gate dielectric layer 114 are etched to define the gate 116 and the gate layer 1802, and further define the barrier layer 122 and the gate dielectric layer 114. In some embodiments, a masking layer 1902 is formed on the gate layer 1802, and etching is performed based on the masking layer 1902. In some embodiments, the masking layer 1902 includes photoresist or some other suitable material. In some embodiments, the etching includes a dry etching process (e.g., plasma etching, reactive ion etching, ion beam etching, or similar processes) or some other suitable process.

[0066] like Figure 20 As shown in the cross-sectional view 2000, a third dielectric layer 112 is deposited on the active layer 106 adjacent to the gate 116 on the side opposite to the gate 116. In some embodiments, the third dielectric layer 112 comprises silicon dioxide, silicon nitride, silicon carbide, or some other suitable material and is deposited via a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the third dielectric layer 112 is deposited on the gate 116, and after the deposition of the third dielectric layer 112, a polishing / planarization process (e.g., blanket etch-back process, chemical mechanical polishing / planarization (CMP) process, or similar) is performed on the third dielectric layer 112 to remove the third dielectric layer 112 from the gate 116.

[0067] like Figure 21 As shown in the cross-sectional view 2100, the third dielectric layer 112 is etched to form a first opening 2104 and a second opening 2106 in the third dielectric layer 112. The etching exposes portions of the active layer 106 at the openings 2104 and 2106. In some embodiments, a masking layer 2102 is formed on the third dielectric layer 112 and the gate 116, and etching is performed based on the masking layer 2102. In some embodiments, the masking layer 2102 comprises photoresist or some other suitable material. In some embodiments, the etching comprises a dry etching process or some other suitable process.

[0068] like Figure 22As shown in cross-sectional view 2200, conductive layers (not labeled) are deposited in a first opening 2104 and a second opening 2106 to form a first source / drain 108 and a second source / drain 110, respectively, in the first opening 2104 and the second opening 2106. In some embodiments, the conductive layer (not labeled) comprises a metal (e.g., tungsten, copper, aluminum, or similar materials) or some other suitable material and is deposited via a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the conductive layer (not labeled) is deposited on a third dielectric layer 112 and a gate 116, and after the conductive layer is deposited, a polishing / planarization process is performed on the conductive layer to remove the conductive layer from the third dielectric layer 112 and the gate 116.

[0069] Figure 23-29 Cross-sectional views 2300-2900 are shown for some embodiments of forming a transistor device, the transistor device including barrier layers 120, 122 surrounding the active layer. Although Figure 23-29 It is described in relation to the method, but it should be understood that... Figure 23-29 The structures disclosed in the document are not limited to such methods, but can exist independently of the methods.

[0070] like Figure 23 As shown in cross-sectional view 2300, a barrier layer 120 is deposited on a first dielectric layer 102, a second dielectric layer 104 is deposited on the barrier layer 120, an active layer 106 is deposited on the second dielectric layer 104, and a gate dielectric layer 114 is deposited on the active layer 106. In some embodiments, the barrier layer 120 comprises silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or some other suitable material, and is deposited via CVD, PVD, ALD, or some other suitable process.

[0071] like Figure 24 As shown in the cross-sectional view 2400, the gate dielectric layer 114 is etched to further define the gate dielectric layer 114 on the active layer 106. The etching exposes portions of the active layer 106 on the opposite sides of the gate dielectric layer 114. In some embodiments, a masking layer 2402 is formed on the gate dielectric layer 114, and etching is performed based on the masking layer 2402. In some embodiments, the masking layer 2402 comprises photoresist or some other suitable material. In some embodiments, the etching comprises a dry etching process or some other suitable process.

[0072] like Figure 25 As shown in the cross-sectional view 2500, a third dielectric layer 112 is deposited on the active layer 106 and the gate dielectric layer 114.

[0073] like Figure 26As shown in the cross-sectional view 2600, the third dielectric layer 112 is etched to form an opening 2604 in the third dielectric layer 112. The gate dielectric layer 114 is etched to expose the opening 2604. In some embodiments, a masking layer 2602 is formed on the third dielectric layer 112, and etching is performed based on the masking layer 2602. In some embodiments, the masking layer 2602 comprises photoresist or some other suitable material. In some embodiments, the etching comprises a dry etching process or some other suitable process.

[0074] like Figure 27 As shown in cross-sectional view 2700, a barrier layer 122 is deposited on a third dielectric layer 112 and in an opening 2604 on a gate dielectric layer 114. A gate layer 2702 is deposited on the barrier layer 122 and in the opening 2604.

[0075] In some embodiments, the barrier layer 122 comprises indium oxide, indium tin oxide, indium zinc oxide, or some other suitable material, and is deposited via a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the gate layer 2702 comprises polysilicon, silicide, metal (e.g., copper, tungsten, tungsten nitride, titanium nitride, or similar materials), or some other suitable material, and is deposited via a CVD process, a PVD process, an ALD process, or some other suitable process.

[0076] like Figure 28 As shown in the cross-sectional view 2800, a polishing / planarization process is performed on the gate layer 2702 and the barrier layer 122 to remove the gate layer 2702 and the barrier layer 122 from the third dielectric layer 112 and to form the gate 116 from the gate layer 2702. In some embodiments, the polishing / planarization process includes a blanket etch-back process, a chemical mechanical polishing / planarization (CMP) process, or some other suitable process.

[0077] like Figure 29 As shown in the cross-sectional view 2900, a first source / drain 108 and a second source / drain 110 are formed within the third dielectric layer 112 and on the active layer 106. In some embodiments, forming the source / drain 108, 110 includes etching the third dielectric layer 112 to form an opening in the third dielectric layer 112, depositing a conductive layer in the opening, and performing a polishing / planarization process on the conductive layer after depositing the conductive layer (e.g., as per [reference]). Figure 21 , 22 The above).

[0078] Figures 30-33 Cross-sectional views 3000-3300 show some embodiments of a method for forming a transistor device, the transistor device including a gate located on an active layer 106 and barrier layers 120, 124 surrounding the active layer. Although Figures 30-33It is described in relation to the method, but it should be understood that... Figures 30-33 The structures disclosed in the document are not limited to such methods, but can exist independently of the methods.

[0079] like Figure 30 As shown in the cross-sectional view 3000, a barrier layer 120 is deposited on the first dielectric layer 102, a second dielectric layer 104 is deposited on the barrier layer 120, an active layer 106 is deposited on the second dielectric layer 104, a gate dielectric layer 114 is deposited on the active layer 106, and a gate layer 3002 is deposited on the gate dielectric layer 114.

[0080] In some embodiments, the barrier layer 120 comprises silicon nitride, aluminum oxide, hafnium alumina, zirconium alumina, or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes. In some embodiments, the gate layer 3002 comprises polysilicon, silicide, metal (e.g., copper, tungsten, tungsten nitride, titanium nitride, or similar materials), or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes.

[0081] like Figure 31 As shown in the cross-sectional view 3100, the gate layer 3002 and the gate dielectric layer 114 are etched to define the gate 116 and the gate layer 3002, and further define the gate dielectric layer 114. In some embodiments, a masking layer 3102 is formed on the gate layer 3002, and etching is performed based on the masking layer 3102. In some embodiments, the masking layer 3102 comprises photoresist or some other suitable material. In some embodiments, the etching comprises a dry etching process or some other suitable process.

[0082] like Figure 32 As shown in the cross-sectional view 3200, a third dielectric layer 112 is deposited on the active layer 106 next to the gate 116 on the side opposite to the gate 116. In some embodiments, the third dielectric layer 112 is deposited on the gate 116, and a polishing / planarization process is performed on the third dielectric layer 112 to remove the third dielectric layer 112 from the gate 116 after the third dielectric layer 112 has been deposited.

[0083] In addition, such as Figure 32 As shown in the cross-sectional view 3200, a barrier layer 124 is deposited on the third dielectric layer 112 and the gate 116. In some embodiments, the barrier layer 124 comprises silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0084] like Figure 33As shown in cross-sectional view 3300, a first source / drain 108 and a second source / drain 110 are formed within the barrier layer 124 and the third dielectric layer 112, and on the active layer 106. In some embodiments, forming the source / drain 108, 110 includes etching the barrier layer 124 and the third dielectric layer 112 to form openings therein, depositing a conductive layer in the openings, and performing a grinding / planarization process on the conductive layer after deposition (e.g., as per [reference]). Figure 21 , 22 The above).

[0085] Figure 34-37 Cross-sectional views 3400-3700 show some embodiments of a method for forming a transistor device, the transistor device including a gate located on an active layer 106 and barrier layers 120, 124 surrounding the active layer. Although Figure 34-37 It is described in relation to the method, but it should be understood that... Figure 34-37 The structures disclosed in the document are not limited to such methods, but can exist independently of the methods.

[0086] like Figure 34 As shown in the cross-sectional view 3400, a barrier layer 120 is deposited on the first dielectric layer 102, a second dielectric layer 104 is deposited on the barrier layer 120, an active layer 106 is deposited on the second dielectric layer 104, a gate dielectric layer 114 is deposited on the active layer 106, and a gate layer 3402 is deposited on the gate dielectric layer 114.

[0087] In some embodiments, the barrier layer 120 comprises silicon nitride, aluminum oxide, hafnium alumina, zirconium alumina, or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes. In some embodiments, the gate layer 3402 comprises polysilicon, silicide, metal (e.g., copper, tungsten, tungsten nitride, titanium nitride, or similar materials), or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes.

[0088] like Figure 35 As shown in the cross-sectional view 3500, the gate layer 3402 and the gate dielectric layer 114 are etched to define the gate 116 and the gate layer 3402 and further define the gate dielectric layer 114. In some embodiments, a masking layer 3502 is formed on the gate layer 3402, and etching is performed based on the masking layer 3502. In some embodiments, the masking layer 3502 includes photoresist or some other suitable material. In some embodiments, the etching includes a dry etching process or some other suitable process.

[0089] like Figure 36As shown in cross-sectional view 3600, a barrier layer 124 is deposited on the gate 116, along the sidewalls of the gate 116, along the sidewalls of the gate dielectric layer 114, and on the active layer 106. In some embodiments, the barrier layer 124 comprises silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or some other suitable material, and is deposited via a CVD process, a PVD process, an ALD process, or some other suitable process.

[0090] like Figure 37 As shown in the cross-sectional view 3700, a third dielectric layer 112 is deposited on the barrier layer 124 next to the gate 116 on the side opposite to the gate 116. Furthermore, a first source / drain 108 and a second source / drain 110 are formed within the third dielectric layer 112 and the barrier layer 124, and on the active layer 106. In some embodiments, forming the source / drain 108, 110 includes etching the third dielectric layer 112 and the barrier layer 124 to form openings therein, depositing a conductive layer in the openings, and performing a polishing / planarization process on the conductive layer after deposition (e.g., as per [reference to...]). Figure 21 , 22 The above).

[0091] Figure 38-41 Cross-sectional views 3800-4100 illustrate some embodiments of a method for forming a transistor device, the transistor device including a gate located on an active layer and barrier layers 120, 122, 124 surrounding the active layer. Although Figure 38-41 It is described in relation to the method, but it should be understood that... Figure 38-41 The structures disclosed in the document are not limited to such methods, but can exist independently of the methods.

[0092] like Figure 38 As shown in the cross-sectional view 3800, a barrier layer 120 is deposited on the first dielectric layer 102, a second dielectric layer 104 is deposited on the barrier layer 120, an active layer 106 is deposited on the second dielectric layer 104, a gate dielectric layer 114 is deposited on the active layer 106, a barrier layer 122 is deposited on the gate dielectric layer 114, and a gate dielectric layer 114 is deposited on the gate layer 3802.

[0093] In some embodiments, barrier layer 120 comprises silicon nitride, aluminum oxide, hafnium alumina, zirconium alumina, or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes. In some embodiments, barrier layer 122 comprises indium oxide, indium tin oxide, indium zinc oxide, or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes. In some embodiments, gate layer 3802 comprises polysilicon, silicide, metal (e.g., copper, tungsten, tungsten nitride, titanium nitride, or similar materials), or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes.

[0094] like Figure 39 As shown in the cross-sectional view 3900, the gate layer 3802, the barrier layer 122, and the gate dielectric layer 114 are etched to define the gate 116 and the gate layer 3802, and further define the barrier layer 122 and the gate dielectric layer 114. In some embodiments, a masking layer 3902 is formed on the gate layer 3802, and etching is performed based on the masking layer 3902. In some embodiments, the masking layer 3902 includes photoresist or some other suitable material. In some embodiments, the etching includes a dry etching process or some other suitable process.

[0095] like Figure 40 As shown in cross-sectional view 4000, a barrier layer 124 is deposited on the gate 116, along the sidewalls of the gate 116, along the sidewalls of the barrier layer 122, along the sidewalls of the gate dielectric layer 114, and on the active layer 106. In some embodiments, the barrier layer 124 comprises silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or some other suitable material, and is deposited via a CVD process, a PVD process, an ALD process, or some other suitable process.

[0096] like Figure 41 As shown in the cross-sectional view 4100, a third dielectric layer 112 is deposited on the barrier layer 124 next to the gate 116 on the opposite side of the gate 116. Furthermore, a first source / drain 108 and a second source / drain 110 are formed within the third dielectric layer 112 and the barrier layer 124, and on the active layer 106. In some embodiments, forming the source / drain 108, 110 includes etching the third dielectric layer 112 and the barrier layer 124 to form openings therein, depositing a conductive layer in the openings, and performing a polishing / planarization process on the conductive layer after deposition (e.g., as per [reference to...]). Figure 21 , 22 The above).

[0097] exist Figure 17-41 In some embodiments of the method shown, along the semiconductor substrate (e.g. Figure 12 Multiple front-end transistor devices (e.g., on a semiconductor substrate 1202) are formed thereon. Figure 12 The front-end transistor device 1204), and in the interconnect structure (e.g. Figure 12 A transistor device is formed on the front-end transistor within 1206. Furthermore, in Figure 17-41 In some embodiments of the method shown, the first dielectric layer 102 is deposited on one or more conductive interconnects of the dielectric layer and / or interconnect structure (e.g., Figure 12 (Interconnected structure 1206).

[0098] Figure 42 Flowcharts of some embodiments of a transistor device formation method 4200 are shown, the transistor device including a barrier layer surrounding an active layer. While method 4200 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown need to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0099] At block 4202, a first barrier layer is deposited on the first dielectric layer. Figure 17 , 23 Sections 1700, 2300, 3000, 3400, and 3800 respectively show cross-sectional views of some embodiments corresponding to block 4202.

[0100] At block 4204, a second dielectric layer is deposited on the first barrier layer. Figure 17 , 23 Sections 1700, 2300, 3000, 3400, and 3800 respectively show cross-sectional views of some embodiments corresponding to block 4204.

[0101] At block 4206, an active layer is deposited on the second dielectric layer. Figure 17 , 23 Sections 1700, 2300, 3000, 3400, and 3800 respectively show cross-sectional views of some embodiments corresponding to block 4206.

[0102] At block 4208, a gate dielectric layer is deposited on the active layer. Figure 18 , 2330, 34, and 38 show cross-sectional views 1800, 2300, 3000, 3400, and 3800 of some embodiments corresponding to block 4208, respectively.

[0103] At block 4210, a second barrier layer is deposited on the gate dielectric layer. Figure 18 , 27 Sections 1800, 2700, and 3800 respectively show cross-sectional views of some embodiments corresponding to block 4210.

[0104] At block 4212, a gate is formed on the second barrier layer. Figure 19 , 28 Sections 1900, 2800, 3100, 3500, and 3900 respectively show cross-sectional views of some embodiments corresponding to block 4212.

[0105] At block 4214, a third barrier layer is deposited on the gate. Figure 32 , 36 Sections 3200, 3600, and 4000 respectively show cross-sectional views of some embodiments corresponding to block 4214.

[0106] At block 4216, a first source / drain and a second source / drain are formed on the active layer on the opposite side of the gate. Figure 22 , 29 Sections 2200, 2900, 3300, 3700, and 4100 respectively show cross-sectional views of some embodiments corresponding to block 4216.

[0107] Figures 43-47 Cross-sectional views 4300-4700 show some other embodiments of a method for forming a transistor device, the transistor device including barrier layers 120, 124, 134 surrounding an active layer 106. Although Figures 43-47 It is described in relation to the method, but it should be understood that... Figures 43-47 The structures disclosed in the document are not limited to such methods, but can exist independently of the methods.

[0108] like Figure 43 As shown in the cross-sectional view 4300, a first dielectric layer 102 is deposited on the barrier layer 134. In some embodiments, the barrier layer 134 comprises silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or some other suitable material, and is deposited via a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the barrier layer 134 is deposited on a dielectric layer or an interconnect structure (e.g., Figure 14 (Interconnected structure 1206).

[0109] like Figure 44 As shown in the cross-sectional view 4400, the first dielectric layer 102 is etched to form an opening 4404 in the first dielectric layer 102. A portion of the barrier layer 134 exposed at the opening 4404 is etched. In some embodiments, a masking layer 4402 is formed on the first dielectric layer 102, and etching is performed based on the masking layer 4402. In some embodiments, the masking layer 4402 comprises photoresist or some other suitable material. In some embodiments, the etching comprises a dry etching process or some other suitable process.

[0110] like Figure 45 As shown in the cross-sectional view 4500, a gate 132 is formed on a barrier layer 134 (between the sidewalls of the first dielectric layer 102) in an opening 4404. In some embodiments, the gate 132 is formed by depositing a gate layer (not labeled) comprising polysilicon, silicide, metal, or some other suitable material on the first dielectric layer 102 and the opening 4404, removing the gate layer therefrom by performing a grinding / planarization process on the gate layer, and forming the gate 132 from the gate layer.

[0111] like Figure 46 As shown in the cross-sectional view 4600, a barrier layer 120 is deposited on the first dielectric layer 102 and the gate 132, a second dielectric layer 104 (e.g., the gate dielectric layer) is deposited on the barrier layer 120, an active layer 106 is deposited on the second dielectric layer 104, a third dielectric layer 112 is deposited on the active layer 106, and a barrier layer 124 is deposited on the third dielectric layer 112.

[0112] In some embodiments, barrier layer 120 comprises indium oxide, indium tin oxide, indium zinc oxide, or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes. In some embodiments, barrier layer 124 comprises silicon nitride, aluminum oxide, hafnium alumina, zirconium alumina, or other suitable materials, and is deposited via CVD, PVD, ALD, or other suitable processes.

[0113] like Figure 47 As shown in cross-sectional view 4700, a first source / drain 108 and a second source / drain 110 are formed within the third dielectric layer 112 and the barrier layer 124, and on the active layer 106. In some embodiments, forming the source / drain 108, 110 includes etching the barrier layer 124 and the third dielectric layer 112 to form openings therein, depositing a conductive layer in the openings, and performing a grinding / planarization process on the conductive layer after deposition (e.g., as per [reference]). Figure 21 , 22 The above).

[0114] exist Figures 43-47In some embodiments of the method shown, along the semiconductor substrate (e.g., Figure 14 Multiple front-end transistor devices (e.g., on a semiconductor substrate 1202) are formed thereon. Figure 14 The front-end transistor device 1204), and in the interconnect structure (e.g., Figure 14 A transistor device is formed on the front-end transistor within the interconnect structure 1206.

[0115] Figure 48 Flowcharts of some embodiments of a transistor device formation method 4800 are shown, the transistor device including a barrier layer surrounding an active layer. While method 4800 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown need to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0116] At block 4802, a first dielectric layer is deposited on the first barrier layer. Figure 43 A cross-sectional view 4300 corresponding to some embodiments of block 4802 is shown.

[0117] At block 4804, the first dielectric layer is etched to form an opening in the first dielectric layer. Figure 44 A cross-sectional view 4400 corresponding to some embodiments of block 4804 is shown.

[0118] At block 4806, a gate is formed in the opening. Figure 45 A cross-sectional view 4500 corresponding to some embodiments of block 4806 is shown.

[0119] At block 4808, a second barrier layer is deposited on the gate. Figure 46 A cross-sectional view 4600 corresponding to some embodiments of block 4808 is shown.

[0120] At block 4810, a second dielectric layer (e.g., a gate dielectric layer) is deposited on the second barrier layer. Figure 46 A cross-sectional view 4600 corresponding to some embodiments of block 4810 is shown.

[0121] At block 4812, an active layer is deposited on the second dielectric layer. Figure 46 A cross-sectional view 4600 corresponding to some embodiments of block 4812 is shown.

[0122] At block 4814, a third dielectric layer is deposited on the active layer. Figure 46 A cross-sectional view 4600 corresponding to some embodiments of block 4814 is shown.

[0123] At block 4816, deposit a third barrier layer on the third dielectric layer. Figure 46 A cross-sectional view 4600 corresponding to some embodiments of block 4816 is shown.

[0124] At block 4818, a first source / drain and a second source / drain are formed within the third dielectric layer and the third barrier layer, as well as on the active layer. Figure 47 A cross-sectional view 4700 corresponding to some embodiments of block 4818 is shown.

[0125] Figures 49-53 Cross-sectional views 4900-5300 show some embodiments of a method for forming a transistor device along a substrate, the transistor device including barrier layers 120, 122, 124 surrounding an active layer 106 on the substrate. Although Figures 49-53 It is described in relation to the method, but it should be understood that... Figures 49-53 The structures disclosed in the document are not limited to such methods, but can exist independently of the methods.

[0126] like Figure 49 As shown in cross-sectional view 4900, a gate dielectric layer 114 is deposited on a substrate 1502, a barrier layer 122 is deposited on the gate dielectric layer 114, and a gate layer 4902 is deposited on the barrier layer 122. In some embodiments, the substrate 1502 is formed by forming a base dielectric layer 1506 between a base semiconductor layer 1504 and an active layer 106. In some embodiments, the base dielectric layer 1506 includes a barrier layer 120, a first dielectric layer 102, and a second dielectric layer 104.

[0127] In some embodiments, the base semiconductor layer 1504 comprises silicon or some other suitable material. In some embodiments, the barrier layer 120 comprises silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or some other suitable material. In some embodiments, the barrier layer 122 comprises indium oxide, indium tin oxide, indium zinc oxide, or some other suitable material, and is deposited via CVD, PVD, ALD, or some other suitable process. In some embodiments, the gate layer 4902 comprises polysilicon, silicide, metal (e.g., copper, tungsten, tungsten nitride, titanium nitride, or similar materials) or some other suitable material and is deposited via CVD, PVD, ALD, or some other suitable process.

[0128] like Figure 50As shown in the cross-sectional view 5000, the gate layer 4902, the barrier layer 122, and the gate dielectric layer 114 are etched to define the gate 116 and the gate layer 4902, and further define the barrier layer 122 and the gate dielectric layer 114. In some embodiments, a masking layer 5002 is formed on the gate layer 4902, and etching is performed based on the masking layer 5002. In some embodiments, the masking layer 5002 comprises photoresist or some other suitable material. In some embodiments, the etching comprises a dry etching process or some other suitable process.

[0129] like Figure 51 As shown in the cross-sectional view 5100, portions of the active layer 106 are doped to form a first source / drain region 126 and a second source / drain region 128 in the active layer 106. In some embodiments, doping the active layer 106 includes performing an ion implantation process or some other suitable doping process. The source / drain regions 126, 128 are formed to have a different doping type than the active layer 106.

[0130] like Figure 52 As shown in cross-sectional view 5200, a barrier layer 124 is deposited on the gate 116, along the sidewalls of the gate 116, along the sidewalls of the barrier layer 122, along the sidewalls of the gate dielectric layer 114, and on the active layer 106. In some embodiments, the barrier layer 124 comprises silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or some other suitable material, and is deposited via a CVD process, a PVD process, an ALD process, or some other suitable process.

[0131] like Figure 53 As shown in the cross-sectional view 5300, a third dielectric layer 112 is deposited on the barrier layer 124 next to the gate 116 on the side opposite to the gate 116. Furthermore, a first source / drain 108 and a second source / drain 110 are formed within the third dielectric layer 112 and the barrier layer 124, and on the active layer 106. In some embodiments, forming the source / drain 108, 110 includes etching the third dielectric layer 112 and the barrier layer 124 to form openings therein, depositing a conductive layer in the openings, and performing a polishing / planarization process on the conductive layer after deposition (e.g., as per [reference to...]). Figure 21 , 22 The above).

[0132] exist Figures 49-53 In some embodiments of the method shown, the interconnect structure (e.g., Figure 16 The interconnect structure 1206 is formed on the transistor device, and one or more additional transistor devices are formed on the interconnect structure (e.g., such as...). Figure 16 (as shown) inside.

[0133] Figure 54Flowcharts of some embodiments of a method 5400 for forming a transistor device are shown, the transistor device including a barrier layer surrounding an active layer. While method 5400 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown need to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0134] At block 5402, a first barrier layer is formed within the base dielectric layer of the substrate. Figure 49 A cross-sectional view 4900 corresponding to some embodiments of block 5402 is shown.

[0135] At block 5404, an active layer of the substrate is formed on the base dielectric layer of the substrate. Figure 49 A cross-sectional view 4900 corresponding to some embodiments of block 5404 is shown.

[0136] At block 5406, a gate dielectric layer is deposited on the active layer of the substrate. Figure 49 A cross-sectional view 4900 corresponding to some embodiments of block 5406 is shown.

[0137] At block 5408, a second barrier layer is deposited on the gate dielectric layer. Figure 49 A cross-sectional view 4900 corresponding to some embodiments of block 5408 is shown.

[0138] At block 5410, a gate layer is deposited on the second barrier layer. Figure 49 A cross-sectional view 4900 corresponding to some embodiments of block 5410 is shown.

[0139] At block 5412, the gate layer, the second barrier layer, and the gate dielectric layer are etched to form the gate from the gate layer. Figure 50 A cross-sectional view 5000 corresponding to some embodiments of block 5412 is shown.

[0140] At block 5414, a first source / drain region and a second source / drain region are formed in the active layer of the substrate on the opposite side of the gate. Figure 51 A cross-sectional view 5100 corresponding to some embodiments of block 5414 is shown.

[0141] At block 5416, a third barrier layer is deposited on the gate. Figure 52 A cross-sectional view 5200 corresponding to some embodiments of block 5416 is shown.

[0142] At block 5418, a first source / drain and a second source / drain are formed on the active layer on the opposite side of the gate. Figure 53 A cross-sectional view 5300 corresponding to some embodiments of block 5418 is shown.

[0143] Therefore, this utility model embodiment relates to an integrated chip including a transistor device, the transistor device including a barrier layer surrounding an active layer to block harmful gases from reaching the active layer.

[0144] Therefore, in some embodiments, this invention relates to an integrated chip including an active layer. A first source / drain and a second source / drain are located on the upper surface of the active layer. A gate is located on a first side of the active layer and between the first source / drain and the second source / drain. A gate dielectric layer is located between the gate and the active layer. A first barrier layer is located on a second side of the active layer and spaced apart from the active layer, the second side being opposite to the first side of the active layer. A second barrier layer is located on the first side of the active layer and spaced apart from the active layer, and extends along the gate.

[0145] In some embodiments, the second barrier layer is located directly between the gate and the gate dielectric layer.

[0146] In some embodiments, the second barrier layer extends along the sidewall of the gate.

[0147] In some embodiments, the gate is located directly between the second barrier layer and the gate dielectric layer.

[0148] In some embodiments, the second barrier layer extends along the sidewall of the gate, the sidewall of the gate dielectric layer, and the active layer.

[0149] In some embodiments, it further includes a third barrier layer located directly between the gate and the gate dielectric layer.

[0150] In some embodiments, the gate and the second barrier layer are on the active layer, the first barrier layer is below the active layer, and the active layer and the first barrier layer are spaced apart on a transistor device disposed along a semiconductor substrate.

[0151] In some embodiments, the gate and the second barrier layer are under the active layer, the first barrier layer, the first source / drain and the second source / drain are on the active layer, and the gate and the second barrier layer are spaced apart on a transistor device disposed along a semiconductor substrate.

[0152] In some embodiments, the gate is located directly between the first and second source / drain electrodes and on a substrate, the substrate including the active layer, a base dielectric layer under the active layer, and a base semiconductor layer under the base dielectric layer, wherein the first barrier layer is located within the base dielectric layer, wherein the active layer has a first doping type, wherein a first source / drain region having a second doping type different from the first doping type is directly located in the active layer under the first source / drain electrode, and wherein a second source / drain region having the second doping type is directly located in the active layer under the second source / drain electrode.

[0153] In other embodiments, this invention relates to an integrated chip including a first dielectric layer. A first barrier layer is located on the first dielectric layer. A second dielectric layer is located on the first barrier layer. An active layer is located on the second dielectric layer. A first source / drain and a second source / drain are located on the active layer. A gate is located on the active layer and between the first source / drain and the second source / drain. A gate dielectric layer is located between the gate and the active layer. A second barrier layer is spaced apart from the active layer and extends along the gate.

[0154] In some embodiments, the second barrier layer extends along the lower surface of the gate and is located directly between the gate and the gate dielectric layer, and the first barrier layer comprises a first oxide and the second barrier layer comprises a second oxide different from the first oxide.

[0155] In some embodiments, the second barrier layer extends along a first sidewall of the gate and is located directly between the gate and the first source / drain, and the second barrier layer extends along a second sidewall of the gate and is located directly between the gate and the second source / drain.

[0156] In some embodiments, the second barrier layer extends along the upper surface of the gate, and the gate is located directly between the second barrier layer and the active layer.

[0157] In some embodiments, it further includes: a third dielectric layer located on the active layer and adjacent to the gate on the opposite side of the gate, wherein the second barrier layer extends on the third dielectric layer on the opposite side of the gate.

[0158] In some embodiments, the second barrier layer extends along the sidewall of the gate, the sidewall of the gate dielectric layer, and the upper surface of the active layer.

[0159] In some embodiments, the device further includes: a third barrier layer extending along the lower surface of the gate and directly located between the gate and the gate dielectric layer, wherein the first barrier layer comprises a first oxide, the second barrier layer comprises a second oxide, and the third barrier layer comprises a third oxide different from the first oxide and the second oxide, and wherein the second barrier layer extends along the sidewall of the third barrier layer.

[0160] In some embodiments, the device further includes: a semiconductor substrate, located below and spaced apart from the first dielectric layer; a transistor device disposed along the semiconductor substrate; and a plurality of conductive interconnects extending on the semiconductor substrate and coupling the transistor device to the first source / drain, the second source / drain, or the gate.

[0161] In yet another embodiment, the present invention relates to a method for forming an integrated chip. The method includes depositing a first barrier layer on a first dielectric layer; depositing a second dielectric layer on the first barrier layer; depositing an active layer on the second dielectric layer; depositing a gate dielectric layer on the active layer; depositing a gate layer on the gate dielectric layer; forming a gate from the gate layer; forming a first source / drain and a second source / drain on the active layer and adjacent to the gate on opposite sides of the gate; and depositing a second barrier layer on the active layer, the second barrier layer extending along the gate.

[0162] In some embodiments, the second barrier layer is deposited on the gate dielectric layer, and the gate layer is deposited on the second barrier layer.

[0163] In some embodiments, the second barrier layer is deposited on the gate.

[0164] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, characterized in that... ,include: Active layer; The first source / drain and the second source / drain are located on the upper surface of the active layer; The gate is located on the first side of the active layer and between the first source / drain and the second source / drain; A gate dielectric layer is located between the gate and the active layer; A first barrier layer is located on a second side of the active layer and spaced apart from the active layer, the second side being opposite to the first side of the active layer; and A second barrier layer is located on the first side of the active layer and spaced apart from the active layer, and extends along the gate.

2. The integrated chip according to claim 1, characterized in that... The second barrier layer is located directly between the gate and the gate dielectric layer.

3. The integrated chip according to claim 2, characterized in that... The second barrier layer extends along the sidewall of the gate.

4. The integrated chip according to claim 1, characterized in that... The gate is located directly between the second barrier layer and the gate dielectric layer.

5. The integrated chip according to claim 1, characterized in that... The gate and the second barrier layer are on the active layer, the first barrier layer is below the active layer, and the active layer and the first barrier layer are spaced apart on a transistor device disposed along a semiconductor substrate.

6. The integrated chip according to claim 1, characterized in that... The gate and the second barrier layer are below the active layer, the first barrier layer, the first source / drain and the second source / drain are on the active layer, and the gate and the second barrier layer are spaced apart on a transistor device disposed along a semiconductor substrate.

7. The integrated chip according to claim 1, characterized in that... The gate is located directly between the first and second source / drain electrodes and on a substrate, the substrate comprising the active layer, a base dielectric layer beneath the active layer, and a base semiconductor layer beneath the base dielectric layer, wherein the first barrier layer is located within the base dielectric layer. The active layer has a first doping type, wherein a first source / drain region having a second doping type different from the first doping type is directly located in the active layer under the first source / drain, and wherein a second source / drain region having the second doping type is directly located in the active layer under the second source / drain.

8. An integrated chip, characterized in that... ,include: First dielectric layer; A first barrier layer is located on the first dielectric layer; The second dielectric layer is located on the first barrier layer; The active layer is located on the second dielectric layer; The first source / drain and the second source / drain are located on the active layer; A gate is located on the active layer and between the first source / drain and the second source / drain; A gate dielectric layer is located between the gate and the active layer; and A second barrier layer is spaced apart from the active layer on the active layer and extends along the gate.

9. The integrated chip according to claim 8, characterized in that... The second barrier layer extends along the lower surface of the gate and is located directly between the gate and the gate dielectric layer, and the first barrier layer comprises a first oxide and the second barrier layer comprises a second oxide different from the first oxide.

10. The integrated chip according to claim 8, characterized in that... The second barrier layer extends along the upper surface of the gate, and the gate is located directly between the second barrier layer and the active layer.

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