Semiconductor device

Abstract

This invention provides a semiconductor device in which an isolation region between a medium-voltage transistor region and a low-voltage transistor region is fabricated to have characteristics different from those of an isolation region between low-voltage transistors within the low-voltage transistor region. Dual STI technology is used to form the isolation region between low-voltage transistors within the low-voltage transistor region using low-voltage transistor isolation design rules, and additional STI formation operations can be performed to form the isolation region between the low-voltage transistor region and the medium-voltage transistor region. Specifically, dual STI technology can be used to form the isolation region between the low-voltage transistor region and the medium-voltage transistor region such that these isolation regions are deeper than other isolation regions in the semiconductor device.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] High-voltage transistors include transistors configured to operate at higher voltages (e.g., high gate voltage, high drain voltage) relative to medium-voltage transistors and low-voltage transistors, while medium-voltage transistors include transistors configured to operate at higher voltages (e.g., high gate voltage, high drain voltage) relative to low-voltage transistors. The maximum voltage a medium-voltage transistor can withstand (without damage) may be lower than the maximum voltage a high-voltage transistor can withstand (without damage), and the maximum voltage a low-voltage transistor can withstand (without damage) may be lower than the maximum voltage a medium-voltage transistor can withstand (without damage). Low-voltage transistors can be used in applications such as logic circuits (e.g., processors), memory (e.g., static random access memory (SRAM)), and / or input / output (I / O) circuits. High-voltage and medium-voltage transistors can be used in applications such as integrated circuit (IC) drivers, power ICs, shifter circuits, image sensors, power management, radio frequency (RF) power amplifiers, display driver ICs (DDICs), bipolar complementary metal-oxide-semiconductor (CMOS) diffused metal-oxide-semiconductor (DMOS) ICs (BCD ICs) and / or image signal processing (ISP) ICs. Utility Model Content

[0003] This invention provides a semiconductor device, comprising: a plurality of finned active regions extending onto a substrate of the semiconductor device; one or more fin-based transistor structures on the plurality of finned active regions; a planar active region extending onto the substrate of the semiconductor device; a laterally diffused metal-oxide-semiconductor transistor structure on the planar active region; and a dielectric isolation region between the planar active region and the plurality of finned active regions, wherein the dielectric isolation region comprises: a first portion, wherein the bottom surface of the dielectric isolation region is lower than the bottom surface of the plurality of finned active regions in the semiconductor device; and a second portion, wherein the bottom surface of the dielectric isolation region is lower than the bottom surface of the dielectric isolation region in the first portion in the semiconductor device. Attached Figure Description

[0004] The best understanding of the features of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0005] Figures 1A to 1L This is a schematic diagram illustrating an example of a partially formed semiconductor device according to some embodiments described herein.

[0006] Figure 2 This is a schematic diagram of a semiconductor device according to some embodiments described herein.

[0007] Figure 3 This is a schematic diagram of a semiconductor device according to some embodiments described herein.

[0008] Figure 4 This is a schematic diagram of a semiconductor device according to some embodiments described herein.

[0009] Figure 5A and Figure 5B This is a schematic diagram of the transistor structure of various types of transistors that may be included in a semiconductor device according to some embodiments described herein.

[0010] Figure 6 This is a flowchart of an exemplary process related to forming the semiconductor device described herein, based on some embodiments.

[0011] Figure 7 This is a flowchart of an exemplary process related to forming the semiconductor device described herein, based on some embodiments. Detailed Implementation

[0012] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of explanation, this document may use spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can be interpreted accordingly.

[0014] High-voltage and medium-voltage transistors can be integrated into semiconductor devices along with low-voltage transistors, which can be included in the logic circuitry of the semiconductor device. Low-voltage transistors can include fin-based transistors, such as fin field-effect transistors (FFETs), nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge transistors, nanoribbon transistors), and / or other types of transistors with smaller feature sizes and / or more compact spacing compared to high-voltage and / or medium-voltage transistors. While this allows high-voltage, medium-voltage, and low-voltage transistors to be manufactured using similar semiconductor fabrication processes and to share manufacturing operations, high-voltage and / or medium-voltage transistors may have different spacing rules than low-voltage transistors.

[0015] For example, a medium-voltage transistor may include a laterally diffused (or laterally double-diffused) metal-oxide-semiconductor (LDMOS) transistor with a drift region in which charge carriers diffuse laterally to facilitate the electric field distribution between the gate structure and the source / drain regions of the medium-voltage transistor. The lateral diffusion of charge carriers in the drift region allows the medium-voltage transistor to withstand higher gate and source / drain voltages than low-voltage transistors. However, due to the large-area diffusion of charge carriers in the medium-voltage transistor, it may be prone to current leakage into the substrate it forms (sometimes referred to as punch-through current leakage). Therefore, the spacing between the medium-voltage transistor and the low-voltage transistor may be larger than the spacing between the low-voltage transistors to prevent or reduce the possibility of current leakage from the medium-voltage transistor degrading the performance of the low-voltage transistor and / or damaging it.

[0016] Therefore, although high-voltage transistors, medium-voltage transistors, and low-voltage transistors can be manufactured using similar processes, the same semiconductor manufacturing operations used to manufacture low-voltage transistors may not be entirely suitable for manufacturing high-voltage and medium-voltage transistors.

[0017] In some embodiments described herein, a semiconductor device is formed such that the fabrication characteristics of the isolation region between the medium-voltage transistor region and the low-voltage transistor region differ from those of the isolation region between low-voltage transistors within the low-voltage transistor region. The dual shallow trench isolation (STI) technique described herein is used to form the isolation region between low-voltage transistors within the low-voltage transistor region using low-voltage transistor isolation design rules, and additional STI formation operations can be performed to form the isolation region between the low-voltage transistor region and the medium-voltage transistor region. Specifically, the dual STI technique described herein can be used to form the isolation region between the low-voltage transistor region and the medium-voltage transistor region such that these isolation regions are deeper than other isolation regions in the semiconductor device.

[0018] In this way, the dual shallow trench isolation technique described herein allows the isolation region between the low-voltage transistor region and the medium-voltage transistor region to be formed using different design rules, thereby providing greater electrical isolation between the low-voltage transistor region and the medium-voltage transistor region, and achieving smaller spacing between low-voltage transistors in the low-voltage transistor region (to obtain greater transistor density). This allows medium-voltage transistors in the medium-voltage transistor region to be closer to low-voltage transistors in the low-voltage transistor region, while minimizing or eliminating the possibility of current leakage from the medium-voltage transistor affecting the performance of the low-voltage transistor and / or damaging the low-voltage transistor. Therefore, the dual shallow trench isolation technique described herein enables higher device density in semiconductor devices comprising high-voltage transistors, medium-voltage transistors, and low-voltage transistors.

[0019] Figures 1A to 1L This is a schematic diagram of an example 100 forming part of the semiconductor device 102 described herein. Example 100 includes forming active regions for various transistor regions of the semiconductor device 102 and forming associated isolation regions between the active regions. Specifically, the semiconductor device 102 may be manufactured to include a plurality of transistors, and the active regions may be the active regions of transistors. The transistors may include one or more low-voltage transistors in low-voltage transistor regions and one or more medium-voltage transistors in medium-voltage transistor regions. The semiconductor device 102 may also include one or more high-voltage transistors in high-voltage transistor regions.

[0020] Go to Figure 1A and Figure 1B It can provide a substrate 104 for use in semiconductor device 102. Figure 1A A perspective view of the semiconductor device 102 is shown, while Figure 1B Show along Figure 1A A cross-sectional view of the semiconductor device 102 along line AA. Substrate 104 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (e.g., gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates. Substrate 104 may be provided in the form of a semiconductor chip or other types of semiconductor workpieces.

[0021] like Figure 1A and Figure 1B As further shown, multiple layers may be formed on and / or on the substrate 104. These layers may include a pad oxide layer 106 located on and / or on the substrate 104, a hard shielding layer 108 located on and / or on the pad oxide layer 106, and / or a fin patterned layer 110 located on and / or on the hard shielding layer 108, etc.

[0022] The pad oxide layer 106 may include one or more oxide materials, such as silicon dioxide (SiO2). x The dielectric oxide layer 106 may comprise another dielectric material, such as SiO2, SiON, SiOC, fluorine-doped glass silicate (FSG), undoped glass silicate (USG), and / or other suitable dielectric oxide materials. Additionally and / or alternatively, the pad oxide layer 106 may comprise another dielectric material. In some embodiments, the pad oxide layer 106 is formed to have a thickness ranging from approximately 30 angstroms to approximately 50 angstroms. However, other values ​​within this range are within the scope of this disclosure.

[0023] In some embodiments, the hard shielding layer 108 comprises one or more nitride materials, such as silicon nitride (Si). x N y Materials such as Si3N4, silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), and / or other suitable dielectric nitride materials. Additionally and / or alternatively, the hard shielding layer 108 may include another dielectric material. In some embodiments, the hard shielding layer 108 is formed to include a thickness in the range of approximately 360 angstroms to approximately 400 angstroms. However, other values ​​within this range are within the scope of this disclosure.

[0024] The fin patterned layer 110 may include a sacrificial layer for patterning the substrate 104 to form active regions in the substrate 104. For example, the fin patterned layer 110 may be used to form a mandrel over the substrate 104 so that the mandrel can be used to form spacers, and then the substrate 104 is etched using the spacers to form active regions. In some embodiments, the fin patterned layer 110 includes a semiconductor layer having a crystalline or polycrystalline structure. For example, the fin patterned layer 110 may include monocrystalline silicon (Si), polycrystalline silicon (Si), and / or other suitable materials. In some embodiments, the thickness of the fin patterned layer 110 includes a range of approximately 100 angstroms to approximately 500 angstroms. However, other values ​​within this range are within the scope of this disclosure.

[0025] The pad oxide layer 106 and / or hard shielding layer can be deposited using deposition tools employing chemical vapor deposition techniques (e.g., plasma-enhanced CVD (PECVD), atmospheric pressure CVD (APCVD), low-pressure CVD (LPCVD), high-density plasma CVD (HDPCVD)), atomic layer deposition (ALD), atomic layer CVD (ALCVD), physical vapor deposition (PVD) (e.g., sputtering), thermal oxidation, and / or other suitable deposition techniques. The fin pattern layer 110 can be formed using CVD, ALD, epitaxial techniques (e.g., molecular beam epitaxy (MBE), and / or other epitaxial techniques), and / or other suitable deposition techniques.

[0026] Reference Figure 1C and Figure 1D A portion of the substrate 104 of the semiconductor device 102 can be removed to form various active regions in the substrate 104. Figure 1C A perspective view of the semiconductor device 102 is shown, while Figure 1D Show along Figure 1C Cross-sectional view of semiconductor device 102 along center line AA.

[0027] like Figure 1CAs shown, active regions may be formed in low-voltage transistor region 112 and in medium-voltage transistor region 114 adjacent to low-voltage transistor region 112. In some embodiments, active regions are also formed in high-voltage transistor region 116, which may be adjacent to medium-voltage transistor region 114 or located in another region of semiconductor device 102. Active regions formed in low-voltage transistor region 112 include fin-shaped active regions 118. Fin-shaped active regions 118 may form low-voltage transistor structures to be formed in low-voltage transistor region 112. Low-voltage transistor structures may include fin-based transistor structures. Fin-shaped active regions 118 may extend in semiconductor device 102 along the x-direction and may be arranged in semiconductor device 102 in the y-direction. Fin-shaped active regions 118 may extend in semiconductor device 102 over substrate 104 along the z-direction.

[0028] like Figure 1C As further shown, the active region formed in the intermediate voltage transistor region 114 includes a planar active region 120. The planar active region 120 can form a intermediate voltage transistor structure to be formed in the intermediate voltage transistor region 114. The intermediate voltage transistor structure can include a planar transistor structure. Additionally and / or alternatively, fin-shaped active regions can be formed in the intermediate voltage transistor region 114 for one or more fin-based intermediate voltage transistor structures. The planar active region 120 can extend in the semiconductor device 102 along the x-direction and can be arranged in the semiconductor device 102 along the y-direction. The planar active region 120 can extend in the semiconductor device 102 along the z-direction onto the substrate 104.

[0029] The y-direction width of the planar active region 120 may be greater than the y-direction width of the fin active region 118. Furthermore and / or alternatively, the y-direction spacing between adjacent planar active regions 120 in the medium-voltage transistor region 114 may be greater than the y-direction spacing between adjacent fin active regions 118 in the low-voltage transistor region 112.

[0030] like Figure 1C As further shown, the active region formed in the high-voltage transistor region 116 includes a planar active region 122. The planar active region 122 can form a high-voltage transistor structure to be formed in the high-voltage transistor region 116. The high-voltage transistor structure can include a planar transistor structure. Additionally and / or alternatively, a fin-shaped active region can be formed for one or more fin-based high-voltage transistor structures in the high-voltage transistor region 116. The planar active region 122 can extend in the semiconductor device 102 along the x-direction and can be arranged in the semiconductor device 102 along the y-direction. The planar active region 122 can extend in the semiconductor device 102 along the z-direction onto the substrate 104.

[0031] In some embodiments, the y-direction width of the planar active region 122 is greater than the y-direction width of the planar active region 120. In some embodiments, the y-direction width of the planar active region 120 is greater than the y-direction width of the planar active region 122. In some embodiments, the y-direction widths of the planar active region 120 and the planar active region 122 are approximately equal. In some embodiments, the y-direction spacing between adjacent planar active regions 122 in the high-voltage transistor region 116 is greater than the y-direction spacing between adjacent planar active regions 120 in the medium-voltage transistor region 114. In some embodiments, the y-direction spacing between adjacent planar active regions 120 in the medium-voltage transistor region 114 is greater than the y-direction spacing between adjacent planar active regions 122 in the high-voltage transistor region 116. In some embodiments, the y-direction spacing between adjacent planar active regions 122 in the high-voltage transistor region 116 and the y-direction spacing between adjacent planar active regions 120 in the medium-voltage transistor region 114 are approximately equal.

[0032] The pad oxide layer 106, hard shielding layer 108, and / or fin pattern layer 110 can be used to pattern the substrate 104 to form fin-shaped active regions 118, planar active regions 120, and / or planar active regions 122 in the substrate 104. For example, the fin pattern layer 110 can be used to form a mandrel over the substrate 104 to form spacers, and then the substrate 104 can be etched using the spacers to form the fin-shaped active regions 118, planar active regions 120, and / or planar active regions 122. The pattern in the photoresist layer is used to form the mandrel in the fin pattern layer 110. The photoresist layer can be formed on the fin pattern layer 110 using a deposition tool. The photoresist layer can be exposed to a radiation source using an exposure tool to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the fin pattern layer 110 according to the pattern to form the mandrel. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). A spacer layer can be deposited above and around the mandrel using a deposition tool, and a portion of the spacer layer can be removed using an etching tool to form spacers on the hard shielding layer 108. An etching tool can be used to etch through the hard shielding layer 108, the pad oxide layer 106, and into the substrate 104 to form finned active regions 118, planar active regions 120, and / or planar active regions 122 in the substrate 104.

[0033] Other techniques may be used to form fin-shaped active regions 118, planar active regions 120, and / or planar active regions 122 in substrate 104. These techniques may include dual patterning, triple patterning, quadruple patterning, self-aligned patterning, and / or other patterning techniques.

[0034] like Figure 1C As further shown, forming finned active regions 118, planar active regions 120, and planar active regions 122 in substrate 104 results in the formation of one or more isolation grooves in substrate 104. For example, forming finned active regions 118 in low-voltage transistor region 112 and planar active regions 120 in medium-voltage transistor region 114 results in the formation of isolation groove 124 between the finned active regions 118 in low-voltage transistor region 112 and the planar active regions 120 in medium-voltage transistor region 114. As another example, forming planar active regions 120 in medium-voltage transistor region 114 results in the formation of isolation groove 126 between adjacent planar active regions 120 in medium-voltage transistor region 114. As yet another example, forming planar active regions 120 in medium-voltage transistor region 114 and planar active regions 122 in high-voltage transistor region 116 results in the formation of isolation groove 128 between the planar active regions 120 in medium-voltage transistor region 114 and the planar active regions 122 in high-voltage transistor region 116.

[0035] like Figure 1D As shown, removing a portion of substrate 104 results in the formation of an isolation recess 124, such that the isolation recess 124 has a depth corresponding to dimension D1. The depth of the isolation recess 124 is relative to the top surface of the planar active region 120 and / or relative to the top surface of the fin-shaped active region 118. Similarly, removing a portion of substrate 104 results in the formation of an isolation recess 126, such that the isolation recess 126 has a depth corresponding to dimension D1. The depth of the isolation recess 126 is relative to the top surface of the planar active region 120. Removing a portion of substrate 104 results in the formation of an isolation recess 128, such that the isolation recess 128 has a depth corresponding to dimension D1. The depth of the isolation recess 128 is relative to the top surface of the planar active region 120 and / or relative to the top surface of the planar active region 122. Therefore, the depths of isolation recesses 124, 126, and 128 may be approximately equal.

[0036] Removing a portion of substrate 104 results in the formation of a fin-shaped active region 118, such that the fin-shaped active region 118 has a fin height corresponding to dimension D2. The fin height of the fin-shaped active region 118 may be relative to the bottom surface of substrate 104 in low-voltage transistor region 112. In some embodiments, in semiconductor device 102, the top surfaces of the fin-shaped active region 118, the planar active region 120, and the planar active region 122 are approximately coplanar.

[0037] Go to Figure 1E and Figure 1F One or more fin-shaped active regions 118 in the low-voltage transistor region 112 of the semiconductor device 102 may be removed to form one or more fin-shaped cut regions 130 in the low-voltage transistor region 112. Figure 1E A perspective view of the semiconductor device 102 is shown, while Figure 1F It shows along Figure 1E Cross-sectional view of semiconductor device 102 along center line AA.

[0038] like Figure 1E As shown, the fin-cut region 130 includes a portion of the low-voltage transistor region 112, wherein one or more fin-active regions 118 have been removed. The fin-cut region 130 may be adjacent to one or more fin-active regions 118. In some embodiments, the fin-cut region 130 is located between subsets of the fin-active regions 118 in the low-voltage transistor region 112 to provide electrical isolation for adjacent low-voltage transistor structures to be formed in the low-voltage transistor region 112. In some embodiments, the fin-cut region 130 is located between the fin-active regions 118 and the isolation recess 124, and between the fin-active regions 118 and the planar active region 120 of the medium-voltage transistor region 114. The fin-cut region 130 may extend in the semiconductor device 102 along the x-direction. Therefore, the direction in which the fin-cut region 130 extends is the same (and approximately parallel) to the direction in which the isolation recesses 124, 126, and / or 128 extend, and also the same as the direction in which the fin-active regions 118 extend.

[0039] The fin-shaped cut region 130 can be formed by etching one or more fin-shaped active regions 118 using a pattern in the photoresist layer. A photoresist layer can be formed on the fin-shaped active regions 118 in the low-voltage transistor region 112 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern, wherein at least a subset of the fin-shaped active regions 118 is exposed through the pattern. An etching tool can be used to etch at least a subset of the fin-shaped active regions 118 based on the pattern to remove at least a subset of the fin-shaped active regions 118 to form the fin-shaped cut region 130. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0040] like Figure 1F As shown, the distance (dimension D3) between the top of the cut fin in the fin-shaped cutting region 130 and the top of the fin-shaped active region 118 can be less than the fin height (dimension D2) of the fin-shaped active region 118. Therefore, the cut fin can include the remaining portion of the fin-shaped active region 118, most of which is removed to form the cut fin.

[0041] Go to Figure 1G In the low-voltage transistor region 112 of the semiconductor device 102, at least a portion of the fin-shaped active region 118 is cut in the y direction to form one or more fin-shaped cut regions 132 in the low-voltage transistor region 112. Figure 1G A perspective view of the semiconductor device 102 is shown.

[0042] like Figure 1G As shown, the fin-shaped cut region 132 can extend in the y-direction across multiple fin-shaped active regions 118. The fin-shaped cut region 132 can be formed as a portion of the multiple fin-shaped active regions 118 arranged in the x-direction within the semiconductor device 102. This allows portions of the low-voltage transistor structure to be electrically isolated in the x-direction of the low-voltage transistor region 112. The fin-shaped cut region 132 can be formed using a patterning technique similar to that used to form the fin-shaped cut region 130 described above.

[0043] Figures 1H to 1J A method for increasing the depth of isolation grooves 124, 126 and 128 is shown. Figures 1H to 1J The method shown is the dual STI method (along with) Figure 1C and Figure 1DAs part of the operation, the depths of the isolation recesses 124, 126, and 128 are increased to provide greater electrical isolation between the medium-voltage transistor region 114 and other regions in the semiconductor device 102 (e.g., the low-voltage transistor region 112 adjacent to the medium-voltage transistor region 114, and the high-voltage transistor region 116 adjacent to the medium-voltage transistor region 114).

[0044] like Figure 1H As shown in the cross-sectional view, a shielding layer 134 is formed on the semiconductor device 102, and the shielding layer 134 is patterned to expose isolation recesses 124, 126, and 128. After patterning, the shielding layer 134 may remain on the finned active region 118 in the low-voltage transistor region 112 and the planar active region 122 in the high-voltage transistor region 116. The shielding layer 134 may include a photoresist layer. To pattern the shielding layer 134, a deposition tool can be used to form the shielding layer 134 on the semiconductor device 102. An exposure tool can be used to expose the shielding layer 134 to a radiation source to pattern the shielding layer 134. A development tool can be used to develop and remove portions of the shielding layer 134 to expose the pattern through which the isolation recesses 124, 126, and 128 and the planar active region 120 are exposed. In some embodiments, a portion of the shielding layer 134 covers portions of the isolation recesses 124 and 128 to prevent the planar active region 122 and the finned active region 118 from being etched when the substrate 104 is etched to increase the depth of the isolation recesses 124, 126 and 128.

[0045] At least a subset of the fin-shaped active regions 118 can be etched according to a pattern using an etching tool to remove at least a subset of the fin-shaped active regions 118, forming the fin-shaped cut regions 130. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0046] like Figure 1I As shown in the cross-sectional view, additional material of the substrate 104 is removed from the bottom surface of the isolation recesses 124, 126, and 128 according to the pattern in the shielding layer 134. This removal of additional material from the substrate 104 increases the depth of the isolation recesses 124, 126, and 128. Figure 1J The diagram shows a perspective view of the semiconductor device 102 after the depths of the isolation recesses 124, 126, and 128 have been increased.

[0047] like Figure 1IAs shown, the depths of isolation grooves 124, 126, and 128 can be increased from dimension D1 to dimension D4. The substrate 104 can be etched into the isolation grooves 124, 126, and 128 to increase their depths. During the etching of the substrate 104, the etching consumes a portion of the hard shielding layer 108 on the planar active region 120 because the planar active region 120 is exposed through the pattern in the shielding layer 134. The hard shielding layer 108 on the planar active region 120 protects the planar active region 120 from etching. Therefore, the thickness of the hard shielding layer 108 on the planar active region 120 is less than the thickness of the hard shielding layers 108 on the planar active region 122 and the finned active region 118, because the planar active region 122 and the finned active region 118 are covered and protected by the shielding layer 134 during the etching of the substrate 104.

[0048] The substrate 104 in the isolation recesses 124, 126, and 128 can be etched using dry etching, wet etching, plasma-based etching, and / or other suitable etching techniques. In some embodiments, oxygen-containing gas is used to control the respective etching rates of the materials of the hard shield 108 and the substrate 104 during etching to increase the depth of the isolation recesses 124, 126, and 128. Specifically, the oxygen-containing gas can be used to control the amount of hard shield 108 consumed during etching and the amount of substrate 104 removed during etching. The flow rate of the oxygen-containing gas, which is supplied to the processing chamber where the semiconductor device 102 is positioned for etching, can be controlled within a range greater than 0 standard cubic centimeters per minute (sccm) and less than or approximately equal to 15 sccm. If the flow rate of the oxygen-containing gas is too low (e.g., 0 sccm), the etching rate of the material of the hard shield 108 may be too high, and too much material may be removed from the hard shield 108 during etching. If this occurs, in the subsequent planarization operation, the amount of hard shielding layer 108 remaining on the planar active region 120 may be insufficient to adequately protect the planar active region 120. This planarization operation is discussed below regarding... Figure 1LAs described in the description. If the oxygen-containing gas flow rate is too high (e.g., greater than about 15 sccm), the etching rate of the material of substrate 104 may be too low to adequately increase the depth of isolation trenches 124, 126, and 128. Therefore, sufficient electrical isolation may not be provided for the medium-voltage transistors in medium-voltage transistor region 114, leading to current leakage from the medium-voltage transistors degrading the performance of other transistors in semiconductor device 102 (e.g., low-voltage transistors in low-voltage transistor region 112) and / or increasing the likelihood of damage to them. If the oxygen-containing gas flow rate is controlled within a range greater than 0 sccm and less than or approximately equal to 15 sccm, sufficient etching of substrate 104 can be achieved while ensuring that the hard shielding layer 108 is retained in sufficient quantity for subsequent processing operations. However, other values ​​of the oxygen-containing gas flow rate, i.e., ranges other than greater than 0 sccm and less than or approximately equal to 15 sccm, are within the scope of this disclosure.

[0049] In some embodiments, after etching substrate 104 to increase the depth of isolation recesses 124, 126, and / or 128, post-etch cleaning of isolation recesses 124, 126, and / or 128 is performed. Post-etch cleaning may be performed to remove etching byproducts, remove residual oxides, and / or remove residual etchant from isolation recesses 124, 126, and / or 128, etc.

[0050] like Figure 1I As further shown, since the shielding layer 134 covers a portion of the isolation groove 124 during etching to increase the depth of the isolation groove 124, the isolation groove 124 can have portions of varying depths. For example, a portion 136 of the isolation groove 124 not covered by the shielding layer 134 (e.g., the portion of the isolation groove 124 adjacent to the planar active region 120) has a depth corresponding to dimension D4, and another portion 136 of the isolation groove 124 covered by the shielding layer 134 (e.g., the portion of the isolation groove 124 adjacent to the low-voltage transistor region 112) remains at a depth corresponding to dimension D1. Therefore, the bottom surface of the isolation groove 124 can have a stepped cross-sectional profile. Dimension D1 can include a range of approximately 1,300 angstroms to approximately 1,700 angstroms, while dimension D4 can be greater than 1,700 angstroms and less than or approximately equal to 10,000 angstroms. However, other values ​​outside these ranges are within the scope of this disclosure.

[0051] Similarly, the isolation recess 128 may have portions of different depths because the shielding layer 134 covers a portion of the isolation recess 128 during etching to increase its depth. For example, a portion 140 of the isolation recess 128 not covered by the shielding layer 134 (e.g., the portion of the isolation recess 128 adjacent to the planar active region 120) has a depth corresponding to dimension D4, while another portion 142 of the isolation recess 128 covered by the shielding layer 134 (e.g., the portion of the isolation recess 128 adjacent to the high-voltage transistor region 116) remains at a depth corresponding to dimension D1. Therefore, the bottom surface of the isolation recess 128 may have a stepped cross-sectional profile.

[0052] like Figure 1K As shown in the cross-sectional view, an isolation layer 144 is formed on the substrate 104. The isolation layer 144 can be deposited using deposition tools employing CVD, PVD, ALD, oxidation, and / or other deposition techniques. The isolation layer 144 fills isolation recesses 124, 126, and 128. The isolation layer 144 also fills the space between the fin-shaped active regions 118, fills the fin-shaped cut regions 130 and 132 on the cut fins. The isolation layer 144 may include one or more dielectric materials, such as silicon dioxide (SiO2). x Such as SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), fluorine-doped silicate glass (FSG), undoped silicate glass (USG), silicon nitride (SiO2), silicon oxy ... x N y Such as Si3N4), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN) and / or other suitable dielectric nitride materials.

[0053] like Figure 1K As shown, the isolation layer 144 can be formed with a height greater than the height of the planar active region 120 in the medium-voltage transistor region 114 and greater than the height of the planar active region 122 in the high-voltage transistor region 116. In other words, the isolation layer 144 is formed such that the isolation layer 144 covers the planar active regions 120 and 122. In some embodiments, the isolation layer 144 is formed such that the isolation layer 144 also covers the finned active region 118, and a portion of the isolation layer 144 is etched using an etching tool to reduce the height of the isolation layer 144 in the low-voltage transistor region 112. Specifically, the isolation layer 144 can be etched such that the top surface of the isolation layer 144 in the low-voltage transistor region 112 is lower than the top of the finned active region 118. The isolation layer 144 can be etched using plasma etching, wet chemical etching, and / or another etching technique. The remaining portion of the isolation layer 144 between the finned active regions 118 may include STI regions between the finned active regions 118.

[0054] Alternatively, the isolation layer 144 may be deposited such that the top surface of the isolation layer 144 in the low-voltage transistor region 112 is lower than the top of the finned active region 118. This may cause the top surface of the isolation layer 144 to slope downward from the medium-voltage transistor region 114 towards the low-voltage transistor region 112.

[0055] like Figure 1L As shown in the cross-sectional view, the isolation layer 144 can be planarized to remove excess material from the isolation layer 144. The planarization operation to planarize the isolation layer 144 can be performed using a planarization tool employing chemical mechanical planarization (CMP) technology and / or another suitable planarization technique. Removing excess material from the isolation layer 144 results in the formation of a diced fin isolation region 146 (e.g., a dielectric isolation region) in the fin diced region 130 adjacent to the fin active region. The diced fin isolation region 146 may have a thickness (size D5) on the bottom surface of the substrate 104 in the low-voltage transistor region 112, and another thickness (size D6) on the diced fin in the low-voltage transistor region 112. In some embodiments, sizes D5 and D6 are different, resulting in the top surface of the diced fin isolation region 146 having different z-direction heights above the diced fin and above the substrate 104. In some embodiments, sizes D5 and D6 are approximately the same value in the diced fin isolation region 146, resulting in the top surface of the diced fin isolation region 146 having a substantially uniform z-direction height.

[0056] like Figure 1L As further shown, removing excess material from the isolation layer 144 results in the formation of an isolation region 148 (e.g., a dielectric isolation region) between the medium-voltage transistor region 114 and the low-voltage transistor region 112. Specifically, the isolation region 148 includes a planar active region 120 in the medium-voltage transistor region 114 and a finned active region 118 in the low-voltage transistor region 112. The isolation region 148 may be located between a cut-fin isolation region 146 and a planar active region 120 in the medium-voltage transistor region 114, and the cut-fin isolation region 146 may be located between the isolation region 148 and the finned active region 118 in the low-voltage transistor region 112.

[0057] Isolation region 148 may be included to provide electrical isolation between a medium-voltage transistor included in medium-voltage transistor region 114 and a low-voltage transistor included in low-voltage transistor region 112. The bottom surface of isolation region 148 may have a stepped profile, such that isolation region 148 includes portion 154 and another portion 156, wherein segments of the bottom surface of isolation region 148 are at different z-direction heights within semiconductor device 102. These different z-direction heights are generated by dual STI technology, such as... Figure 1C , Figure 1D , Figure 1H , Figure 1I and Figure 1J As described herein, this technique is used to form an isolation recess 124. A portion 154 is adjacent to a planar active region 120 in a medium-voltage transistor region 114, and a portion 156 is located between portion 154 and a plurality of finned active regions 118. Portion 156 may also be adjacent to a cut-fin isolation region 146 in a low-voltage transistor region 112.

[0058] In semiconductor device 102, a segment of the bottom surface of isolation region 148 in portion 154 is lower than the bottom of finned active region 118, and in semiconductor device 102, a segment is lower than the bottom surface of isolation region 148 in portion 156. In semiconductor device 102, a segment of the bottom surface of isolation region 148 in portion 154 is also lower than the top surface of one or more diced fins in diced finned regions 130 in low-voltage transistor region 112.

[0059] In semiconductor device 102, a segment of the bottom surface of isolation region 148 in portion 156 is lower than the bottom of finned active region 118, but higher than a segment of the bottom surface of isolation region 148 in portion 154. In semiconductor device 102, a segment of the bottom surface of isolation region 148 in portion 156 is also lower than the top surface of one or more diced fins in diced finned region 130 of low-voltage transistor region 112.

[0060] A portion 156 of isolation region 148 has a thickness (dimension D7), and a portion 154 of isolation region 148 has a thickness (dimension D8) greater than the thickness of portion 156 of isolation region 148. In some embodiments, the thickness (dimension D8) of portion 154 is greater than about 1,700 angstroms and less than or about 10,000 angstroms, which can achieve sufficient electrical isolation between the medium-voltage transistor in medium-voltage transistor region 114 and the low-voltage transistor in low-voltage transistor region 112. However, other values ​​in this range are within the scope of this disclosure.

[0061] The greater thickness of portion 154 of isolation region 148 may be due to the fact that, in semiconductor device 102, a segment of the bottom surface of isolation region 148 in portion 154 of isolation region 148 is lower than a segment of the bottom surface of isolation region 148 in portion 156 of isolation region 148, and / or may be due to the fact that, in semiconductor device 102, the top surface of isolation region 148 in portion 154 of isolation region 148 is located at a higher z-direction position than the top surface of isolation region 148 in portion 156 of isolation region 148. This difference in z-direction position (dimension D9) of the top surface of isolation region 148 causes the top surface to slope downwards from portion 154 to portion 156. This downward slope of the top surface of isolation region 148 may be due to the top surface of isolation layer 144 sloping downwards from medium-voltage transistor region 114 to low-voltage transistor region 112. Therefore, the thickness of isolation region 148 may decrease from planar active region 120 to finned active region 118.

[0062] like Figure 1L As further shown, removing excess material from the isolation layer 144 results in the formation of an isolation region 150 (e.g., a dielectric isolation region) between adjacent planar active regions 120 in the medium-voltage transistor region 114. The isolation region 150 is formed in the isolation recess 126 and may have a generally uniform bottom surface. The isolation region 150 may have a thickness corresponding to dimension D8. The isolation region 150 may be included to provide electrical isolation between adjacent medium-voltage transistors included in the medium-voltage transistor region 114.

[0063] like Figure 1L As further shown, removing excess material from the isolation layer 144 results in the formation of an isolation region 152 (e.g., a dielectric isolation region) between the medium-voltage transistor region 114 and the high-voltage transistor region 116. Specifically, the isolation region 152 is included between a planar active region 120 in the medium-voltage transistor region 114 and a planar active region 122 in the high-voltage transistor region 116. The isolation region 152 may be included to provide electrical isolation between the medium-voltage transistor included in the medium-voltage transistor region 114 and the high-voltage transistor included in the high-voltage transistor region 116.

[0064] The bottom surface of isolation region 152 may have a stepped cross-section, such that isolation region 152 includes a portion 158 and another portion 160, wherein segments of the bottom surface of isolation region 152 are located at different z-direction heights in semiconductor device 102. These different z-direction heights are a result of dual STI technology, such as... Figure 1C , Figure 1D , Figure 1H , Figure 1I and Figure 1JAs described above, this technique is used to form the isolation recess 128 formed by the isolation region 152. A portion 158 is adjacent to the planar active region 120 in the medium-voltage transistor region 114, and a portion 160 is located between portion 158 and the planar active region 122 of the high-voltage transistor region 116.

[0065] The segment of the bottom surface of isolation region 152 in portion 158 is lower than the bottom of finned active region 118 in semiconductor device 102, and lower than the segment of the bottom surface of isolation region 152 in portion 160 in semiconductor device 102. The segment of the bottom surface of isolation region 152 in portion 158 is also lower than the top surface of one or more diced fins in diced finned region 130 in low-voltage transistor region 112 in semiconductor device 102. The segment of the bottom surface of isolation region 152 in portion 158 may be at approximately the same height as portion 154 of isolation region 148 in semiconductor device 102.

[0066] A segment of the bottom surface of isolation region 152 in portion 160 is lower than the bottom of finned active region 118 in semiconductor device 102, but higher than the segment of the bottom surface of isolation region 152 in portion 158 in semiconductor device 102. The segment of the bottom surface of isolation region 152 in portion 160 is also lower than the top surface of one or more diced fins in diced finned region 130 in low-voltage transistor region 112 in semiconductor device 102. The segment of the bottom surface of isolation region 152 in portion 160 may be at approximately the same height as portion 156 of isolation region 148 in semiconductor device 102.

[0067] A portion 160 of isolation region 152 has a thickness (dimension D7), and a portion 158 of isolation region 152 has a thickness (dimension D8) greater than the thickness of portion 160 of isolation region 152. In some embodiments, the thickness (dimension D8) of portion 158 is greater than about 1,700 angstroms and less than or about 10,000 angstroms, which can achieve sufficient electrical isolation between the medium-voltage transistor in medium-voltage transistor region 114 and the high-voltage transistor in high-voltage transistor region 116. However, other values ​​in this range are within the scope of this disclosure.

[0068] like Figure 1L As further shown, the pad oxide layer 106 and the hard shield layer 108 are also removed during the planarization operation. During the planarization operation, the pad oxide layer 106 and the hard shield layer 108 protect the top of the fin-shaped active region 118, the top of the planar active region 120, and the top of the planar active region 120. Furthermore, the pad oxide layer 106 and the hard shield layer 108 can provide an etch stop indication to stop the planarization operation. In other words, the complete removal of the pad oxide layer 106 and the hard shield layer 108 provides an indication to stop the planarization operation.

[0069] As mentioned above, Figures 1A to 1L This is provided as an example. Other examples may be similar. Figures 1A to 1L The differences mentioned.

[0070] Figure 2 This is a schematic diagram of an example 200 of the semiconductor device 102 described herein. Figure 2 A cross-sectional view of an example 200 of a semiconductor device 102 along line AA is shown. Example 200 includes an example of a semiconductor device 102 after the formation of isolation regions 148 and 150, and after the formation of... Figures 1A to 1L After the cut fin isolation area 146. For example... Figure 2 As shown, the planar active region 120 in the medium-voltage transistor region 114 may have sidewalls that slope outwards from the top to the bottom of the planar active region 120. This results in isolation regions 148 and 150 having inwardly tapered sidewalls from the top to the bottom of isolation regions 148 and 150. Furthermore, the top surface of isolation region 148 may slope downwards from the planar active region 120 to the adjacent cut-fin isolation region 146. Finned active regions 118 may extend above the top surface of the STI region 202 between adjacent finned active regions 118.

[0071] As mentioned above, Figure 2 This is provided as an example. Other examples may be similar. Figure 2 The differences mentioned.

[0072] Figure 3 This is a schematic diagram of an example 300 of the semiconductor device 102 described herein. Figure 3 A top view (e.g., layout diagram) of an example 300 of the semiconductor device 102 is shown. Therefore, Figure 3 Example 300 in the document includes a layout example of one or more regions of the semiconductor device 102, and illustrates an example location of the line AA cross section in the layout of the semiconductor device 102. However, other layout examples of the semiconductor device 102 are within the scope of this disclosure.

[0073] like Figure 3As shown, in the layout of semiconductor device 102, low-voltage transistor region 112 may be adjacent to medium-voltage transistor region 114. Various isolation regions may be included between and / or around these regions to provide electrical isolation in semiconductor device 102. For example, an isolation region 148 may be included between medium-voltage transistor region 114 and low-voltage transistor region 112. As another example, an isolation region 150 may be included between adjacent medium-voltage transistor regions 114 and / or between planar active regions 120 within medium-voltage transistor regions 114.

[0074] Isolation zones 148 and 150 can be used with Figures 1A to 1L The described technique is configured to provide sufficient electrical isolation between the LDMOS transistor in the medium-voltage transistor region 114 and the fin-based transistor in the low-voltage transistor region 112.

[0075] As mentioned above, Figure 3 This is provided as an example. Other examples may be similar. Figure 3 The differences mentioned.

[0076] Figure 4 This is a schematic diagram of an example 400 of the semiconductor device 102 described herein. Figure 4 A cross-sectional view of an example 400 of a semiconductor device 102 is shown, and it may include... Figure 3 An example cross-sectional view of a portion of the example layout shown.

[0077] like Figure 4 As shown, in Example 400, semiconductor device 102 may include a low-voltage transistor region 112, a medium-voltage transistor region 114, and a high-voltage transistor region 116. High-voltage transistor region 116 may include device region 402 and a dummy region 404. A planar active region 122 may be included in device region 402 of the high-voltage transistor within high-voltage transistor region 116.

[0078] Low-voltage transistor region 112 may be adjacent to high-voltage transistor region 116. Low-voltage transistor region 112 and high-voltage transistor region 116 may be separated and electrically isolated by low-voltage isolation ring 406. Low-voltage transistor region 112 may include a finned active region 118 in device region 408 for a fin-based low-voltage transistor. Low-voltage transistor region 112 may also include dummy fins to satisfy various fin spacing design rules in the layout of semiconductor device 102.

[0079] Low-voltage transistor region 112 may be adjacent to medium-voltage transistor region 114. Low-voltage transistor region 112 and medium-voltage transistor region 114 may be separated and electrically isolated by low-voltage isolation ring 406 and medium-voltage isolation ring 410. Medium-voltage transistor region 114 may include device region 412, wherein a planar active region 120 is provided for the medium-voltage transistors of medium-voltage transistor region 114. A virtual region 414 may be provided within medium-voltage isolation ring 410.

[0080] like Figure 4 As further shown, substrate 104 may include multiple doped regions, such as one or more deep n-well regions 416, one or more p-well regions 418, and one or more n-well regions 420. One or more of regions 416, 418, and 420 may be included in low-voltage transistor region 112, medium-voltage transistor region 114, and / or high-voltage transistor region 116. Virtual fins 422 may be included in virtual regions 404 and / or 414 to satisfy various fin pitch design rules in the layout of semiconductor device 102.

[0081] like Figure 4 As further shown, various isolation regions may be included above substrate 104. For example, one or more diced fin isolation regions 146 may be included in device regions 402 and / or 408. As another example, one or more diced fin isolation regions 146 may be included in dummy regions 404 and / or 414. As another example, one or more diced fin isolation regions 146 may be included in low-voltage isolation ring 406 and / or medium-voltage isolation ring 410. As another example, one or more isolation regions 148 may be included between planar active regions 120 in device region 412 of medium-voltage transistor region 114 and finned active regions 118 in low-voltage transistor region 112. As another example, isolation region 150 may be included between adjacent planar active regions 120 in device region 412 of medium-voltage transistor region 114.

[0082] As mentioned above, Figure 4 This is provided as an example. Other examples may be similar. Figure 4 The differences mentioned.

[0083] Figure 5A and Figure 5B This is a schematic diagram of an example transistor structure 500, representing various types of transistors that may be included in the semiconductor device 102 described herein. For example... Figure 5AAs shown, an exemplary low-voltage transistor structure 502 may be included in device region 408 of low-voltage transistor region 112 of a semiconductor device. The low-voltage transistor structure 502 may be a fin-based transistor structure, which includes one or more fin-shaped active regions 118 electrically isolated via STI regions and / or cut-out fin isolation regions 146.

[0084] like Figure 5A As further shown, the voltage transistor structure 504 in the example may be included in device region 412 of the medium voltage transistor region 114 of the semiconductor device 102. The medium voltage transistor structure 504 may be a planar transistor structure, which includes a planar active region 120 electrically isolated by an isolation region 150. In addition and / or alternatively, an isolation region 148 may be provided between the medium voltage transistor structure 504 and the low voltage transistor structure 502 in the semiconductor device 102.

[0085] like Figure 5A As further shown, the exemplary high-voltage transistor structure 506 may be included in device region 402 of the high-voltage transistor region 116 of the semiconductor device 102. The high-voltage transistor structure 506 may be a planar transistor structure, which includes a planar active region 122 electrically isolated by an isolation region 152.

[0086] like Figure 5A As further shown, the low-voltage transistor structure 502 may include a gate structure 508 surrounding at least three sides of the finned active region 118. The medium-voltage transistor structure 504 includes a planar gate structure 510 extending over the top of the planar active region 120 and the top of the isolation region 150. The high-voltage transistor structure 506 may similarly include a planar gate structure 512 extending over the top of the planar active region 122 and the top of the isolation region 152.

[0087] Figure 5B An example of a medium-voltage transistor structure 504 is shown. The medium-voltage transistor structure 504 may include an LDMOS transistor and / or other types of medium-voltage transistor structures. For example... Figure 5BAs shown, a medium-voltage transistor structure 504 may include a source / drain region 514 in substrate 104 and a source / drain region 516 in substrate 104 of semiconductor device 102. In some embodiments, source / drain region 514 is a source region of medium-voltage transistor structure 504, and source / drain region 516 is a drain region of medium-voltage transistor structure 504 configured to operate at medium voltage. Source / drain region 514 may be included in and / or on a doped body region 518 in substrate 104 with body contact 520. Source / drain region 516 may be included in and / or on a drift region 522 in substrate 104. Drift region 522 may include a region of substrate 104 having a low doping concentration (e.g., relative to doped body region 518 and other doped regions) to enable drift region 522 to accommodate medium voltage of medium-voltage transistor structure 504.

[0088] A gate structure 524 may be included over a substrate 104 between source / drain regions 514 and 516, and a gate dielectric layer 526 may be included between the gate structure 524 and the substrate 104. Sidewall spacers 528 may be included on the sidewalls of the gate structure 524. A voltage may be selectively applied to the gate structure 524 to selectively control the conductivity in the drift region 522 between the source / drain regions 514 and 516.

[0089] A field plate layer 530 may be included to improve the performance of the intermediate voltage transistor structure 504 by manipulating the electric field in the drift region 522. The field plate layer 530 may be shorted to the gate structure 524, shorted to the source / drain region 516, and / or electrically connected to another structure within the intermediate voltage transistor structure 504. A bias voltage may be applied to the field plate layer 530 through the field plate contacts to reduce the peak electric field strength generated by the gate structure 524 in the drift region 522. This is known as the reduced surface field (RESURF) technique. The bias voltage increases the depletion of carriers in the drift region 522, thereby reducing the peak electric field strength in the drift region 522. By manipulating the electric field generated by the gate structure 524, the intermediate voltage transistor structure 504 can achieve an increased breakdown voltage. In some embodiments, a dielectric layer may be included between the substrate 104 and the field plate layer 530. This dielectric layer can be referred to as a localized oxide (LOCOS) layer of silicon and / or another type of dielectric layer.

[0090] like Figure 5BAs further shown, dielectric layer 532 may be included above medium-voltage transistor structure 504. Source / drain contact 534 may be included in dielectric layer 532 and may be electrically and / or physically connected to source / drain region 514. Source / drain contact 536 may be included in dielectric layer 532 and may be electrically and / or physically connected to source / drain region 516. Gate contact 538 may be included in dielectric layer 532 and may be electrically and / or physically connected to gate structure 524.

[0091] As mentioned above, Figure 5A and Figure 5B This is provided as an example. Other examples may be similar. Figure 5A and Figure 5B The descriptions are different.

[0092] Figure 6 This is a flowchart of an exemplary process 600 related to the formation of the semiconductor device described herein. In some embodiments, Figure 6 One or more process blocks are executed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, and / or chip / die transfer tools.

[0093] like Figure 6 As shown, process 600 may include removing a first portion of the substrate of the semiconductor device to form a plurality of fin-shaped active regions (block 610). For example, one or more semiconductor processing tools may be used to remove a first portion of the substrate 104 of the semiconductor device 102 to form a plurality of fin-shaped active regions 118, as described herein.

[0094] like Figure 6 As further shown, process 600 may include removing a second portion of the substrate to form a planar active region (block 620) adjacent to the plurality of finned active regions 118. For example, one or more semiconductor processing tools may be used to remove the second portion of substrate 104 to form a planar active region 120 adjacent to the plurality of finned active regions 118, as described herein. In some embodiments, removing the second portion of substrate 104 results in the formation of an isolation recess 124 between the planar active region 120 and the plurality of finned active regions 118. In some embodiments, after removing the second portion of substrate 104, the isolation recess 124 has a first depth (dimension D1) relative to the top of the planar active region 120.

[0095] like Figure 6As further shown, process 600 may include removing a third portion of the substrate from the isolation trench (block 630). For example, one or more semiconductor processing tools may be used to remove the third portion of the substrate 104 in the isolation trench 124, as described herein. After removing the third portion of the substrate 104, the isolation trench 124 has a second depth (dimension D4) relative to the top of the planar active region 120, and the second depth is greater than the first depth.

[0096] like Figure 6 As further shown, process 600 may include forming a dielectric isolation region (block 640) in the isolation recess after removing the third portion. For example, as described herein, one or more semiconductor processing tools may be used to form a dielectric isolation region (e.g., isolation region 148) in the isolation recess 124 after removing the third portion.

[0097] Process 600 may include additional implementations, such as any single or combined implementations described herein, and / or any single or combined implementations in connection with one or more other processes described elsewhere herein.

[0098] In the first embodiment, removing the third portion of the substrate 104 from the isolation groove 124 includes removing the third portion of the substrate 104 from the isolation groove 124 while the plurality of fin-shaped active regions 118 are covered by the shielding layer 134.

[0099] In the second embodiment, either alone or in combination with the first embodiment, the shielding layer 134 covers a first portion (e.g., portion 138) of the bottom surface of the isolation groove 124, and removing a third portion of the substrate 104 from the isolation groove 124 includes removing the third portion of the substrate 104 from a second portion (e.g., portion 136) of the bottom surface of the isolation groove 124 adjacent to the first portion while the shielding layer 134 covers the first portion of the bottom surface of the isolation groove 124.

[0100] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, after the third portion of the substrate 104 is removed, a first portion (e.g., portion 138) of the bottom surface of the isolation groove 124 is at a first depth (dimension D1) relative to the top of the planar active region 120, and after the third portion of the substrate 104 is removed, a second portion (e.g., portion 136) of the bottom surface of the isolation groove 124 is at a second depth (dimension D4) relative to the top of the planar active region 120.

[0101] In the fourth embodiment, removing a third portion of the substrate 104 from the isolation recess 124, either alone or in combination with one or more of the first to third embodiments, includes removing the third portion of the substrate 104 from the isolation recess 124 after forming a fin-cut region 130 adjacent to a plurality of fin-shaped active regions 118, wherein the fin-cut region 130 extends to the side of the isolation recess 124.

[0102] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, process 600 includes performing an etch-after cleaning of the isolation recess 124 after removing a third portion of the substrate 104 from the isolation recess 124.

[0103] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, removing a third portion of the substrate 104 from the isolation groove 124 includes removing the third portion of the substrate 104 from the isolation groove 124 after forming a fin-cut region 132 spanning a plurality of fin-shaped active regions 118, wherein the direction in which the fin-cut region 132 extends (e.g., the y-direction) is approximately perpendicular to the isolation groove 124.

[0104] Although Figure 6 An example block of process 600 is shown, but in some implementations, process 600 includes more... Figure 6 The block may be more, less, different, or arranged differently as described in the document. Alternatively, two or more blocks in process 600 may be executed in parallel.

[0105] Figure 7 This is a flowchart of an exemplary process 700 related to the formation of the semiconductor device described herein. In some embodiments, Figure 7 One or more process blocks are executed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, and / or chip / die transfer tools.

[0106] like Figure 7 As shown, process 700 may include removing a first portion of the substrate of the semiconductor device to form a plurality of fin-shaped active regions (block 710). For example, one or more semiconductor processing tools may be used to remove a first portion of the substrate 104 of the semiconductor device 102 to form a plurality of fin-shaped active regions 118, as described herein.

[0107] like Figure 7As further shown, process 700 may include removing a second portion of the substrate to form a planar active region adjacent to the plurality of finned active regions (block 720). For example, one or more semiconductor processing tools may be used to remove the second portion of the substrate 104 to form a planar active region 120 adjacent to the plurality of finned active regions 118, as described herein. In some embodiments, removing the second portion of the substrate 104 results in the formation of a first isolation groove 124 between a first side of the planar active region 120 and the plurality of finned active regions 118, and a second isolation groove 126 adjacent to a second side of the planar active region 120 opposite to the first side. In some embodiments, after removing the second portion of the substrate 104, the bottom surface of the first isolation groove 124 is at a first depth (dimension D1) relative to the top of the planar active region 120. In some embodiments, after removing the second portion of the substrate 104, the bottom surface of the second isolation groove 126 is at a first depth (dimension D1) relative to the top of the planar active region 120. In some embodiments, the first depth is greater than the fin height (dimension D2) of the plurality of finned active regions 118.

[0108] like Figure 7 Further, process 700 may include removing a third portion of the substrate from the first isolation recess and the second isolation recess (block 730). For example, one or more semiconductor processing tools may be used to remove the third portion of the substrate 104 from the first isolation recess 124 and the second isolation recess 126, as described herein. In some embodiments, after removing the third portion of the substrate 104, at least a portion of the bottom surface of the first isolation recess 124 is at a second depth (dimension D4) relative to the top of the planar active region 120. In some embodiments, after removing the third portion of the substrate 104, the bottom surface of the second isolation recess 126 is at a second depth (dimension D4) relative to the top of the planar active region 120. In some embodiments, the second depth is greater than the first depth.

[0109] like Figure 7 As further shown, process 700 may include forming a first dielectric isolation region in a first isolation recess and a second dielectric region in a second isolation recess (block 740) after removing the third portion. For example, after removing the third portion, one or more semiconductor processing tools may be used to form the first dielectric isolation region (e.g., isolation region 148) in the first isolation recess 124 and the second dielectric region (e.g., isolation region 150) in the second isolation recess 126, as described herein.

[0110] Process 700 may include additional implementations, such as any single or combined implementations relating to one or more other processes described elsewhere herein and in connection with the following and / or the process described elsewhere herein.

[0111] In the first embodiment, after the third portion of the substrate 104 is removed, another portion of the bottom surface of the first isolation groove 124 in the stepped portion (e.g., portion 138) of the first isolation groove 124 is at a first depth (dimension D1).

[0112] In the second embodiment, either alone or in combination with the first embodiment, when a third portion of the substrate 104 is removed from the first isolation recess 124 and the second isolation recess 126, the stepped portion (e.g., portion 138) of the first isolation recess 124 is covered by the shielding layer 134.

[0113] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, after the third portion of the substrate 104 is removed, the first thickness of the hard shielding layer 108 on top of the planar active region 120 is less than the second thickness of the hard shielding layer 108 on top of the plurality of fin-shaped active regions 118.

[0114] In the fourth embodiment, removing a third portion of the substrate 104 from the first isolation recess 124 and the second isolation recess 126, either alone or in combination with one or more of the first to third embodiments, includes performing an etching operation to etch the substrate 104 to remove the third portion of the substrate 104 from the first isolation recess 124 and the second isolation recess 126, wherein an oxygen-containing gas is used to control the etch selectivity between the substrate 104 and the hard shielding layer 108.

[0115] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the flow rate of the oxygen-containing gas during the etching operation is greater than 0 sccm and less than or approximately equal to 15 sccm.

[0116] In the sixth embodiment, forming the first dielectric isolation region and the second dielectric region, alone or in combination with one or more of the first to fifth embodiments, includes depositing a dielectric layer (e.g., isolation layer 144) in the first isolation recess 124 and the second isolation recess 126, wherein the dielectric layer covers the planar active region 120, and performing a planarization operation on the dielectric layer to remove the dielectric layer from the planar active region 120, wherein the planarization operation results in the formation of the first dielectric isolation region 148 and the second dielectric isolation region 150.

[0117] Although Figure 7 An example block of process 700 is shown, but in some implementations, process 700 includes more... Figure 7 The block may be more, less, different, or arranged differently as described in the document. Alternatively, two or more blocks in process 700 may be executed in parallel.

[0118] In this manner, a semiconductor device is formed such that the isolation region between the medium-voltage transistor region and the low-voltage transistor region is fabricated to have characteristics different from those of the isolation region between low-voltage transistors in the low-voltage transistor region. The dual STI technique described herein is used to form the isolation region between low-voltage transistors in the low-voltage transistor region using low-voltage transistor isolation design rules, and additional STI forming operations can be performed to form the isolation region between the low-voltage transistor region and the medium-voltage transistor region. Specifically, the dual STI technique described herein can be used to form the isolation region between the low-voltage transistor region and the medium-voltage transistor region such that these isolation regions are deeper than other isolation regions in the semiconductor device. This allows the medium-voltage transistors in the medium-voltage transistor region to be placed closer to the low-voltage transistors in the low-voltage transistor region, while minimizing or eliminating the possibility of current leakage from the medium-voltage transistor affecting the performance of the low-voltage transistor and / or damaging the low-voltage transistor. Therefore, the dual STI technique described herein can achieve higher device density in semiconductor devices including high-voltage transistors, medium-voltage transistors, and low-voltage transistors.

[0119] In one embodiment of this disclosure, a method is disclosed. The method includes removing a first portion of a substrate of a semiconductor device to form a plurality of fin-shaped active regions. The method includes removing a second portion of the substrate to form a planar active region adjacent to the plurality of fin-shaped active regions, wherein removing the second portion of the substrate results in the formation of an isolation trench between the planar active region and the plurality of fin-shaped active regions, and the isolation trench has a first depth relative to the top of the planar active region after removing the second portion of the substrate. The method includes removing a third portion of the substrate from the isolation trench, wherein after removing the third portion of the substrate, the isolation trench has a second depth relative to the top of the planar active region, and the second depth is greater than the first depth. The method includes forming a dielectric isolation region in the isolation trench after removing the third portion.

[0120] In some embodiments, removing the third portion of the substrate from the isolation groove includes: removing the third portion of the substrate from the isolation groove while the plurality of fin-shaped active regions are covered by a shielding layer. In some embodiments, the shielding layer covers a first portion of the bottom surface of the isolation groove; and removing the third portion of the substrate from the isolation groove includes: removing the third portion of the substrate from a second portion of the bottom surface of the isolation groove adjacent to the first portion of the bottom surface of the isolation groove while the shielding layer covers the first portion of the bottom surface of the isolation groove. In some embodiments, after removing the third portion of the substrate, the first portion of the bottom surface of the isolation groove is at a second depth relative to the top of the planar active region; and the second portion of the bottom surface of the isolation groove is at a first depth relative to the top of the planar active region after removing the third portion of the substrate. In some embodiments, removing the third portion of the substrate from the isolation groove includes: removing the third portion of the substrate from the isolation groove after forming a fin-shaped cut area adjacent to the plurality of fin-shaped active regions, wherein the fin-shaped cut area extends to the side of the isolation groove. In some embodiments, the method further includes performing an etch-after cleaning of the isolation groove after removing the third portion of the substrate from the isolation groove. In some embodiments, removing the third portion of the substrate from the isolation groove includes removing the third portion of the substrate from the isolation groove after forming fin-cut regions across the plurality of fin-active regions, wherein the fin-cut regions extend in a direction approximately perpendicular to the isolation groove.

[0121] In another embodiment of this disclosure, a method is disclosed. The method includes removing a first portion of a substrate of a semiconductor device to form a plurality of finned active regions. The method includes removing a second portion of the substrate to form a planar active region adjacent to the plurality of finned active regions, wherein removing the second portion of the substrate results in the formation of a first isolation groove between a first side of the planar active region and the plurality of finned active regions, and a second isolation groove is formed adjacent to a second side of the planar active region relative to the first side, wherein after removing the second portion of the substrate, the bottom surface of the first isolation groove is at a first depth relative to the top of the planar active region, and wherein after removing the second portion of the substrate, the bottom surface of the second isolation groove is at a first depth relative to the top of the planar active region, and the first depth is greater than the fin height of the plurality of finned active regions. The method includes removing a third portion of the substrate from the first isolation groove and the second isolation groove, wherein after removing the third portion of the substrate, at least a portion of the bottom surface of the first isolation groove is at a second depth relative to the top of the planar active region, and wherein after removing the third portion of the substrate, the bottom surface of the second isolation groove is at a second depth relative to the top of the planar active region, and the second depth is greater than the first depth. The method includes forming a first dielectric isolation region in a first isolation groove and forming a second dielectric region in a second isolation groove after removing the third part.

[0122] In some embodiments, after the third portion of the substrate is removed, another portion of the bottom surface of the first isolation recess is at the first depth at the stepped portion of the first isolation recess. In some embodiments, when the third portion of the substrate is removed from the first isolation recess and the second isolation recess, a shielding layer covers the stepped portion of the first isolation recess. In some embodiments, after the third portion of the substrate is removed, a first thickness of the hard shielding layer on top of the planar active region is less than a second thickness of the hard shielding layer on top of the plurality of fin active regions. In some embodiments, removing the third portion of the substrate from the first isolation recess and the second isolation recess includes performing an etching operation to etch the substrate, thereby removing the third portion of the substrate from the first isolation recess and the second isolation recess, wherein an oxygen-containing gas is used to control the etch selectivity between the substrate and the hard shielding layer. In some embodiments, during the etching operation, the flow rate of the oxygen-containing gas is greater than 0 standard cubic centimeters per minute and less than or approximately equal to 15 standard cubic centimeters per minute. In some embodiments, forming the first dielectric isolation region and the second dielectric region includes: depositing a dielectric layer in the first isolation recess and the second isolation recess, wherein the dielectric layer covers the planar active region; and performing a planarization operation on the dielectric layer to remove the dielectric layer from the planar active region, wherein the planarization operation results in the formation of the first dielectric isolation region and the second dielectric region.

[0123] In another embodiment of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of finned active regions extending above a substrate of the semiconductor device. The semiconductor device includes one or more fin-based transistor structures on the plurality of finned active regions. The semiconductor device includes planar active regions extending above the semiconductor device. The semiconductor device includes laterally diffused metal-oxide-semiconductor (LDMOS) transistor structures on the planar active regions. The semiconductor device includes a dielectric isolation region between the planar active regions and the plurality of finned active regions, wherein the dielectric isolation region includes: a first portion, wherein the bottom surface of the dielectric isolation region is lower than the bottom surface of the plurality of finned active regions in the semiconductor device; and a second portion, wherein the bottom surface of the dielectric isolation region is lower than the bottom surface of the dielectric isolation region in the first portion in the semiconductor device.

[0124] In some embodiments, the first portion is adjacent to the planar active region; and the second portion is located between the first portion and the plurality of fin-like active regions. In some embodiments, a cut-fin isolation region is further included between the plurality of fin-like active regions and the dielectric isolation region. In some embodiments, the bottom surface of the dielectric isolation region in the first and second portions is lower than the top surface of one or more cut fins in the cut-fin isolation region in the semiconductor device. In some embodiments, the thickness of the dielectric isolation region decreases from the planar active region to the plurality of fin-like active regions. In some embodiments, a plurality of virtual fins are adjacent to the planar active region; and another dielectric isolation region is located between the planar active region and the plurality of virtual fins, wherein the other dielectric isolation region includes: a third portion, wherein the bottom surface of the other dielectric isolation region is lower than the bottom of the plurality of virtual fins in the semiconductor device; and a fourth portion, wherein the bottom surface of the other dielectric isolation region is lower than the bottom surface of the other dielectric isolation region in the third portion in the semiconductor device.

[0125] The terms "approximately" and "substantially" can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and are not intended to be limiting. It should be understood that, according to this disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0126] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: include: Multiple fin-shaped active regions extend onto the substrate of the semiconductor device; One or more fin-based transistor structures on the plurality of fin-shaped active regions; A planar active region extending onto the substrate of the semiconductor device; Laterally diffused metal-oxide-semiconductor transistor structure on the planar active region; as well as In the dielectric isolation region between the planar active region and the plurality of fin-shaped active regions The dielectric isolation region includes: In the first part, the bottom surface of the dielectric isolation region is lower than the bottom of the plurality of fin-shaped active regions in the semiconductor device; as well as In the second part, the bottom surface of the dielectric isolation region is lower than the bottom surface of the dielectric isolation region in the first part in the semiconductor device.

2. The semiconductor device according to claim 1, wherein The first portion is adjacent to the planar active region; and The second portion is located between the first portion and the plurality of fin-shaped active regions.

3. The semiconductor device according to claim 1, wherein Also includes: A cut-fin isolation region between the plurality of fin-shaped active regions and the dielectric isolation region.

4. The semiconductor device according to claim 3, characterized in that, The bottom surface of the dielectric isolation region in the first and second portions is lower than the top surface of one or more cleaving fins in the cleaving fin isolation region in the semiconductor device.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the dielectric isolation region decreases from the planar active region to the plurality of fin-shaped active regions.

6. The semiconductor device according to claim 1, characterized in that, Also includes: Multiple virtual fins adjacent to the planar active region; as well as In another dielectric isolation region between the planar active region and the plurality of virtual fins The other dielectric isolation region includes: The third part, wherein the bottom surface of the other dielectric isolation region is lower than the bottom of the plurality of virtual fins in the semiconductor device; as well as In the fourth part, the bottom surface of the other dielectric isolation region in the semiconductor device is lower than the bottom surface of the other dielectric isolation region in the third part.

7. The semiconductor device according to claim 4, characterized in that, The one or more cutting fins mentioned above include the remaining portion of the plurality of fin-shaped active regions.

8. The semiconductor device according to claim 1, characterized in that, Also includes: An isolation layer fills the dielectric isolation region and the space between the plurality of fin-shaped active regions.

9. The semiconductor device according to claim 4, characterized in that, The extension direction of one or more of the cutting fins is parallel to the extension direction of the dielectric isolation region.

10. The semiconductor device according to claim 1, characterized in that, The dielectric isolation region includes a first dielectric isolation region and a second dielectric isolation region, which are respectively formed on both sides of the planar active region.

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