Package structure and semiconductor device

Abstract

The utility model provides a kind of packaging structure and semiconductor device, the packaging structure includes: chip packaging copper sheet, the chip packaging copper sheet includes packaging copper sheet body, gate pin and source level pin, the gate pin and the source level pin are connected with the packaging copper sheet body, the packaging copper sheet body is connected with chip, in the packaging structure and semiconductor device provided in the utility model, pin and chip packaging copper sheet are combined together, improve the bonding strength between both, avoid the need for more connecting process between both separate, correspondingly, avoid the problem of the solder joint between pin and chip packaging copper sheet.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a packaging structure and a semiconductor device. Background Technology

[0002] Currently, most semiconductor packaging structures require leadframes, which are a crucial basic material in the electronics and information industry. Leadframes serve multiple functions, including supporting the chip, connecting internal chips to external circuit boards for electrical signals, and mounting and securing electronic components. The chip package copper sheet acts as a bridging structure, connecting the chip and its pins. It largely replaces the standard wire bonding method between the chip and pins, achieving unique package resistance values, higher current carrying capacity, and better thermal conductivity. Current chip leadframe packaging structures generally include a chip package copper sheet, leadframe, chip, and pins. The chip is connected to the leadframe, while the chip package copper sheet connects to both the chip and the pins. All components—chip package copper sheet, leadframe, chip, and pins—are encapsulated within a plastic package. When subjected to rapid temperature changes or bending due to mechanical strain or vibration, this packaging structure is prone to solder joint detachment between the pins and the chip package copper sheet, potentially leading to cracking of the plastic package and device failure. Utility Model Content

[0003] The purpose of this invention is to provide a packaging structure and semiconductor device to solve the problem that solder joints between pins and chip package copper sheets are prone to detachment in existing packaging structures.

[0004] To solve the above-mentioned technical problems, this utility model provides a packaging structure, the packaging structure comprising:

[0005] Lead frame;

[0006] The chip is connected to the lead frame;

[0007] A chip packaging copper sheet, comprising a copper sheet body, gate pins, and source pins, wherein the gate pins and the source pins are both connected to the copper sheet body, and the copper sheet body is connected to the chip; and...

[0008] The chip and the encapsulation copper sheet are both encapsulated within the molding compound.

[0009] Optionally, in the package structure described above, the gate pin and / or the source pin are exposed outside the plastic package.

[0010] Optionally, in the package structure described above, the gate pin and / or the source pin are gull-wing pin structures.

[0011] Optionally, in the aforementioned packaging structure, the chip package copper sheet further includes an electroplated layer, the gate pin and the source pin have ribbed surfaces, and the electroplated layer covers the gate pin and the source pin and exposes the ribbed surfaces.

[0012] Optionally, in the package structure, at least one of the gate pin and the source pin is integrally formed with the package copper sheet body.

[0013] Optionally, in the aforementioned packaging structure, the packaging copper sheet body includes a first packaging copper sheet body and a second packaging copper sheet body, the gate pin is integrally formed with the first packaging copper sheet body, and the source pin is integrally formed with the second packaging copper sheet body.

[0014] Optionally, in the packaging structure, the packaging copper sheet body and the chip are welded together.

[0015] Optionally, in the packaging structure, the lead frame includes opposing first and second surfaces, the first surface carrying the chip and encapsulating it within the molding compound, and the second surface exposed outside the molding compound.

[0016] Optionally, in the packaging structure, the chip and the lead frame are welded together.

[0017] This utility model also provides a semiconductor device, which includes: a printed circuit board and a package structure as described above, wherein the gate pin and source pin of the package structure are connected to the printed circuit board.

[0018] In the packaging structure and semiconductor device provided by this utility model, the packaging structure includes a chip packaging copper sheet, which includes a packaging copper sheet body, a gate pin, and a source pin. The gate pin and the source pin are both connected to the packaging copper sheet body. The packaging copper sheet body is connected to the chip. In the packaging structure and semiconductor device provided by this utility model, the pin and the chip packaging copper sheet are combined together, which improves the bonding strength between the two and avoids the need for an additional connection process due to their separation. Correspondingly, it avoids the problem of solder joint detachment between the pin and the chip packaging copper sheet. Attached Figure Description

[0019] Figure 1 This is a discrete schematic diagram of the packaging structure of an embodiment of the present utility model.

[0020] Figure 2 This is a partial schematic diagram of the packaging structure of an embodiment of the present utility model.

[0021] Figure 3 This is an overall schematic diagram of the packaging structure of an embodiment of the present utility model.

[0022] Figure 4 This is another overall schematic diagram of the packaging structure of this utility model embodiment.

[0023] Figure 5 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0024] Figure 6 This is a schematic diagram of a packaging structure.

[0025] The reference numerals in the attached figures are explained as follows:

[0026] 100 - Package structure; 110 - Lead frame; 1100 - First surface; 1101 - Second surface; 120 - Chip; 130 - Chip package copper sheet; 131 - Package copper sheet body; 1310 - First package copper sheet body; 1311 - Second package copper sheet body; 132 - Gate pin; 133 - Source pin; 134 - Electroplated layer; 1340 - Beam cut surface; 1341 - Straight portion; 1342 - Bending portion; 140 - Molded package; 150 - First solder layer; 151 - Second solder layer; 200 - Printed circuit board; 332 - Gate pin; 333 - Source pin; 340 - Molded package; 10 - Semiconductor device. Detailed Implementation

[0027] The packaging structure and semiconductor device proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0028] The terminology used in this utility model is for the purpose of describing particular embodiments only and is not intended to limit the utility model. Unless otherwise defined in this application, the technical or scientific terms used in this utility model should be understood in their ordinary sense by one of ordinary skill in the art to which this utility model pertains. The words "first," "second," and similar terms used in this utility model specification and claims do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, the words "a" or "one" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, the words "upper / upper layer" and / or "lower / lower layer" and similar terms are for ease of description only and are not limited to a location or spatial orientation. The words "comprising" or "including" and similar terms mean that the elements or structures preceding "comprising" or "including" cover the elements or structures listed after "comprising" or "including" and their equivalents, and do not exclude other elements or structures. The words "connected" or "linked" and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0029] Please refer to Figures 1 to 4 ,in, Figure 1 This is a discrete schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 2 This is a partial schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 3 This is an overall schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 4 This is another overall schematic diagram of the packaging structure of this utility model embodiment.

[0030] like Figures 1 to 4 As shown in this embodiment, the packaging structure 100 includes: a lead frame 110; a chip 120 connected to the lead frame 110; a chip encapsulation copper sheet 130, which includes an encapsulation copper sheet body 131, a gate pin 132, and a source pin 133, both of which are connected to the encapsulation copper sheet body 131, and the encapsulation copper sheet body 131 is connected to the chip 120; and a molding compound 140, in which the chip 120 and the encapsulation copper sheet body 131 are both encapsulated.

[0031] In this embodiment, the gate pin 132 and the source pin 133 are combined with the packaged copper sheet body 131, which improves the bonding strength between the gate pin 132 and the source pin 133 and the packaged copper sheet body 131, avoiding the need for an extra connection process due to separation, and correspondingly avoiding the problem of solder joint detachment between the pin and the chip packaged copper sheet.

[0032] like Figures 1 to 4 As shown in this embodiment, the gate pin 132 and the source pin 133 are exposed outside the molding compound 140. In other embodiments of this application, one of the gate pin 132 and the source pin 133 may be exposed outside the molding compound 140, while the other is encapsulated within the molding compound 140. Exposing the gate pin 132 and the source pin 133 outside the molding compound 140 improves the compliance of the package structure 100. When subjected to rapid temperature changes or bending due to mechanical strain or vibration, the gate pin 132 and / or the source pin 133 can adapt to the changes, thereby further improving the connection reliability within the package structure 100 and preventing problems such as cracking of the molding compound 140 and device failure.

[0033] In some embodiments of this application, both the gate pin 132 and the source pin 133 are gull-wing pin structures. In other embodiments of this application, only one of the gate pin 132 and the source pin 133 may be a gull-wing pin structure, while the other may be, for example, a straight pin, a J-type pin, an L-type pin, etc. The gull-wing pin structure has a larger bottom and side surface area, increasing the connection surface between the package structure 100 and other structures, thereby improving the connection strength and reliability between the package structure 100 and other structures.

[0034] like Figure 3As shown, in some embodiments of this application, the chip package copper sheet 130 further includes an electroplated layer 134. The gate pin 132 and the source pin 133 have a chamfered surface 1340. The electroplated layer 134 covers the gate pin 132 and the source pin 133 and exposes the chamfered surface 1340. In some embodiments of this application, the electroplated layer 134 can be formed by electroplating on the gate pin 132 and the source pin 133 first. Then, chamfering is performed on the gate pin 132 and the source pin 133 to expose the chamfered surface 1340. Thus, the electroplated layer 134 can improve the connection reliability of the gate pin 132 and the source pin 133 with other structures. At the same time, by electroplating first and then chamfering, the electroplated layer 134 exposes the chamfered surface 1340, which can improve the quality of the gate pin 132 and the source pin 133 and avoid defects such as adhesion between them.

[0035] In some embodiments of this application, at least one of the gate pin 132 and the source pin 133 is integrally formed with the package copper body 131. For example... Figure 1 and Figure 2 As shown in this embodiment, the encapsulated copper sheet body 131 includes a first encapsulated copper sheet body 1310 and a second encapsulated copper sheet body 1311. The gate pin 132 is integrally formed with the first encapsulated copper sheet body 1310, and the source pin 133 is integrally formed with the second encapsulated copper sheet body 1311. Therefore, the connection reliability and compliance between the gate pin 132 and the encapsulated copper sheet body 131, as well as between the source pin 133 and the encapsulated copper sheet body 131, are higher, improving the quality and reliability of the encapsulation structure 100.

[0036] In this embodiment, the encapsulated copper sheet body 131 and the chip 120 are soldered together. Here, both the first encapsulated copper sheet body 1310 and the second encapsulated copper sheet body 1311 are soldered together with the chip 120. The gate pin 132 is integrally formed with the first encapsulated copper sheet body 1310, and the source pin 133 is integrally formed with the second encapsulated copper sheet body 1311. Accordingly, the connection between the gate pin 132 and the chip 120, and the connection between the source pin 133 and the chip 120, are achieved through a single soldering operation, thereby simplifying the manufacturing process and improving connection reliability.

[0037] like Figures 1 to 4As shown in this embodiment, the lead frame 110 includes a first surface 1100 and a second surface 1101 facing each other. The first surface 1100 carries the chip 120 and is encapsulated within the molding compound 140. The second surface 1101 is exposed outside the molding compound 140 for better heat dissipation. In this embodiment, the chip 120 and the lead frame 110 are welded together, wherein the chip 120 is welded to the first surface 1100 of the lead frame 110.

[0038] like Figure 1 As shown, in some embodiments of this application, the packaging structure 100 may include: the lead frame 110, a first solder layer 150 disposed on the lead frame 110, the chip 120 disposed on the first solder layer 150, a second solder layer 151 disposed on the chip 120, and a chip packaging copper sheet 130 disposed on the second solder layer 151. The chip 120 can be fixedly connected to the lead frame 110 through the first solder layer 150, and the chip packaging copper sheet 130 can be fixedly connected to the chip 120 through the second solder layer 151.

[0039] In this embodiment, the gate pin 132 and the source pin 133 are combined with the packaged copper sheet body 131. The connection between the gate pin 132 and the source pin 133 in the lead frame 110, the chip 120, and the chip packaged copper sheet 130 can be achieved solely through the first solder layer 150 and the second solder layer 151, resulting in a simple process and high reliability. Furthermore, in this embodiment, the first solder layer 150 and the second solder layer 151 are respectively located on the lead frame 110, allowing the lead frame 110 to support the corresponding solder joints, thereby improving the reliability of the connection.

[0040] In the packaging structure 100 provided in this application embodiment, the gate pin 132 and the source pin 133 are combined with the packaging copper sheet body 131, which simplifies the connection of the packaging structure 100, improves the bonding strength between the gate pin 132 and the source pin 133 and the packaging copper sheet body 131, avoids the need for an extra connection process due to separation, and correspondingly avoids the problem of solder joint detachment between the pin and the chip packaging copper sheet.

[0041] This application also provides a semiconductor device, please refer to... Figure 5 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 5As shown in the embodiment of this application, the semiconductor device 10 includes: a printed circuit board 200 and a package structure 100, wherein the gate pin 132 and the source pin 133 of the package structure 100 are connected to the printed circuit board 200.

[0042] like Figure 5 As shown in the embodiment of this application, the gate pin 132 and the source pin 133 are exposed outside the molding compound 140. Please refer to the reference. Figure 6 In contrast to the molding compound 340, which only exposes the connection surfaces of the gate pin 332 and the source pin 333, in this embodiment, the gate pin 132 and the source pin 133 are exposed outside the molding compound 140. This facilitates the connection between the package structure 100 and the printed circuit board 200, reduces manufacturing complexity, and improves the compliance of the package structure 100. When the semiconductor device 10 is subjected to rapid temperature changes or bends due to mechanical strain or vibration, the exposed gate pin 132 and the source pin 133 allow the package structure 100 to adapt to the changes in the printed circuit board 200, thereby improving the connection reliability between the package structure 100 and the printed circuit board 200. It also avoids problems such as solder joint detachment and molding compound cracking caused by poor compliance between the package structure and the printed circuit board, thus ensuring the reliability of the package structure 100.

[0043] Please refer to the reference. Figures 1 to 6 In this embodiment of the application, both the gate pin 132 and the source pin 133 are gull-wing pin structures. Figure 3 and Figure 5 As shown in this embodiment, both the gate pin 132 and the source pin 133 include a straight portion 1341 and a bent portion 1342, which are connected. The straight portion 1341 is used to connect to the printed circuit board 200. The flat surface of the straight portion 1341 facilitates connection to the printed circuit board 200, and its large connection surface improves connection reliability. The bent portion 1342 improves the compliance between the package structure 100 and the printed circuit board 200. When the printed circuit board 200 expands, shrinks, or bends due to temperature changes or stress, the bent portion 1342 adapts to the deformation, resulting in better compliance between the package structure 100 and the printed circuit board 200, thus improving the quality and reliability of the package structure 100, the printed circuit board 200, and the semiconductor device 10.

[0044] In some embodiments of this application, the chip package copper sheet 130 further includes an electroplated layer 134, and the gate pin 132 and the source pin 133 have truncated surfaces 1340. The electroplated layer 134 covers the gate pin 132 and the source pin 133 and exposes the truncated surfaces 1340. The electroplated layer 134 facilitates the connection between the gate pin 132 and the source pin 133 and the printed circuit board 200, for example, through soldering, and improves connection reliability.

[0045] In the packaging structure 100 and semiconductor device 10 provided in the embodiments of this application, the packaging structure 100 includes a chip packaging copper sheet 130. The chip packaging copper sheet 130 includes a packaging copper sheet body 131, a gate pin 132, and a source pin 133. The gate pin 132 and the source pin 133 are both connected to the packaging copper sheet body 131. The packaging copper sheet body 131 is connected to the chip 120. In the packaging structure 100 and semiconductor device 10 provided in this utility model, the pins and the chip packaging copper sheet are combined together, which improves the bonding strength between the two and avoids the need for an additional connection process due to their separation. Correspondingly, it avoids the problem of solder joint detachment between the pins and the chip packaging copper sheet.

[0046] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.

[0047] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. A package structure, characterized by, The packaging structure includes: Lead frame; The chip is connected to the lead frame; A chip packaging copper sheet, comprising a copper sheet body, gate pins, and source pins, wherein the gate pins and the source pins are both connected to the copper sheet body, and the copper sheet body is connected to the chip; and... The chip and the encapsulation copper sheet are both encapsulated within the molding compound.

2. The package structure of claim 1, wherein, The gate pin and / or the source pin are exposed outside the plastic package.

3. The package structure of claim 1, wherein, The gate pin and / or the source pin are gull-wing pin structures.

4. The package structure of any one of claims 1-3, wherein, The chip package copper sheet also includes an electroplating layer, and the gate pin and the source pin have ribbed surfaces. The electroplating layer covers the gate pin and the source pin and exposes the ribbed surfaces.

5. The packaging structure as described in any one of claims 1 to 3, characterized in that, At least one of the gate pin and the source pin is integrally formed with the packaged copper body.

6. The packaging structure as described in claim 5, characterized in that, The encapsulated copper sheet body includes a first encapsulated copper sheet body and a second encapsulated copper sheet body. The gate pin is integrally formed with the first encapsulated copper sheet body, and the source pin is integrally formed with the second encapsulated copper sheet body.

7. The package structure of any one of claims 1-3, wherein, The encapsulated copper sheet body and the chip are welded together.

8. The packaging structure as described in any one of claims 1 to 3, characterized in that, The lead frame includes opposing first and second surfaces, the first surface carrying the chip and encapsulating it within the molding compound, and the second surface exposed outside the molding compound.

9. The package structure of any one of claims 1-3, wherein, The chip and the lead frame are welded together.

10. A semiconductor device, characterized in that, The semiconductor device includes: a printed circuit board and a package structure as described in any one of claims 1 to 9, wherein the gate pin and source pin of the package structure are connected to the printed circuit board.

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