A packaged chip
By using a SiC-MOS transistor and controller co-packaged structure, the problems of high parasitic parameters, low power density and heat dissipation difficulties in traditional designs are solved, achieving higher power density and EMI performance, and improving the heat dissipation and reliability of the packaged chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHONGQING PINGWEI ENTERPRISE
- Filing Date
- 2025-06-17
- Publication Date
- 2026-06-19
AI Technical Summary
In traditional single-ended flyback topology switching power supplies, the separate design of the controller and power devices leads to high parasitic parameters, low power density, and difficulty in heat dissipation. SJ-MOS transistors and GaN devices also have limitations.
The controller adopts a package structure that combines SiC-MOS transistors and controllers, with base island isolation and pins brought out. The controller and SiC-MOS transistors are electrically isolated. The package design is DIP-7L. The controller includes a quasi-resonant controller and an optimized heat dissipation structure.
It reduces package size, decreases parasitic inductance and capacitance, improves power density and EMI performance, enhances heat dissipation, and improves system reliability.
Smart Images
Figure CN224386128U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power electronic devices, specifically to a packaged chip. Background Technology
[0002] In current power electronic systems, the increasing demand for high efficiency, high power density, and high reliability places higher demands on the performance and integration of power devices and controllers. Traditional single-ended flyback topology switching power supplies employ a separate controller and power device design, which presents the following problems: ① High parasitic parameters: External connections between the controller and power devices introduce additional parasitic inductance and capacitance, leading to increased switching losses and reduced efficiency. ② Low power density: The separate design occupies a large PCB area, making it difficult to meet high power density requirements. ③ Difficult heat dissipation: Heat is dispersed between the power devices and the controller, resulting in complex heat dissipation paths. In related technologies, the controller is packaged with a traditional SJ-MOS transistor, but the SJ-MOS transistor has a large package area, slow switching speed, and high switching losses. Furthermore, the SJ-MOS transistor requires a negative voltage to turn off, limiting its application. Another approach involves packaging gallium nitride (GaN) devices, but GaN devices themselves have poor thermal stability, and e-mode GaN devices have low gate drive voltages, leading to many limitations in drive circuit design and practical applications. Utility Model Content
[0003] In view of the shortcomings of the prior art described above, the present invention provides a packaged chip to solve at least one of the above-mentioned technical problems.
[0004] To achieve the above and other related objectives, the technical solution provided in this application is as follows.
[0005] This application provides a packaged chip, comprising: a controller for adjusting the output voltage according to the load, a SiC-MOS transistor for responding to the output voltage, a first base island, a second base island, and a package body. The output terminal of the controller is connected to the gate of the SiC-MOS transistor, and the chip select terminal of the controller is connected to the source of the SiC-MOS transistor. The controller is disposed on the first base island, the SiC-MOS transistor is disposed on the second base island, and the drain of the SiC-MOS transistor is connected to the second base island. The first base island and the second base island are disposed within the package body.
[0006] In one embodiment of this utility model, the controller and the SiC-MOS transistor are led out through the package body to the corresponding pins of the packaged chip.
[0007] In one embodiment of the present invention, two pins of the packaged chip are disposed on the second base island, and each pin on the second base island is respectively connected to the drain of the SiC-MOS transistor.
[0008] In one embodiment of the present invention, the chip select terminal of the controller is connected to the second base island via a bonding wire, and the second base island is connected to the source of the SiC-MOS transistor via a bonding wire.
[0009] In one embodiment of the present invention, the first base island and the second base island are spaced apart.
[0010] In one embodiment of the present invention, the area of the first base island is larger than the area of the second base island.
[0011] In one embodiment of this utility model, the packaging structure of the packaged chip is DIP-7L.
[0012] In one embodiment of the present invention, the controller includes a quasi-resonant controller.
[0013] This application provides a packaged chip including a controller for adjusting the output voltage according to the load, a SiC-MOS transistor for responding to the output voltage, a first base island, a second base island, and a package. The output terminal of the controller is connected to the gate of the SiC-MOS transistor, and the chip select terminal of the controller is connected to the source of the SiC-MOS transistor. The controller is disposed on the first base island, and the SiC-MOS transistor is disposed on the second base island. The drain of the SiC-MOS transistor is connected to the second base island, and the first and second base islands are disposed within the package. The package provided in this application uses a 0V off SiC-MOS transistor and controller encapsulated together, resulting in a smaller junction capacitance. The package area is smaller than that of the SJ-MOS transistor in the prior art, effectively reducing the device's footprint and increasing power density. Furthermore, it shortens the connection line length between the controller and the SiC-MOS transistor, significantly reducing parasitic inductance and capacitance compared to traditional discrete device connection methods. During the operation of the SiC-MOS transistor, the rate of change of voltage and current is effectively controlled, reducing electromagnetic interference and improving the system's EMI performance. The encapsulated chip also has better heat dissipation.
[0014] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description
[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments conforming to the present invention and, together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:
[0016] Figure 1 This is a schematic diagram of the packaged chip shown in an exemplary embodiment of the present invention;
[0017] Figure 2 This is a schematic diagram illustrating the packaged chip after it has been packaged, as shown in an exemplary embodiment of this utility model;
[0018] Figure 3 This is an exemplary embodiment of the present invention, showing a detailed structural diagram of the controller and SiC-MOS transistor in the packaged chip;
[0019] Reference numerals: 110-Controller; 120-SiC-MOS transistor; 310-Sampling module; 320-Undervoltage lockout module; 330-Enable startup module; 340-Control module; 350-Detection module. Detailed Implementation
[0020] The embodiments of this utility model will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. It should be understood that the preferred embodiments are only for illustrating this utility model and not for limiting the scope of protection of this utility model.
[0021] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0022] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present invention.
[0023] SJ-MOSFET (Super Junction MOSFET) is a high-voltage power MOSFET that optimizes the trade-off between on-resistance (RDS(on)) and breakdown voltage (Breakdown Voltage) of traditional MOSFETs through a special super junction structure, making it suitable for high-efficiency, high-voltage switching applications.
[0024] SiC-MOSFET (Silicon Carbide MOSFET) is a wide-bandgap semiconductor power device based on silicon carbide (SiC) material. Compared with traditional silicon-based MOSFETs (such as SJ-MOS), it has advantages such as higher voltage withstand, higher switching frequency, and lower loss.
[0025] In current power electronic systems, the increasing demand for high efficiency, high power density, and high reliability places higher demands on the performance and integration of power devices and controllers. Traditional single-ended flyback topology switching power supplies employ a separate controller and power device design, which presents the following problems: ① High parasitic parameters: External connections between the controller and power devices introduce additional parasitic inductance and capacitance, leading to increased switching losses and reduced efficiency. ② Low power density: The separate design occupies a large PCB (Printed Circuit Board) area, making it difficult to meet high power density requirements. ③ Difficult heat dissipation: Heat is dispersed between the power devices and the controller, resulting in complex heat dissipation paths.
[0026] In related technologies, the controller is packaged with a traditional SJ-MOS transistor. However, the SJ-MOS transistor has a large package area, slow switching speed, and high switching losses. Furthermore, the SJ-MOS transistor requires a negative voltage to turn off, which limits its application. Another approach is to package gallium nitride (GaN) devices. However, GaN devices have poor thermal stability, and e-mode GaN devices have low gate drive voltages, which imposes many limitations on drive circuit design and practical use.
[0027] To solve the above problems, such as Figure 1 As shown, this application provides a packaged chip, including: a controller 110 for adjusting the output voltage according to the load, a SiC-MOS transistor 120 for responding to the output voltage, a first base island, a second base island, and a package body. The output terminal of the controller 110 is connected to the gate of the SiC-MOS transistor 120, the chip select terminal of the controller 110 is connected to the source of the SiC-MOS transistor 120, the controller 110 is disposed on the first base island, the SiC-MOS transistor 120 is disposed on the second base island, the drain of the SiC-MOS transistor 120 is connected to the second base island, and the first base island and the second base island are disposed within the package body.
[0028] like Figure 1 As shown, the controller 110 and the SiC-MOS transistor 120 are led out to the corresponding pins of the packaged chip through the package body. The chip select terminal of the controller 110 is connected to the second base island via a bonding wire, and the second base island is connected to the source of the SiC-MOS transistor 120 via a bonding wire. Specifically, as shown... Figure 1 As shown, the power supply terminal of controller 110 is connected to the power supply pin of the package via a bonding wire; the compensation terminal of controller 110 is connected to the compensation pin of the package via a bonding wire; the feedback terminal of controller 110 is connected to the feedback pin of the package via a bonding wire; the ground terminal of controller 110 is connected to the ground terminal of the package via a bonding wire; the chip select terminal of controller 110 is connected to the chip select pin of the package via a bonding wire; the output terminal of controller 110 is connected to the gate of SiC-MOS transistor 120 via a bonding wire; the chip select terminal of controller 110 is connected to the source of SiC-MOS transistor 120 via a bonding wire; the drain of SiC-MOS transistor 120 is connected to the second base island, and the corresponding pin of the package is led out through the second base island.
[0029] It should be noted that the first and second base islands are made of metal and have electrical conductivity.
[0030] like Figure 1 As shown, the second base island has two pins (2 DRAINs) of the packaged chip, and each pin on the second base island is connected to the drain of the SiC-MOS transistor 120.
[0031] In detail, such as Figure 1 As shown, the first base island and the second base island are spaced apart to achieve electrical isolation between the controller 110 and the SiC-MOS transistor 120, thereby reducing signal interference.
[0032] In detail, such as Figure 1 As shown, to enhance the heat dissipation capability of the packaged chip, the area of the first base island is larger than that of the second base island.
[0033] More in detail, such as Figure 2 As shown, the package structure of the packaged chip is DIP-7L.
[0034] In detail, controller 110 includes a quasi-resonant controller, for example, the controller includes an MK2606S chip.
[0035] In detail, such as Figure 3As shown, the controller 110 includes a sampling module 310 for sampling the source of the SiC-MOS transistor 120, an undervoltage lockout module 320 for shutting down the controller 110 when the power supply VCC is lower than a preset power supply threshold, and an enable / start module 330 for controlling the controller 110. The input terminal of the sampling module 310 is connected to the source of the SiC-MOS transistor 120 and the chip select pin of the package. The input terminal of the undervoltage lockout module 320 is connected to the power supply pin of the package. The first input terminal of the enable / start module 330 is connected to the output terminal of the undervoltage lockout module 320, and the second input terminal of the enable / start module 330 is connected to the output terminal of the sampling module 310.
[0036] More in detail, such as Figure 3 As shown, the controller 110 also includes a data processing module 340 for processing various data and a detection module 350 for detecting the load operating status. The first input terminal of the data processing module 340 is connected to the compensation pin of the package, the second input terminal of the data processing module 340 is connected to the sampling module 310, the third input terminal of the data processing module 340 is connected to the enable module 330, the first output terminal of the data processing module 340 is connected to the gate of the SiC-MOS transistor 120, the second output terminal of the data processing module 340 is connected to the third input terminal of the enable module 330, the input terminal of the detection module 350 is connected to the feedback terminal of the package, and the output terminal of the detection module 350 is connected to the fourth input terminal of the enable module 330 and the fourth input terminal of the data processing module 340.
[0037] More in detail, such as Figure 3 As shown, the detection module 350 includes a valley detection unit for detecting the valley value corresponding to the load operation feedback voltage and a voltage detection unit for detecting the load operation feedback voltage. The input terminals of the valley detection unit and the voltage detection unit are connected to the feedback pin of the package. The output terminal of the valley detection unit is connected to the fourth input terminal of the data processing module 340, and the output terminal of the voltage detection unit is connected to the fourth input terminal of the enable module 330.
[0038] More in detail, such as Figure 3As shown, the data processing module 340 includes a first resistor R1, a second resistor R2, a first comparator AMP1, and a second comparator AMP2. The first end of the first resistor R1 is grounded after passing through the second resistor R2. The first end of the first resistor R1 is also connected to the first input terminal of the first comparator AMP1. The output terminal of the first comparator AMP1 is connected to the first input terminal of the second comparator AMP2. The positive power supply terminal of the second comparator AMP2 is connected to the power supply VCC, and the negative power supply terminal of the second comparator AMP2 is grounded. The second end of the first resistor R1 is the first input terminal of the data processing module 340. The second input terminal of the first comparator AMP1 is the second input terminal of the data processing module 340. The second input terminal of the second comparator AMP2 is the third input terminal of the data processing module 340. The third input terminal of the second comparator AMP2 is the fourth input terminal of the data processing module 340. The output terminal of the second comparator AMP2 is the first output terminal of the data processing module 340, and the first input terminal of the first comparator AMP1 is the second output terminal of the data processing module 340. A clamping module can also be installed between the positive power supply terminal of the second comparator AMP2 and the power supply VCC to limit the power supply VCC from exceeding the safe range and prevent damage to the second comparator AMP2.
[0039] like Figures 1 to 3 As shown, the working principle of the packaged chip provided in this application is as follows:
[0040] like Figure 1-2 As shown, the packaged chip provided in this application includes a controller 110 and a SiC-MOS transistor 120. The SiC-MOS transistor 120 is a 0V off device with a smaller junction capacitance. Therefore, a 340mohm SiC-MOS transistor can replace a 180mohm SJ-MOS transistor. Furthermore, the area of the packaged chip corresponding to the SiC-MOS transistor is 1 / 3 of that of the packaged chip corresponding to the SJ-MOS transistor, which reduces the area of the device on the PCB board and improves the power density.
[0041] When the packaged chip is operating, the undervoltage lockout module 320 cuts off power to the controller 110 when the input voltage is lower than the preset power supply threshold, causing the controller 110 to stop working. The sampling module 310 collects the load current, the detection module 350 detects the valley voltage of the load feedback and the undervoltage and overvoltage conditions of the feedback voltage, and the data processing module 340 collects the load compensation value. Based on the voltage values output by each module, the data processing module 340 enables the controller 110 to adjust the control strategy according to the real-time load conditions. During operation, the controller 110 adaptively adjusts the SiC-MOS transistor 120 to operate in discontinuous conduction mode / quasi-resonant mode based on the voltage of the compensation pin and feedback pin of the package, and uses valley switching as much as possible. The controller 110 adjusts the control mode and switching frequency by monitoring the voltage of the package feedback pin, and simultaneously uses frequency jitter to optimize electromagnetic interference. Under light load, the packaged chip enters green mode, adjusting the switching frequency to 25kHz to reduce switching losses; Figure 2 The diagram shown is a schematic of the packaged chip.
[0042] It should be noted that the above working principle describes the working state of the controller 110 and the SiC-MOS transistor, which are the functions of the controller 110 and the SiC-MOS transistor itself, and do not involve any innovation in the devices themselves.
[0043] This application provides a packaged chip, which includes a controller for adjusting the output voltage according to the load, a SiC-MOS transistor for responding to the output voltage, a first base island, a second base island, and a package body. The output terminal of the controller is connected to the gate of the SiC-MOS transistor, and the chip select terminal of the controller is connected to the source of the SiC-MOS transistor. The controller is disposed on the first base island, the SiC-MOS transistor is disposed on the second base island, and the drain of the SiC-MOS transistor is connected to the second base island. The first base island and the second base island are disposed within the package body. The packaged chip provided in this application uses a 0V off SiC-MOS transistor and a controller in a single package, resulting in a smaller junction capacitance. The packaged chip has a smaller area than existing SJ-MOS transistors, effectively reducing the device's footprint and increasing power density. Furthermore, it shortens the connection length between the controller and the SiC-MOS transistor, significantly reducing parasitic inductance and capacitance compared to traditional discrete device connections. During SiC-MOS transistor operation, the rate of change of voltage and current is effectively controlled, reducing electromagnetic interference and improving the system's electromagnetic interference performance. The heat generated by the controller and SiC-MOS transistor can be more concentratedly transferred to the package's heat dissipation structure. By optimizing the package's heat dissipation design, such as increasing the heat sink area and using high-efficiency heat dissipation materials, the chip's temperature can be kept within a reasonable range during operation, improving chip reliability and lifespan.
[0044] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.
Claims
1. A packaged chip, characterized in that, include: A controller for adjusting the output voltage according to the load, a SiC-MOS transistor for responding to the output voltage, a first base island, a second base island, and a package. The output terminal of the controller is connected to the gate of the SiC-MOS transistor, and the chip select terminal of the controller is connected to the source of the SiC-MOS transistor. The controller is disposed on the first base island, the SiC-MOS transistor is disposed on the second base island, and the drain of the SiC-MOS transistor is connected to the second base island. The first base island and the second base island are disposed within the package.
2. The packaged chip according to claim 1, characterized in that, The controller and the SiC-MOS transistor are led out through the package body to the corresponding pins of the packaged chip.
3. The packaged chip according to claim 2, characterized in that, The second base island has two pins of the packaged chip, and each pin on the second base island is connected to the drain of the SiC-MOS transistor.
4. The packaged chip according to claim 1, characterized in that, The chip select terminal of the controller is connected to the second base island via a bonding wire, and the second base island is connected to the source of the SiC-MOS transistor via a bonding wire.
5. The packaged chip according to claim 1, characterized in that, The first base island and the second base island are spaced apart.
6. The packaged chip according to claim 1, characterized in that, The area of the first base island is larger than the area of the second base island.
7. The packaged chip according to claim 1, characterized in that, The packaged chip has a DIP-7L packaging structure.
8. The packaged chip according to claim 1, characterized in that, The controller includes a quasi-resonant controller.