Line structure
By using symmetrical wiring blocks to form capacitor modules in a multi-chip package structure, the problems of large capacitor area and noise are solved, and the miniaturization of electronic packages and the improvement of signal quality are realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SILICONWARE PRECISION IND CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-06-19
Smart Images
Figure CN224386131U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a circuit structure, and more particularly to a circuit structure having a capacitor module. Background Technology
[0002] With the booming development of portable electronic products in recent years, various related electronic products are also developing in accordance with the trends of high density, high performance, and lightness, thinness, shortness, and smallness. At the same time, semiconductor devices are also gradually moving towards heterogeneous integration, and for this reason, three-dimensional (3D) multi-chip packaging module related technologies are gradually emerging.
[0003] In existing multi-chip packaging structures, capacitors are often placed on printed circuit boards (PCBs), resulting in excessive PCB area occupied by capacitors. This makes it difficult to reduce the overall size of electronic packages and meet the requirements of being lightweight, thin, short, and small. Furthermore, when there are too many discrete capacitors or integrated capacitors such as die-side capacitors (DSCs) and integrated passive device (IPD) silicon capacitors within an electronic package, excessive noise can be generated, leading to a degrade of power and signal quality within the electronic package.
[0004] Therefore, overcoming the various problems of the existing technologies has become a pressing issue that the industry urgently needs to address. Utility Model Content
[0005] In view of the various deficiencies of the prior art, this application provides a circuit structure, including: a dielectric material; two wiring blocks, which are covered in the dielectric material and respectively include a first wiring layer and a second wiring layer located above the first wiring layer; and a line block, which is covered in the dielectric material and includes at least one line layer; wherein the two wiring blocks are spaced apart by a distance and are adjacent to each other and symmetrically arranged to form a capacitor module.
[0006] In the aforementioned circuit structure, each wiring block contains a through conductive via, and each through conductive via passes through the dielectric material from the top of the wiring block and is electrically connected to the first wiring layer and the second wiring layer.
[0007] In the aforementioned circuit structure, each wiring block contains an interlayer conductive via corresponding to the through conductive via, and each interlayer conductive via is electrically connected to the second wiring layer through conductive via after passing through the dielectric material from the top of the wiring block.
[0008] In the aforementioned circuit structure, the two through-holes in the two wiring blocks are symmetrically arranged in the capacitor module.
[0009] In the aforementioned circuit structure, the interlayer conductive via in one of the two wiring blocks and the interlayer conductive via in the other wiring block are symmetrically arranged in the capacitor module.
[0010] In the aforementioned circuit structure, the two through-holes in the two wiring blocks are arranged adjacent to each other in the capacitor module.
[0011] In the aforementioned circuit structure, the two through-holes in the two wiring blocks are disposed far apart from each other in the capacitor module.
[0012] In the aforementioned circuit structure, the interlayer conductive via in one wiring block and the interlayer conductive via in another wiring block are disposed adjacent to each other in the capacitor module.
[0013] In the aforementioned circuit structure, the interlayer conductive via in one wiring block and the interlayer conductive via in another wiring block are disposed far apart from each other in the capacitor module.
[0014] In the aforementioned circuit structure, each of the through-holes and interlayer conductive vias exposed on the end face of the dielectric material is respectively formed with an electrical connection pad.
[0015] As can be seen from the above, this application replaces the capacitors mounted on the circuit board in existing electronic packages with capacitor modules formed by symmetrical wiring blocks, thus significantly reducing the area and volume of the electronic package. Furthermore, by reducing the number of existing discrete capacitors in the package, the noise generated by discrete capacitors can be effectively reduced, thereby greatly improving the power and signal quality within the electronic package. Attached Figure Description
[0016] Figure 1A This is a partial cross-sectional schematic diagram of an embodiment of the circuit structure of this application.
[0017] Figure 1B for Figure 1A A top view schematic diagram of the capacitor module in the diagram.
[0018] Figure 2A This is a partial cross-sectional schematic diagram of another embodiment of the circuit structure of this application.
[0019] Figure 2B for Figure 2A A top view schematic diagram of the capacitor module in the diagram.
[0020] Figure 3 This is a cross-sectional schematic diagram of an embodiment of an electronic package having the circuit structure of this application.
[0021] Explanation of reference numerals in the attached figures
[0022] 1 Electronic package
[0023] 10. Bearing components
[0024] 20 Package Module
[0025] 20a Circuit Structure
[0026] 21 Dielectric Materials
[0027] 22R, 22L cabling blocks
[0028] 221a First Wiring Layer
[0029] 221b Second Wiring Layer
[0030] 222R, 222L through conductive vias
[0031] 223R, 223L interlayer conductive vias
[0032] 224 Electrical Connector Pad
[0033] 225 Support component
[0034] 23 Line Blocks
[0035] 231 Line Layer
[0036] 24 Electronic Components
[0037] CM capacitor module. Detailed Implementation
[0038] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0039] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "below," "one," "first," and "second" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0040] Figure 1A This is a partial cross-sectional schematic diagram of an embodiment of the circuit structure of this application; Figure 1B for Figure 1A A top view schematic diagram of the capacitor module; Figure 2A This is a partial cross-sectional schematic diagram of another embodiment of the circuit structure of this application; Figure 2B for Figure 2A A top view schematic diagram of the capacitor module; Figure 3 This is a cross-sectional schematic diagram of an embodiment of an electronic package having the circuit structure of this application.
[0041] like Figure 1A and Figure 1B As shown, this embodiment provides a circuit structure 20a, which can be applied to a redistributed line layer (RDL) structure, substrate, interposer, or circuit board. This embodiment is described using a redistributed line layer structure. The circuit structure 20a includes: a dielectric material 21, two wiring blocks 22R, 22L, and a circuit block 23. Each wiring block 22R, 22L includes a first wiring layer 221a and a second wiring layer 221b located above the first wiring layer 221a. The first wiring layer 221a and the second wiring layer 221b are covered by the dielectric material 21. The two wiring blocks 22R, 22L are spaced apart and adjacent to each other and symmetrically arranged to form a capacitor module CM.
[0042] Specifically, in the circuit structure 20a shown in this embodiment, each wiring block 22R, 22L contains a through-hole 222R, 222L that passes through the dielectric material 21 from the top of the wiring block 22R, 22L and electrically connects the first wiring layer 221a and the second wiring layer 221b. Simultaneously, each wiring block 22R, 22L also contains interlayer conductive vias 223R, 223L corresponding to the through-holes 222R, 222L. For example, each through-hole 222R, 222L corresponds to one interlayer conductive via 223R, 223L. Each interlayer conductive via 223R, 223L passes through the dielectric material 21 from the top of the two wiring blocks 22R, 22L and is electrically connected to the second wiring layer 221b. In a preferred embodiment, each through-hole 222R, 222L and interlayer conductive via 223R, 223L exposed on the end face of the dielectric material 21 may also have an electrical connection pad 224 formed thereon for electrical connection with other lines or components (not shown). In some other variations, a support member 225 (e.g., a temporary carrier of silicon oxide or glass) may be further provided below the dielectric material 21. It should be noted that in Figure 1B In the top view schematic diagram of the capacitor module CM shown, the positions of the first wiring layer 221a and the second wiring layer 221b relative to the top surface of the capacitor module CM are marked with different dashed lines, and according to... Figure 1BAs shown, both the first wiring layer 221a and the second wiring layer 221b are circular, but the shapes of the first wiring layer 221a and the second wiring layer 221b when viewed from above are not limited to those shown in this embodiment.
[0043] Generally, the circuit structure 20a will also contain at least one circuit block 23. The circuit block 23 includes at least one circuit layer 231, which is also covered by the dielectric material 21 and can be used to transmit electrical signals. This embodiment does not have any limitations in this regard.
[0044] Preferably, the two through-holes 222R, 222L in the two wiring blocks 22R, 22L are symmetrically arranged in the capacitor module CM, and the interlayer conductive via 223R in one wiring block 22R and the interlayer conductive via 223L in the other wiring block 22L are symmetrically arranged in the capacitor module CM. Figure 1A and Figure 1B Taking the example shown, the two through-holes 222R and 222L in the two wiring blocks 22R and 22L are arranged adjacent to each other in the capacitor module CM, while the interlayer conductive via 223R in wiring block 22R and the interlayer conductive via 223L in the other wiring block 22L are arranged far apart from each other in the capacitor module CM. With this arrangement, wiring block 22R, which includes the through-hole 222R and the interlayer conductive via 223R on the right, and wiring block 22L, which includes the through-hole 222L and the interlayer conductive via 223L on the left, can form a capacitor module CM. When the through-holes 222R, 222L or the interlayer through-holes 223R, 223L in these two wiring blocks 22R, 22L are electrically connected to other lines or components (not shown), the charge can accumulate or be released in the dielectric material 21 between the two wiring blocks 22R, 22L, thus functioning as a capacitor. The capacitance and voltage withstand characteristics of this capacitor module CM can be determined by selecting the material of the dielectric material 21 or designing the distance between the two wiring blocks 22R, 22L to meet the requirements.
[0045] Or such as Figure 2A and Figure 2BAs shown, in another variation of the embodiment, the two through-holes 222R, 222L in the two wiring blocks 22R, 22L are disposed far apart from each other in the capacitor module CM, while the two interlayer conductive vias 223R, 223L in the two wiring blocks 22R, 22L are disposed adjacent to each other in the capacitor module CM. This also forms a symmetrical capacitor module CM, which functions as a capacitor in the connected lines (not shown). Since the only difference between this embodiment and the previous embodiment is the placement and symmetry of the through-holes 222R, 222L and the interlayer conductive vias 223R, 223L, the other mechanisms of operation are the same, details will not be repeated here.
[0046] like Figure 3 As shown, the circuit structure 20a provided in this embodiment is applied in an electronic package 1. The electronic package 1 has a carrier 10 and two package modules 20 disposed on the carrier 10. The carrier 10 is, for example, a circuit board, and each package module 20 can be, for example, a fan-out multi-chip module (FOMCM), but this embodiment does not have any particular limitation on this. Each package module 20 has a circuit structure 20a as described above. One or more electronic components 24 are connected above each circuit structure 20a. Figure 3 The example shown uses three electronic components 24 connected above the circuit structure 20a in each package module 20. The electronic components 24 are, for example, various active or passive components such as High Bandwidth Memory (HBM), System-On-Chip (SoC), or Integrated Passive Device (IPD), depending on the requirements or design; this embodiment does not impose any limitations on this. In this embodiment, the capacitor module CM in each circuit structure 20a is used to replace the existing capacitor components. Since there is no need to additionally set or form capacitors, the area and volume of the electronic package 1 are significantly reduced. At the same time, since the electronic package 1 shown in this embodiment does not have existing capacitor components, the noise within the electronic package 1 can be significantly reduced, effectively improving power and signal quality.
[0047] In summary, this application significantly reduces the area and volume of the electronic package 1 by replacing existing capacitor components with a capacitor module CM formed by symmetrical wiring blocks 22R and 22L. Furthermore, since the existing capacitor components in the package are eliminated, noise generated by discrete capacitors can be effectively reduced, thereby greatly improving the power supply and signal quality within the electronic package 1.
[0048] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. A circuit structure, characterized in that, include: Dielectric materials; Two wiring blocks, encapsulated in the dielectric material and each comprising a first wiring layer and a second wiring layer located above the first wiring layer; and The circuit block is encapsulated in the dielectric material and includes a circuit layer; The two wiring blocks are spaced apart, adjacent to each other, and symmetrically arranged to form a capacitor module.
2. The circuit structure as described in claim 1, characterized in that, Each wiring block contains a through conductive via, and each through conductive via passes through the dielectric material from the top of the wiring block and is electrically connected to the first wiring layer and the second wiring layer.
3. The circuit structure as described in claim 2, characterized in that, Each wiring block contains an interlayer conductive via corresponding to the through conductive via, and each interlayer conductive via is electrically connected to the second wiring layer after passing through the dielectric material from the top of the wiring block.
4. The circuit structure as described in claim 2, characterized in that, The two through-holes in the two wiring blocks are symmetrically arranged in the capacitor module.
5. The circuit structure as described in claim 3, characterized in that, The interlayer conductive via in one of the two wiring blocks is symmetrically disposed in the capacitor module with the interlayer conductive via in the other wiring block.
6. The circuit structure as described in claim 4, characterized in that, The two through-holes in the two wiring blocks are arranged adjacent to each other in the capacitor module.
7. The circuit structure as described in claim 4, characterized in that, The two through-holes in the two wiring blocks are disposed far apart in the capacitor module.
8. The circuit structure as described in claim 5, characterized in that, The interlayer conductive via of one of the two wiring blocks and the interlayer conductive via of the other wiring block are disposed adjacent to each other in the capacitor module.
9. The circuit structure as described in claim 5, characterized in that, The interlayer conductive via of one of the two wiring blocks and the interlayer conductive via of the other wiring block are disposed far apart in the capacitor module.
10. The circuit structure as described in claim 3, characterized in that, Each of the through-holes and interlayer conductive vias exposed on the end face of the dielectric material has an electrical connection pad formed thereon.