Electronic package
By placing electronic components and intermediary components on both sides of the circuit structure of the electronic package and forming a passivation layer on them, the high cost and complex process problems caused by conductive bumps and carrier plates in the prior art are solved, achieving cost reduction, process simplification and yield improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SILICONWARE PRECISION IND CO LTD
- Filing Date
- 2025-05-08
- Publication Date
- 2026-06-19
AI Technical Summary
Existing fan-out packaging structures involve forming conductive bumps on the back of the semiconductor chip and connecting them to a carrier plate, which results in high manufacturing costs, cumbersome processes, and consequently, low yield and low productivity.
By employing the manufacturing method of electronic packaging components, electronic components and intermediate components are placed on both sides of the circuit structure, and a passivation layer is formed on them. The design of exposed conductive vias avoids the use of conductive bumps and carrier plates, simplifying the process and reducing costs.
It reduces manufacturing costs, simplifies processes, improves productivity and yield, while ensuring the proper electrical function of electronic components and increasing design flexibility.
Smart Images
Figure CN224386137U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor packaging technology, and more particularly to an electronic package that can improve reliability. Background Technology
[0002] High-performance computing (HPC) technology is becoming increasingly important and widespread in modern life, for example in medical technology development such as cancer drug development, or in the automatic sensing and detection computing of autonomous vehicles. Devices used in these fields often employ fan-out package (FO PKG) structures. To address this, the industry has developed numerous advanced process packaging technologies, such as Fan-Out Multi-Chip Module (FOMCM) and Fan-Out Embedded Bridge Die (FOEB), to meet design requirements such as multi-chip functionality, high line count, large fan-out size, and high heat dissipation.
[0003] Figures 1A to 1D This is a cross-sectional schematic diagram of the existing fan-out embedded bridging structure manufacturing method.
[0004] like Figure 1A As shown, a semiconductor chip 10 is provided, which has a first side 10a and a second side 10b opposite to each other. A plurality of first conductive bumps 11 are formed on the first side 10a, and a plurality of conductive vias 100 are formed in the semiconductor chip 10, and the plurality of conductive vias 100 are electrically connected to the plurality of first conductive bumps 11. The first conductive bumps 11 are, for example, metal pillars of copper.
[0005] like Figure 1B As shown, the second side 10b is thinned (e.g., through a polishing process) to expose the plurality of conductive vias 100. Next, conductive lines 13 are formed on the second side 10b of the semiconductor chip 10, and a plurality of second conductive bumps 12 are formed on the conductive lines 13. The conductive lines 13 are electrically connected to the plurality of conductive vias 100, allowing the plurality of second conductive bumps 12 to be electrically connected to the plurality of first conductive bumps 11 through the conductive lines 13 and the plurality of conductive vias 100. The second conductive bumps 12, for example, include copper pillars and solder.
[0006] like Figure 1C As shown, a carrier 140 is provided, on which a circuit layer 141 and a plurality of conductive pillars 142 are disposed, and the semiconductor chip 10 is attached to the circuit layer 141 by a plurality of second conductive bumps 12. The carrier 140 is, for example, a plate made of semiconductor material (such as silicon or glass).
[0007] like Figure 1D As shown, a covering layer 15 is formed to cover the semiconductor chip 10 and the conductive pillars 142. Then, a circuit structure 16 is formed on the covering layer 15. Next, a plurality of electronic components 17 are disposed on the circuit structure 16. Then, the electronic components 17 are covered by an encapsulation layer 18. After that, the carrier 140 is removed, and a plurality of conductive components 19 are formed on the circuit layer 141.
[0008] However, the aforementioned manufacturing method requires forming a second conductive bump (u-bump) on the back of the semiconductor chip with conductive silicon through-holes, which is not only costly to manufacture, but also requires flip-chip bonding to the circuit layer on the surface of the carrier board, which is another cost expense. In addition, the above process is complicated, resulting in problems such as decreased yield, low productivity and high cost.
[0009] Therefore, overcoming the problems of the existing technology has become an urgent issue that needs to be addressed. Utility Model Content
[0010] In view of the various deficiencies of the prior art, this application provides an electronic package, comprising: a circuit structure having opposing first and second sides; an electronic component disposed on the first side of the circuit structure; an intermediary element disposed on the first side of the circuit structure and having a plurality of conductive vias; a first passivation layer formed on the electronic component; a second passivation layer formed on the intermediary element, wherein the top surfaces of the plurality of conductive vias are exposed on the second passivation layer; an overlay layer having opposing first and second surfaces and the second surface formed on the first side of the circuit structure to overlay the electronic component, the intermediary element, the first passivation layer and the second passivation layer, wherein the top surfaces of the first passivation layer, the second passivation layer and the plurality of conductive vias are exposed on the first surface; and a plurality of functional elements disposed on the second side of the circuit structure to electrically bridge the plurality of functional elements through the electronic component and / or the intermediary element.
[0011] This application also provides a method for manufacturing an electronic package, comprising: providing an electronic module, which includes: a circuit structure having a first side and a second side opposite to each other; an electronic component disposed on the first side of the circuit structure; an intermediate element disposed on the first side of the circuit structure and having a plurality of conductive vias; a cover layer having a first surface and a second surface opposite to each other and formed on the first side of the circuit structure with the second surface to cover the electronic component and the intermediate element; and a plurality of functional elements disposed on the second side of the circuit structure to electrically bridge the plurality of functional elements through the electronic component and / or the intermediate element; performing a thinning process on the electronic component and the intermediate element, such that the electronic component and the intermediate element are relatively recessed in the first surface of the cover layer, thereby forming a first recess and a second recess respectively, and causing the plurality of conductive vias to protrude from the second recess; and forming a first passivation layer and a second passivation layer in the first recess and the second recess respectively, and exposing the top surfaces of the first passivation layer, the second passivation layer and the plurality of conductive vias on the first surface.
[0012] In the aforementioned electronic package and its manufacturing method, a portion of the material of the electronic component and the intermediate component is removed by wet etching to form the first recess and the second recess, respectively.
[0013] In the aforementioned electronic package and its manufacturing method, a first passivation layer and a second passivation layer are formed by filling the first recess and the second recess with liquid adhesive to cover the electronic component and the intermediary component.
[0014] The aforementioned electronic package and its manufacturing method also include a leveling process to remove part of the first passivation layer, part of the second passivation layer and part of the cover layer, so that the top surfaces of the first passivation layer, the second passivation layer and the plurality of conductive through holes are flush with the first surface of the cover layer.
[0015] In the aforementioned electronic package and its manufacturing method, the electronic module further includes a plurality of conductive pillars formed on the first side of the circuit structure and covered by the covering layer, with the top surfaces of the plurality of conductive pillars exposed on the first surface.
[0016] In the aforementioned electronic package and its manufacturing method, the electronic module further includes a packaging layer formed on the second side of the circuit structure to cover the plurality of functional components.
[0017] In the aforementioned electronic package and its manufacturing method, a plurality of conductive elements are disposed on the first surface of the covering layer and on the first passivation layer and the second passivation layer, and the plurality of conductive elements are electrically connected to the plurality of conductive vias.
[0018] In the aforementioned electronic package and its manufacturing method, a wiring layer is formed on the first surface of the covering layer, the first passivation layer, and the second passivation layer, and a plurality of conductive elements are disposed on the wiring layer.
[0019] In the aforementioned electronic package and its manufacturing method, the electronic component has opposing active and non-active surfaces, and the active surface faces the first side to be electrically connected to the circuit structure.
[0020] In the aforementioned electronic package and its manufacturing method, the intermediate element is electrically connected to the circuit structure through the plurality of conductive through-holes.
[0021] In the aforementioned electronic package and its manufacturing method, the functional element is electrically connected to the circuit structure through multiple conductive bumps.
[0022] As can be seen from the above, the electronic package of this application mainly has electronic components / intermediate components and multiple functional components on both sides of the circuit structure. Not only can the electronic components / intermediate components be used as bridging elements to electrically connect the multiple functional components, but a first passivation layer / second passivation layer is also formed on the electronic components / intermediate components, and multiple conductive vias of the intermediate components are exposed to the second passivation layer, so that multiple conductive components can be disposed on the covering layer and the first passivation layer / second passivation layer, and electrically connected to the multiple conductive vias. This avoids the problem of forming conductive bumps on the conductive vias and preparing glass carriers in the existing manufacturing process, thus reducing manufacturing costs, simplifying the process, and improving productivity and yield. Attached Figure Description
[0023] Figures 1A to 1D This is a cross-sectional schematic diagram of the existing fan-out embedded bridging structure manufacturing method.
[0024] Figures 2A to 2D This is a cross-sectional schematic diagram of the electronic package and its manufacturing method according to this application.
[0025] Figure 3 This is a cross-sectional schematic diagram of another embodiment of the electronic package and its manufacturing method of this application.
[0026] Explanation of reference numerals in the attached figures
[0027] 10 Semiconductor chips
[0028] 10a First side
[0029] 10b Second side
[0030] 100 Conductive Through-hole
[0031] 11 First conductive bump
[0032] 12 Second conductive bump
[0033] 13 Conductive circuits
[0034] 140 load-bearing components
[0035] 141 Line Layer
[0036] 142 conductive pillars
[0037] 15 Coating Layers
[0038] 16. Circuit Structure
[0039] 17 Electronic components
[0040] 18 Encapsulation Layer
[0041] 19. Conductive elements
[0042] 2,3 Electronic packages
[0043] 2a Electronic Module
[0044] 20. Circuit Structure
[0045] 20a First side
[0046] 20b Second side
[0047] 200 dielectric layers
[0048] 201 Line Layer
[0049] 21 Electronic Components
[0050] 21a Working surface
[0051] 21b Non-operating surface
[0052] 210 Electrode Pad
[0053] 211, 221 Protective film
[0054] 212,222 Conductors
[0055] 22 Intermediate Components
[0056] 220 conductive via
[0057] 223 contacts
[0058] 23 Conductive pillars
[0059] 24 Protective Layers
[0060] 241 Conductive components
[0061] 25 coating layers
[0062] 25a First Surface
[0063] 25b Second Surface
[0064] 251 First recess
[0065] 252 Second recess
[0066] 26 Functional Components
[0067] 260 conductive bumps
[0068] 261 base rubber
[0069] 27 Encapsulation layer
[0070] 281 First passivation layer
[0071] 282 Second passivation layer
[0072] 29 Conductive elements
[0073] 34. Wiring layer. Detailed Implementation
[0074] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0075] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0076] Please see Figures 2A to 2D This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package of this application.
[0077] like Figure 2A As shown, an electronic module 2a is provided, which includes: a covering layer 25, at least one electronic component 21, at least one intermediate component 22, a plurality of conductive pillars 23, a circuit structure 20, and a plurality of functional components 26.
[0078] The coating layer 25 has opposing first surfaces 25a and second surfaces 25b. In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, or an encapsulating compound such as epoxy resin. For example, the coating layer 25 can be formed by methods such as liquid compounding, injection, lamination, or compression molding.
[0079] The electronic component 21 is embedded in the covering layer 25. The electronic component 21 is an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor chip, while the passive component is, for example, a resistor, capacitor, or inductor. In this embodiment, the electronic component 21 is a semiconductor chip with opposing active surfaces 21a and non-active surfaces 21b. The active surface 21a faces the second surface 25b and has multiple electrode pads 210 for bonding and electrically connecting multiple conductors 212, and the conductors 212 are covered by a protective film 211. The conductors 212 may be conductive lines, spherical solder balls, columnar metal materials such as copper pillars or solder bumps, or stud conductive parts made by a wire bonding machine.
[0080] The intermediate element 22 is a semiconductor material such as silicon substrate and is embedded in the cladding layer 25. It has multiple conductive vias 220, such as through-silicon vias (TSVs). In this embodiment, the conductive via 220 has a contact 223 on one end face of the intermediate element 22 to connect and electrically link multiple conductors 222, and the conductors 222 are covered by a protective film 221. The conductors 222 can be conductive lines, spherical solder balls, columnar metal materials such as copper pillars or solder bumps, or stud conductive parts made by wire bonding machines. It should be understood that the conductive vias 220 can take many forms, for example, they can be covered with insulating material, and there are no particular limitations.
[0081] The plurality of conductive pillars 23 are embedded in the covering layer 25, and the material forming the plurality of conductive pillars 23 is a metal such as copper or solder. In this embodiment, one end face of the plurality of conductive pillars 23 is exposed on the first surface 25a of the covering layer 25.
[0082] The circuit structure 20 has opposing first sides 20a and second sides 20b, with the first side 20a disposed on the second surface 25b of the covering layer 25 and electrically connecting the conductive post 23 to the electronic component 21 and the intermediate element 22. In this embodiment, the circuit structure 20 includes multiple dielectric layers 200 and multiple circuit layers 201, such as a redistribution layer (RDL) specification, or the circuit structure 20 may also include only a single dielectric layer 200 and a single circuit layer 201. Furthermore, the material forming the circuit layer 201 is copper, and the material forming the dielectric layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc.
[0083] The plurality of functional elements 26 are disposed on the second side 20b of the circuit structure 20 and electrically connected to the circuit layer 201, such that the cladding layer 25, conductive pillars 23, electronic components 21 and the intermediary element 22 are disposed on one side of the circuit structure 20, while the functional elements 26 are disposed on the other side. The functional elements 26 are active elements, passive elements, or a combination of both. The active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, capacitor, and inductor. In this embodiment, the functional element 26 is, for example, a semiconductor chip such as a graphics processing unit (GPU) or high bandwidth memory (HBM), which is electrically connected to the circuit layer 201 via multiple conductive bumps 260 in a flip-chip manner, and then the conductive bumps 260 are covered with an adhesive base 261.
[0084] The electronic component 21 and / or the intermediate component 22 can serve as a bridge die, so that the electronic component 21 and / or the intermediate component 22 are electrically connected to the circuit layer 201 of the circuit structure 20 via the conductors 212, 222, so as to electrically bridge the plurality of functional components 26.
[0085] Additionally, an encapsulation layer 27 can be formed on the outermost side of the circuit structure 20 to cover the plurality of functional components 26 and the primer 261. If the encapsulation layer 27 covers the conductive bumps 260, then the primer 261 is not required. For example, the encapsulation layer 27 is an insulating material, such as polyimide (PI), dry film, epoxy resin, epoxy resin encapsulant, or molding compound, which can be formed by lamination or molding. It should be understood that the material of the covering layer 25 and the encapsulation layer 27 can be the same as or different from the material of the encapsulation layer 27. Furthermore, the encapsulation layer 27 can cover the top surface of the functional component 26, or, as required, the outer surface of the encapsulation layer 27 can be flush with the top surface of the functional component 26, so that the top surface of the functional component 26 is exposed by the encapsulation layer 27.
[0086] Next, a thinning process is performed on the electronic component 21 and the intermediate element 22, for example, by wet etching to remove part of the material of the electronic component 21 (non-functional surface 21b) and the intermediate element 22, so that the conductive vias 220 are exposed on the intermediate element 22, and the electronic component, the intermediate element 22 and their conductive vias 220 are exposed on the first surface 25a of the cladding layer 25. That is, the electronic component 21 and the intermediate element 22 are relatively recessed in the first surface 25a of the cladding layer 25, forming a first recess 251 and a second recess 252 respectively, and the plurality of conductive vias 220 protruding from the second recess 252. In addition, the depth of the first recess 251 may be the same as or different from the depth of the second recess 252, that is, the degree of thinning of the electronic component 21 and the intermediate element 22 may be the same or different, so as to obtain electronic components 21 and intermediate elements 22 of the same or different thicknesses after the thinning process.
[0087] like Figure 2B As shown, a first passivation layer 281 and a second passivation layer 282 are formed on the electronic component 21 and the intermediate element 22, respectively. For example, the first passivation layer 281 and the second passivation layer 282 are formed by filling the first recess 251 and the second recess 252 with liquid adhesive (such as primer or non-conductive adhesive) to cover the electronic component 21, the intermediate element 22 and its conductive through-hole 220.
[0088] like Figure 2CAs shown, a leveling process is performed to remove a portion of the first passivation layer 281 on the electronic component 21, a portion of the second passivation layer 282 on the intermediate element 22, a portion of the material of the first surface 25a of the covering layer 25, and a portion of the material of the conductive pillar 23, so that the outer surface of the second passivation layer 282 on the intermediate element 22, the end face of the conductive via 220, the outer surface of the first passivation layer 281 on the electronic component 21, the first surface 25a of the covering layer 25, and the end face of the conductive pillar 23 are flush. For example, this leveling process uses a grinding method.
[0089] like Figure 2D As shown, a plurality of conductive elements 29 are formed on the first surface 25a of the covering layer 25, the first passivation layer 281 and the second passivation layer 282, and the plurality of conductive elements 29 are electrically connected to the plurality of conductive pillars 23 and the plurality of conductive through holes 220 to obtain the electronic package 2.
[0090] In this embodiment, the conductive element 29 is a solder ball or a metal bump such as a copper bump. For example, the conductive element 29 is a C4 type solder ball, allowing the electronic package 2 to be attached to an electronic device (not shown) such as a circuit board through these conductive elements 29. Furthermore, a protective layer 24 can be formed on the first surface 25a of the covering layer 25, and a plurality of conductive elements 241 can be formed in the protective layer 24 to connect the plurality of conductive elements 29. The plurality of conductive elements 241 are erected on the first passivation layer 281 and the second passivation layer 282, the plurality of conductive pillars 23, and the plurality of conductive vias 220, electrically connecting the plurality of conductive pillars 23 and the plurality of conductive vias 220. The conductive element 241 is, for example, a conductive blind via or a conductive block, and its material is metallic copper.
[0091] Since this application provides electronic components 21 / intermediate components 22 and multiple functional components 26 on both sides of the circuit structure 20, the electronic components 21 / intermediate components 22 can be used as bridging elements to electrically connect the multiple functional components 26. Simultaneously, a first passivation layer 281 / second passivation layer 282 is formed on the electronic components 21 / intermediate components 22, and multiple conductive vias 220 of the intermediate components 22 are exposed to the second passivation layer 282, allowing multiple conductive components 29 to be disposed on the covering layer 25 and the first passivation layer 281 / second passivation layer 282, and electrically connected to the multiple conductive vias 220. This avoids the problems of forming conductive bumps and preparing glass carriers on conductive vias in existing manufacturing methods, thus reducing manufacturing costs, simplifying the process, and improving productivity and yield. Furthermore, this application can utilize the first passivation layer 281 of the non-functional surface 21b of the electronic component 21 to prevent electrical short circuits caused by the placement of conductive components 29, ensuring the normal electrical function of the electronic component 21.
[0092] Please see Figure 3In another embodiment of the electronic package 3, a wiring layer 34 may be formed on the first surface 25a of the covering layer 25, the first passivation layer 281 and the second passivation layer 282, so that the wiring layer 34 electrically connects the plurality of conductive pillars 23 and the plurality of conductive vias 220 of the intermediate element 22. Then, a plurality of conductive elements 241 are formed on the wiring layer 34 for placing a plurality of conductive elements 29, so that the plurality of conductive elements 29 are electrically connected to the plurality of conductive pillars 23 and the plurality of conductive vias 220.
[0093] This application also provides an electronic package 2,3, comprising: a circuit structure 20 having opposing first sides 20a and second sides 20b; an electronic component 21 disposed on the first side 20a of the circuit structure 20; an intermediate element 22 disposed on the first side 20a of the circuit structure 20 and having a plurality of conductive vias 220; a first passivation layer 281 formed on the electronic component 21; a second passivation layer 282 formed on the intermediate element 22, wherein the top surfaces of the plurality of conductive vias 220 are exposed to the second passivation layer 282; and an overlay layer 25 having a relative... A first surface 25a and a second surface 25b are formed on the first side 20a of the circuit structure 20, with the second surface 25b forming the second surface 25b, to cover the electronic component 21, the intermediate element 22, the first passivation layer 281 and the second passivation layer 282, and to expose the top surfaces of the first passivation layer 281, the second passivation layer and the plurality of conductive vias 220 on the first surface 25a; and a plurality of functional elements 26 are disposed on the second side 20b of the circuit structure 20 to electrically bridge the plurality of functional elements 26 through the electronic component 21 and / or the intermediate element 22.
[0094] In one embodiment, the electronic package 2,3 further includes: a plurality of conductive pillars 23 formed on the first side 20a of the circuit structure 20 and covered by the covering layer 25, with the top surfaces of the plurality of conductive pillars 23 exposed on the first surface 25a.
[0095] In one embodiment, the electronic package 2,3 further includes an encapsulation layer 27 formed on the second side 20b of the circuit structure 20 to cover the plurality of functional elements 26.
[0096] In one embodiment, the electronic package 2, 3 further includes a plurality of conductive elements 29 disposed on the first surface 25a of the cover layer 25 and the first passivation layer 281 and the second passivation layer 282, and the plurality of conductive elements 29 are electrically connected to the plurality of conductive vias 220. Further, the electronic package 3 includes a wiring layer 34 formed on the first surface 25a of the cover layer 25 and the first passivation layer 281 and the second passivation layer 282, for the plurality of conductive elements 29 to be disposed on the wiring layer 34.
[0097] In one embodiment, the electronic component 21 has an opposing active surface 21a and a non-active surface 21b, with the active surface 21a facing the first side 20a and electrically connected to the circuit structure 20. The intermediate component 22 is also electrically connected to the circuit structure 20 through the plurality of conductive vias 220.
[0098] In summary, the electronic package of this application mainly features electronic components / intermediate components and multiple functional components on both sides of the circuit structure. This allows the electronic components / intermediate components to act as bridging elements for electrical connection of these functional components. Furthermore, a first passivation layer / second passivation layer is formed on the electronic components / intermediate components, exposing multiple conductive vias of the intermediate components to the second passivation layer. This allows multiple conductive components to be disposed on the covering layer and the first / second passivation layer, and electrically connected to these conductive vias. This avoids the problems of forming conductive bumps and preparing glass carriers on conductive vias in existing manufacturing methods, thus reducing manufacturing costs, simplifying the process, and improving productivity and yield. Simultaneously, the first passivation layer on the non-functional surface of the electronic component prevents electrical short circuits caused by the placement of conductive components, ensuring the normal electrical function of the electronic component. Moreover, by forming the first / second passivation layer on the electronic components / intermediate components, this application can be used with electronic components / intermediate components of varying thicknesses, increasing the design flexibility of electronic products. Furthermore, this application can be manufactured using existing semiconductor packaging processes, without the need to develop special processes or purchase special equipment, thus solving existing technical problems in the industry.
[0099] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. An electronic package, characterized in that, include: The circuit structure has a first side and a second side that are opposite to each other; Electronic components are located on the first side of the circuit structure; An intermediate element is disposed on the first side of the circuit structure and has multiple conductive vias; A first passivation layer is formed on the electronic component; A second passivation layer is formed on the intermediate element, and the top surface of the plurality of conductive vias is exposed to the second passivation layer. The cladding layer has a first surface and a second surface opposite to each other and is formed on the first side of the circuit structure on the second surface to cover the electronic component, the intermediate component, the first passivation layer and the second passivation layer, and exposes the top surfaces of the first passivation layer, the second passivation layer and the plurality of conductive vias on the first surface. as well as Multiple functional elements are disposed on the second side of the circuit structure to electrically bridge the multiple functional elements through the electronic element and / or the intermediate element.
2. The electronic package as described in claim 1, characterized in that... The electronic package also includes a plurality of conductive pillars formed on a first side of the circuit structure and covered by the overlay layer, with the top surfaces of the plurality of conductive pillars exposed on the first surface.
3. The electronic package as described in claim 1, characterized in that... The electronic package also includes a packaging layer formed on a second side of the circuit structure to cover the plurality of functional components.
4. The electronic package as described in claim 1, characterized in that... The electronic package also includes a plurality of conductive elements disposed on the first surface of the cover layer and on the first passivation layer and the second passivation layer, and the plurality of conductive elements are electrically connected to the plurality of conductive vias.
5. The electronic package as described in claim 1, characterized in that... The electronic package also includes a first surface forming the cover layer and wiring layers on the first passivation layer and the second passivation layer, and a plurality of conductive elements are disposed on the wiring layer.
6. The electronic package as claimed in claim 1, characterized in that, The electronic component has opposing active and non-active surfaces, and the active surface faces the first side to be electrically connected to the circuit structure.
7. The electronic package as claimed in claim 1, characterized in that, The intermediary element is electrically connected to the circuit structure through the multiple conductive vias.
8. The electronic package as claimed in claim 1, characterized in that, This functional element is electrically connected to the circuit structure through multiple conductive bumps.
9. The electronic package as claimed in claim 1, characterized in that, The electronic component and the intermediate component are recessed relative to each other on the first surface of the covering layer, and respectively form a first recess and a second recess.
10. The electronic package as claimed in claim 9, characterized in that, The first passivation layer and the second passivation layer respectively fill the first recess and the second recess.