Dual-sided package structure
By using a double-sided packaging structure and combining transfer molding and black or white film with compression molding, the problems of poor filling and difficulty in reducing package size in single-sided BDMP packaging are solved, resulting in smaller package size and optimized layout design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- VANCHIP TIANJIN TECH
- Filing Date
- 2025-05-21
- Publication Date
- 2026-06-19
AI Technical Summary
In the existing technology, single-sided BDMP packaging has the risk of Sn short circuit due to poor bottom filling of FC die, and the package size is difficult to reduce. The FC die, SAW filter and resistor-capacitor components are attached to the same side, which increases the difficulty of arrangement.
A double-sided packaging structure is adopted. The non-filter chip is encapsulated on the front side of the substrate using transfer molding process, and the filter chip and other electronic components are encapsulated on the back side. By combining black film or white film with compression molding process, the layout design is optimized and the thickness of the first encapsulation body is reduced to less than 100μm.
It ensures the filling effect at the bottom of the non-filter chip, reduces the package size to below 650μm, optimizes the layout design, and increases the area of the stamp.
Smart Images
Figure CN224386138U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuit technology, and in particular to a double-sided packaging structure. Background Technology
[0002] Currently, bare die module package (BDMP) is mainly single-sided packaging. It mounts FC die (flip chip), surface acoustic wave (SAW) filter and resistive capacitor components onto the substrate surface, and forms a cavity by coating to achieve the SAW filter function. Then, the low molding characteristics of compression molding process prevent the cavity from collapsing, thus protecting the overall electrical performance of the module.
[0003] After coating, single-sided BDMP requires laser ablation around the FC die to cut through the coating, and then fill it with C-mold (compression molding process). However, in actual operation, even with laser ablation, poor filling still occurs due to the low molding characteristics of C-mold, resulting in voids at the bottom of the FC die and the risk of Sn short circuit. Moreover, the FC die, SAW filter and resistor / capacitor components are attached to the same side, increasing the difficulty of arrangement and making it difficult to reduce the package size. Utility Model Content
[0004] The purpose of this invention is to provide a double-sided packaging structure that optimizes the layout design and reduces the package size while ensuring the filling effect at the bottom of the non-filter chip.
[0005] To achieve the above and other related objectives, this utility model provides a double-sided packaging structure, characterized in that it includes: a substrate, a non-filter chip, a back-side electronic component, a first molding compound, and a second molding compound. The substrate has a front side and a back side. The first molding compound encapsulates the non-filter chip on the front side of the substrate. The first molding compound is formed by transfer molding. The second molding compound encapsulates the back-side electronic component on the back side of the substrate. The back-side electronic component includes a filter chip.
[0006] Optionally, in the double-sided encapsulation structure, the second encapsulation body is a combination of a black film or a white film and an encapsulation body formed by the compression molding process, wherein the white film covers the surface of the back electronic component, and the encapsulation body formed by the compression molding process covers the white film.
[0007] Optionally, in the double-sided packaging structure, the double-sided packaging structure further includes a stamp, which is disposed on the front side of the substrate and spaced apart from the non-filter chip.
[0008] Optionally, in the double-sided encapsulation structure, the thickness of the first molding compound is less than or equal to 150 μm.
[0009] Optionally, in the double-sided packaging structure, the double-sided packaging structure further includes conductive pillars and solder balls, the conductive pillars being located on the back side of the substrate and spaced apart from the back side electronic components, and the solder balls being located on the surface of the conductive pillars away from the substrate.
[0010] Optionally, in the double-sided packaging structure, the height of the conductive pillar is greater than the height of the back electronic component.
[0011] Optionally, in the double-sided packaging structure, the back-side electronic component further includes a resistive capacitor, and there is a cavity between the back-side electronic component and the substrate.
[0012] Optionally, in the double-sided packaging structure, the number of the back-side electronic components and the non-filter chip is at least one.
[0013] Optionally, in the double-sided packaging structure, there is a cavity between the non-filter chip and the substrate, and the first molding compound fills the cavity between the non-filter chip and the substrate.
[0014] Optionally, in the double-sided packaging structure, the non-filter chip is a flip chip.
[0015] Compared with the prior art, the technical solution of this utility model has the following beneficial effects:
[0016] The front side of the substrate of this utility model is only covered with non-filter chips, which can be encapsulated by transfer molding to ensure the filling effect at the bottom of the non-filter chips. At the same time, the thickness of the non-filter chips can be reduced to less than 100μm, and the theoretical size of the double-sided packaging structure can be reduced to less than 650μm. Since only non-filter chips are covered on the front side of the substrate, the layout design can be optimized and the area of the stamp can be increased. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the double-sided packaging structure provided by this utility model;
[0018] Figure 2 This is a schematic diagram of the product structure after step S11 in the preparation method of a double-sided packaging structure of this utility model;
[0019] Figure 3This is a schematic diagram of the product structure after step S121 in the preparation method of a double-sided packaging structure of this utility model;
[0020] Figure 4 This is a schematic diagram of the product structure after step S122 in the preparation method of a double-sided packaging structure of this utility model;
[0021] Figure 5 This is a schematic diagram of the product structure after step S13 in the preparation method of a double-sided packaging structure of this utility model;
[0022] Figure 6 This is a schematic diagram of the product structure after the step of forming the conductive pillar 50 in the preparation method of the double-sided encapsulation structure of this utility model;
[0023] Figure 7 This is a schematic diagram of the product structure after step S14 in the preparation method of a double-sided packaging structure of this utility model;
[0024] Figure 8 This is a schematic diagram of the product structure after step S15 in the preparation method of a double-sided packaging structure of this utility model;
[0025] Figure 9 This is a schematic diagram of the product structure after step S16 in the preparation method of a double-sided packaging structure of this utility model;
[0026] Figure 10 This is a schematic diagram of the product structure after step S18 in the preparation method of a double-sided packaging structure of this utility model;
[0027] Figure 11 This is a schematic diagram of the product structure after step S21 in another method for preparing a double-sided packaging structure of this utility model;
[0028] Figure 12 This is a schematic diagram of the product structure after the second molding compound 60 is subjected to a thinning process step in another method for preparing a double-sided encapsulation structure according to this utility model.
[0029] Figure 13 This is a schematic diagram of the product structure after step S26 in another method for preparing a double-sided packaging structure of this utility model;
[0030] Figure 14 This is a schematic diagram of the product structure after step S27 in another method for preparing a double-sided packaging structure of this utility model;
[0031] Figures 1 to 14 middle:
[0032] 10-Substrate, 10a-Front side, 10b-Back side, 20-Non-filter chip, 30-First molding compound, 401-Filter chip, 402-Capacitor component, 50-Conductive pillar, 60-Second molding compound, 70-Solder ball, 80-Stamp. Detailed Implementation
[0033] The double-sided packaging structure proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.
[0034] See Figure 1 The double-sided packaging structure provided by this utility model can be applied to bare chip module packaging (BDMP), specifically including: substrate 10, back electronic components, non-filter chip 20, first molding compound 30 and second molding compound 60. The first molding compound 30 molds the non-filter chip 20 on the front side 10a of the substrate 10, and the second molding compound 60 molds the back electronic components on the back side 10b of the substrate 10. The first molding compound 30 is a molding compound formed by transfer molding process.
[0035] In this embodiment, the substrate 10 may be a printed circuit board, but is not limited to this. The front side 10a and back side 10b of the substrate 10 may have multiple exposed pads. These pads may be used, but are not limited to, solder pads for mounting chips or carrying conductive pillars. The chips and conductive pillars can be electrically connected to the internal circuitry of the substrate 10 via the pads. The non-filter chip 20 may be a flip chip, mounted face down on the front side 10a of the substrate 10, with bumps on the front side of the flip chip soldered to the pads of the substrate 10. The number of non-filter chips 20 is at least one, preferably multiple. For example... Figure 1 The number of non-filter chips 20 is two. In this embodiment, there is a cavity between the non-filter chip 20 and the substrate 10, specifically, there is a cavity between the non-filter chip 20 and the front side 10a of the substrate 10.
[0036] The back-side electronic components may include a filter chip, more preferably a surface acoustic wave (SAW) filter chip, but are not limited thereto. In some embodiments, the back-side electronic components may also include passive devices, which may be resistive or capacitive devices, but are not limited thereto. In this embodiment, the number of back-side electronic components may be one or more, preferably more, and the multiple back-side electronic components are arranged at intervals. For example Figure 1The number of back-side electronic components is three, specifically including two filter chips 401 and one capacitor component 402. In this embodiment, there is a cavity between the back-side electronic components and the substrate 10, specifically, there is a cavity between the back-side electronic components and the back surface 10b of the substrate 10.
[0037] In this embodiment, the first molding compound 30 encapsulates the non-filter chip 20 on the front side 10a of the substrate 10. The first molding compound 30 at least covers the sidewalls of the non-filter chip 20. In this embodiment, the first molding compound 30 is a molding compound formed by a transfer molding process. Further, the material of the first molding compound 30 can be epoxy molding compound (EMC), but is not limited to this. This embodiment uses a molding compound formed by a transfer molding process as the first molding compound 30, which can protect the non-filter chip 20. Simultaneously, due to the high molding pressure of the transfer molding process, the first molding compound 30 can fill the cavity at the bottom of the non-filter chip 20 (i.e., the cavity between the non-filter chip 20 and the front side 10a of the substrate 10), avoiding the problem of poor filling at the bottom of the non-filter chip 20 caused by the low molding pressure of the compression molding process. The transfer molding process is an existing process and will not be described in detail here.
[0038] The second molding compound 60 encapsulates the back-side electronic component on the back side 10b of the substrate 10. The second molding compound 60 can be a combination of a black film or a white film and a molding compound formed by the compression molding process. The white film covers the surface of the back-side electronic component, and the molding compound formed by the compression molding process covers the white film. In this embodiment, the second molding compound 60 does not fill the cavity between the back-side electronic component and the substrate 10 to ensure the normal functioning of the back-side electronic component. In this embodiment, the black film and white film can be conventionally configured, and the material of the molding compound formed by the compression molding process can be epoxy molding compound (EMC), but is not limited to this. The compression molding process is an existing process and will not be described in detail here.
[0039] In this embodiment, the double-sided packaging structure may further include a stamp 80, which is disposed on the front side 10a of the substrate 10 and spaced apart from the non-filter chip 20. Since only the non-filter chip 20 is mounted on the front side 10a of the substrate 10 in this embodiment, the layout design can be optimized, and the design and area of the stamp 80 can be increased.
[0040] In this embodiment, the double-sided packaging structure may further include conductive pillars 50 and solder balls 70. The conductive pillars 50 are located on the back side 10b of the substrate 10 and are spaced apart from the back side electronic components. The solder balls 70 are located on the surface of the conductive pillars 50 away from the substrate 10.
[0041] See Figures 2 to 10 This utility model also provides a method for preparing the above-mentioned double-sided packaging structure, which may specifically include the following steps:
[0042] Step S11: Provide a substrate 10 and mount a non-filter chip 20 on the front side 10a of the substrate 10;
[0043] Step S12: The first molding compound 30 is formed using a transfer molding process, and the first molding compound 30 encapsulates the non-filter chip 20 on the front side 10a of the substrate 10.
[0044] Step S13: Mount back electronic components on the back side 10b of the substrate 10;
[0045] Step S14: Form a second molding compound 60, and the second molding compound 60 molds the back electronic components on the back side 10b of the substrate 10.
[0046] See Figure 2 In step S11, a substrate 10 is provided, and the non-filter chip 20 is mounted thereon. The substrate 10 may be a printed circuit board, but is not limited to this. The front side 10a and back side 10b of the substrate 10 may have multiple exposed pads. These pads may be used, but are not limited to, solder feet for mounting chips or conductive pillars. The chips and conductive pillars can be electrically connected to the internal circuitry of the substrate 10 via the pads. The non-filter chip 20 may be a flip chip, mounted face down on the front side 10a of the substrate 10, with bumps on the front side of the flip chip soldered to the pads of the substrate 10. The non-filter chip 20 may be mounted onto the front side 10a of the substrate 10 using surface mount technology (SMT) or flip chip assembly technology, but is not limited to these methods. A cavity is formed between the non-filter chip 20 and the front side 10a of the substrate 10.
[0047] See Figure 3 and Figure 4 Step S12 is executed to form the first molding compound 30. In this embodiment, a transfer molding process is used to form the first molding compound 30 to protect the non-filter chip 20. Simultaneously, the high molding pressure of the transfer molding process allows the first molding compound 30 to fill the cavity at the bottom of the non-filter chip 20 (i.e., the cavity between the non-filter chip 20 and the front surface 10a of the substrate 10), avoiding the problem of poor filling at the bottom of the non-filter chip 20 caused by the low molding pressure of the compression molding process. The material of the first molding compound 30 can be epoxy molding compound (EMC), but is not limited to this.
[0048] In this embodiment, the step of forming the first molding compound 30 may include:
[0049] Step S121: The first molding compound 30 completely covers the non-filter chip 20 using a transfer molding process;
[0050] Step S122: Perform a first thinning process on the first molding compound 30 until the distance between the surface of the first molding compound 30 away from the substrate 10 and the surface of the non-filter chip 20 away from the substrate 10 reaches a first target value.
[0051] See Figure 3 In step S121, the thickness of the first molding compound 30 formed is approximately 300 μm. The first molding compound 30 also fills the cavity between the non-filter chip 20 and the substrate 10.
[0052] See Figure 4 In step S122, the first thinning process can be a polishing process, but is not limited to this. The first target value is to protect the non-filter chip 20 from the risk of cracking or fragmentation in subsequent processes after it is exposed. In this embodiment, the first target value can be set according to process requirements. For example, the first thinning process is stopped when the distance between the surface of the first molding compound 30 away from the substrate 10 and the surface of the non-filter chip 20 away from the substrate 10 reaches 20 μm.
[0053] See Figure 5 Step S13 is executed, whereby a back-side electronic component is mounted on the back side 10b of the substrate 10. In this embodiment, the back-side electronic component may include a filter chip, but is not limited thereto. In some embodiments, the back-side electronic component may also include a passive device, which may be a resistive or capacitive device, but is not limited thereto. The back-side electronic component may be mounted on the back side 10b of the substrate 10 using surface mount technology (SMT), but is not limited thereto. A cavity is formed between the back-side electronic component and the back side 10b of the substrate 10. For example, Figure 5 Two filter chips 401 and a blocking device 402 are mounted on the back side 10b of the substrate 10, and each filter chip 401 and blocking device 402 forms a cavity with the back side 10b of the substrate 10.
[0054] See Figure 6After performing step S13 and before performing step S14, the method for fabricating the double-sided package structure in this example may further include forming conductive pillars 50. In this embodiment, the conductive pillars 50 are located on the back side 10b of the substrate 10 and are spaced apart from the back side electronic components. Preferably, there are multiple conductive pillars 50, and these multiple conductive pillars 50 can be respectively disposed on the pads of the substrate 10. The heights of the multiple conductive pillars 50 are preferably equal. The material of the conductive pillars 50 includes, but is not limited to, at least one of copper, titanium, and tin. In some embodiments, the conductive pillars 50 can be directly mounted on the substrate 10 using SMT (Surface Mount Technology). In some embodiments, the conductive pillars 50 can be directly formed on the back side 10b of the substrate 10 using 3D printing or electroplating.
[0055] In this embodiment, the height of the conductive post 50 is greater than the height of the back electronic component to ensure that when the second molding compound 60 is subsequently polished to expose the conductive post 50, the back electronic component is still protected by the second molding compound 60. The height of the conductive post 50 can be set conventionally, for example, 230 μm.
[0056] See Figure 7 Step S14 is executed to form a second molding compound 60, which encapsulates the back-side electronic component on the back side 10b of the substrate 10. In some embodiments, the second molding compound 60 can be a black film or a combination of a white film and a molding compound formed by the compression molding process. The white film covers the surface of the back-side electronic component, and the molding compound formed by the compression molding process covers the white film. That is, in this embodiment, the second molding compound 60 can be formed using a one-time black film molding process or using a white film process and a compression molding process. The black film is generally relatively thick, and the one-time black film molding process involves directly attaching the black film to the back side 10b of the substrate 10, whereby the black film directly wraps around the back-side electronic component and the conductive pillar 50. The white film is generally relatively thin, and the white film process and compression molding process involve first attaching a relatively thin white film to the surface of the back-side electronic component and the conductive pillar 50, and then using a compression molding process to directly form a molding compound covering the white film. In this embodiment, the black and white films can be set conventionally, and the compression molding process is a conventional process. The material of the molded body formed by the compression molding process is preferably EMC, but not limited to this. The second molded body 60 can be made using the compression molding process, but cannot be made using the transfer molding process, to prevent the cavity between the back electronic component and the back surface 10b of the substrate 10 from collapsing.
[0057] See Figure 8Following step S14, the fabrication method may further include step S15: performing a thinning process on the second molding compound 60 until the conductive pillar 50 is exposed on the surface away from the substrate 10. This thinning process is preferably a polishing process, but is not limited to it. The thinning process must not reduce the thickness of the back-side electronic components, especially the filter chip, to avoid affecting the performance of the filter chip.
[0058] See Figure 9 Following step S15, the fabrication method may further include step S16: performing a second thinning process on the first molding compound 30 until the thickness of the first molding compound 30 reaches a second target value. In this embodiment, the second thinning process is preferably a polishing process, and the second target value can be set according to process requirements, preferably less than or equal to 150 μm, or even less than 100 μm. In some embodiments, the second thinning process may only remove a portion of the thickness of the first molding compound 30, exposing the surface of the non-filter chip 20 away from the substrate 10. In some embodiments, the second thinning process may remove a portion of the thickness of the non-filter chip 20 while removing a portion of the thickness of the first molding compound 30. Since only the non-filter chip 20 is mounted on the front side 10a of the substrate 10, and the non-filter chip 20 is a flip chip, removing a portion of the thickness of the non-filter chip 20 will not affect the performance of the device.
[0059] See Figure 10 Following step S16, the preparation method may further include step S17: printing a stamp 80 in a blank area of the first encapsulation body 30. The printing method for the stamp 80 is a conventional method and will not be described in detail here. The blank area of the first encapsulation body 30 is the area in the first encapsulation body 30 where no non-filter chip 20 is disposed. The number of stamps 80 is at least one.
[0060] Continue reading Figure 10 Following step S17, the preparation method may further include step S18: forming solder balls 70. In this embodiment, the solder balls 70 are formed on the surface of the conductive pillars 50 away from the substrate 10 by solder printing and reflow. The material of the solder balls 70 is preferably tin, but is not limited thereto.
[0061] See Figures 11 to 14 This utility model also provides another method for preparing the above-mentioned double-sided packaging structure, which may specifically include the following steps:
[0062] Step S21: Provide a substrate 10, and provide conductive pillars 50 on the back side 10b of the substrate 10;
[0063] Step S22: Mount back electronic components on the back side 10b of the substrate 10;
[0064] Step S23: Form a second molding compound 60, and the second molding compound 60 molds the back electronic components onto the back side 10b of the substrate 10;
[0065] Step S24: Attach a non-filter chip 20 to the front side 10a of the substrate 10;
[0066] Step S25: The first molding compound 30 is formed using a transfer molding process, and the first molding compound 30 encapsulates the non-filter chip 20 on the front side 10a of the substrate 10.
[0067] See Figure 11 Step S21 is executed, providing a substrate 10. The substrate 10 may be a printed circuit board, but is not limited to this. The front side 10a and back side 10b of the substrate 10 may have multiple exposed pads. These pads may be used, but are not limited to, solder feet for mounting chips or to support conductive pillars. Chips and conductive pillars can be electrically connected to the internal circuitry of the substrate 10 via the pads. The conductive pillars 50 can be directly formed on the substrate 10 by electroplating and are disposed on the pads of the substrate 10. The material of the conductive pillars 50 includes, but is not limited to, at least one of copper, titanium, and tin. The height of the conductive pillars 50 can be set conventionally.
[0068] See Figure 12 Step S22 is executed, whereby a back-side electronic component is mounted on the back side 10b of the substrate 10. The back-side electronic component and its arrangement are described in step S13 and will not be repeated here. In this embodiment, the height of the conductive post 50 is greater than the height of the back-side electronic component to ensure that when the second molding compound 60 is subsequently polished to expose the conductive post 50, the back-side electronic component is still protected by the second molding compound 60.
[0069] Continue reading Figure 12 Step S23 is executed: a second molding compound 60 is formed, and the second molding compound 60 encapsulates the back-side electronic component on the back side 10b of the substrate 10. The second molding compound 60 is a combination of a black film or a white film and a molding compound formed by the compression molding process. The white film covers the surface of the back-side electronic component, and the molding compound formed by the compression molding process covers the white film. The second molding compound 60 and its formation are described in step S14, and will not be repeated here.
[0070] Continue reading Figure 12After step S23, the preparation method may further include: performing a thinning process on the second molding compound 60 until the surface of the conductive pillar 50 away from the substrate 10 is exposed. The thinning process in this step is preferably a polishing process, but is not limited thereto.
[0071] See Figure 13 Then, step S24 is executed, whereby a non-filter chip 20 is mounted on surface 10a of the substrate 10. In this embodiment, the non-filter chip 20 and its mounting method are described in step S11, and will not be repeated here.
[0072] Continue reading Figure 13 Step S25 is executed to form the first molding compound 30. In this embodiment, a transfer molding process is used to form the first molding compound 30 to protect the non-filter chip 20. Simultaneously, the high molding pressure of the transfer molding process allows the first molding compound 30 to fill the cavity at the bottom of the non-filter chip 20 (i.e., the cavity between the non-filter chip 20 and the front surface 10a of the substrate 10), avoiding the problem of poor filling at the bottom of the non-filter chip 20 caused by the low molding pressure of the compression molding process. The material of the first molding compound 30 can be epoxy molding compound (EMC), but is not limited to this.
[0073] In this embodiment, the step of forming the first molding compound 30 may include:
[0074] Step S251: The first molding compound 30 completely covers the non-filter chip 20 using a transfer molding process;
[0075] Step S252: Perform a thinning process on the first molding compound 30 until the thickness of the first molding compound 30 reaches the second target value.
[0076] In step S251, the thickness of the first molding compound 30 formed is approximately 300 μm.
[0077] In step S252, the thinning process can be a polishing process, but is not limited to it. The second target value can be set according to process requirements, preferably less than or equal to 150 μm, or even less than 100 μm. In some embodiments, the thinning process in this step can remove only a portion of the thickness of the first molding compound 30, exposing the surface of the non-filter chip 20 away from the substrate 10. In some embodiments, the thinning process in this step can remove a portion of the thickness of the first molding compound 30 while also removing a portion of the thickness of the non-filter chip 20. Since only the non-filter chip 20 is mounted on the front side of the substrate 10, and the non-filter chip 20 is a flip chip, removing a portion of the thickness of the non-filter chip 20 will not affect the performance of the device. In this embodiment, the first molding compound 30 can reach the second target value with a single thinning process, thus the process is simpler.
[0078] Continue reading Figure 13 Following step S25, the preparation method may further include step S26: printing a stamp 80 in a blank area of the first encapsulation body 30. The printing method for the stamp 80 is a conventional method and will not be described in detail here. The blank area of the first encapsulation body 30 is the area in the first encapsulation body 30 where no non-filter chip 20 is disposed. The number of stamps 80 is at least one.
[0079] See Figure 14 Following step S26, the preparation method may further include step S27: forming solder balls 70. In this embodiment, the solder balls 70 are formed on the surface of the conductive pillars 50 away from the substrate 10 by solder printing and reflow. The material of the solder balls 70 is preferably tin, but is not limited thereto.
[0080] In summary, in the double-sided packaging structure of this utility model, only non-filter chips are mounted on the front side of the substrate. A transfer molding process can be used to increase molding and ensure the bottom filling effect of the non-filter chips. According to the requirements of the total thickness of the double-sided packaging structure, a thinning process can be added to the first molding body on the front side of the substrate, so that the first molding body is thinned to less than or equal to 150μm, or even less than 100μm. Moreover, the thickness of the non-filter chips can be reduced from the existing 200μm to less than 100μm, and the thickness of the double-sided packaging structure can be reduced from the existing 750μm to less than 650μm. Compared with single-sided DBMP, the thickness not only does not increase, but can be reduced. At the same time, since only non-filter chips are mounted on the front side of the substrate 10, the layout design can be optimized, and the design and area of the stamp can be increased.
[0081] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention's technical solutions using the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention's technical solutions. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention's technical solutions, shall still fall within the protection scope of the present invention's technical solutions.
[0082] Furthermore, it should be understood that this invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of this invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive”, unless the context clearly indicates otherwise. The structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way, unless the context clearly indicates otherwise.
Claims
1. A double-sided packaging structure, characterized in that, include: The substrate comprises a non-filter chip, a back-side electronic component, a first molding compound, and a second molding compound. The substrate has a front side and a back side. The first molding compound encapsulates the non-filter chip on the front side of the substrate. The first molding compound is formed by a transfer molding process. The second molding compound encapsulates the back-side electronic component on the back side of the substrate. The back-side electronic component includes a filter chip.
2. The double-sided packaging structure as described in claim 1, characterized in that, The second encapsulation is a combination of a black film or a white film and a compression molding process, wherein the white film covers the surface of the back electronic component, and the compression molding process encapsulation covers the white film.
3. The double-sided packaging structure as described in claim 1, characterized in that, The double-sided packaging structure also includes a stamp, which is disposed on the front side of the substrate and spaced apart from the non-filter chip.
4. The double-sided packaging structure as described in claim 1, characterized in that, The thickness of the first molding compound is less than or equal to 150 μm.
5. The double-sided packaging structure as described in claim 1, characterized in that, The double-sided packaging structure further includes conductive pillars and solder balls. The conductive pillars are located on the back side of the substrate and spaced apart from the back side electronic components, and the solder balls are located on the surface of the conductive pillars away from the substrate.
6. The double-sided packaging structure as described in claim 5, characterized in that, The height of the conductive pillar is greater than the height of the back electronic component.
7. The double-sided packaging structure as described in claim 1, characterized in that, The back-side electronic component also includes a resistive capacitor, and there is a cavity between the back-side electronic component and the substrate.
8. The double-sided packaging structure as described in claim 1, characterized in that, The number of the back-side electronic components and the non-filter chip is at least one.
9. The double-sided packaging structure as described in claim 1, characterized in that, There is a cavity between the non-filter chip and the substrate, and the first molding compound fills the cavity between the non-filter chip and the substrate.
10. The double-sided packaging structure as described in claim 1, characterized in that, The non-filter chip is a flip-chip.