Adjustment circuit and image sensor

Abstract

The application discloses an adjusting circuit and an image sensor. The adjusting circuit comprises a temperature detection module and an adjusting control module. The temperature detection module is configured to output a corresponding first control signal to the adjusting control module according to a current temperature. The adjusting control module is configured to output a corresponding first adjusting voltage to a voltage-controlled oscillator of a phase-locked loop according to the first control signal, so that the voltage-controlled oscillator adjusts a frequency adjusting voltage generated by the voltage-controlled oscillator based on the first adjusting voltage, so that the adjusted frequency adjusting voltage is in or tends to be in a set voltage range. In this way, the phase-locked loop can make the generated frequency adjusting voltage be in or tend to be in the available voltage range at various temperatures, so as to avoid the situation that the tuned frequency of the phase-locked loop exceeds the normal tuning range, and ensure that the phase-locked loop can work normally.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and in particular to an adjustment circuit and an image sensor. Background Technology

[0002] In the operation of a phase-locked loop (such as a low-jitter clock phase-locked loop LCPLL), the frequency adjustment voltage is linearly related to the tuning frequency, and the tuning frequency can be guaranteed to be within the normal tuning range within the available voltage range corresponding to the frequency adjustment voltage.

[0003] When the temperature fluctuates significantly in the operating environment of a phase-locked loop (PLL), the frequency adjustment voltage may deviate from the usable voltage range, causing the tuning frequency to exceed the normal tuning range and resulting in malfunctions in the PLL. Therefore, preventing the frequency adjustment voltage in the PLL from deviating from the usable voltage range under large temperature variations is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] The purpose of this application is to provide an adjustment circuit and an image sensor that enables the phase-locked loop (PLL) to maintain the frequency adjustment voltage within or close to the usable voltage range under various temperatures, thereby preventing the PLL tuning frequency from exceeding the normal tuning range and ensuring that the PLL can work normally.

[0005] To achieve the above objectives:

[0006] In a first aspect, embodiments of this application provide an adjustment circuit, including: a temperature detection module and an adjustment control module; the temperature detection module is used to output a corresponding first control signal to the adjustment control module according to the current temperature; the adjustment control module is used to output a corresponding first adjustment voltage to the voltage-controlled oscillator of the phase-locked loop according to the first control signal, so that the voltage-controlled oscillator adjusts the frequency adjustment voltage it generates based on the first adjustment voltage, so that the adjusted frequency adjustment voltage is within or tends to be within a set voltage range.

[0007] Secondly, embodiments of this application provide an image sensor configured with an adjustment circuit and a phase-locked loop as described in any of the preceding claims.

[0008] The technical solution of this application can determine and output a corresponding adjustment voltage to the voltage-controlled oscillator of the phase-locked loop (PLL) based on the current temperature. This allows the PLL's voltage-controlled oscillator to adjust the frequency adjustment voltage it generates to be within or close to the usable voltage range based on the adjustment voltage. Thus, the technical solution of this application enables the PLL to maintain the frequency adjustment voltage generated within or close to the usable voltage range at various temperatures, thereby preventing the PLL tuning frequency from exceeding the normal tuning range and ensuring that the PLL can work normally. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0010] Figure 1 This is a structural diagram of the adjustment circuit provided in the embodiments of this application.

[0011] Figure 2 This is a first frame structure diagram of the temperature-sensing voltage generating unit exemplified in the second embodiment of this application.

[0012] Figure 3 This is a second frame structure diagram of the temperature-sensing voltage generating unit exemplified in the second embodiment of this application.

[0013] Figure 4 This is a circuit diagram of the temperature-sensing voltage generating unit as exemplified in the second embodiment of this application.

[0014] Figure 5 This is a circuit diagram of the comparator and signal output port in the temperature detection module of the second embodiment of this application.

[0015] Figure 6 This is a first connection structure diagram of the adjustment circuit exemplified in the second embodiment of this application.

[0016] Figure 7 This is a second connection structure diagram of the adjustment circuit exemplified in the second embodiment of this application.

[0017] Figure 8 This is a third connection structure diagram of the adjustment circuit exemplified in the second embodiment of this application.

[0018] Figure 9 This is a circuit diagram of a voltage-controlled oscillator with a phase-locked loop as exemplified in the second embodiment of this application.

[0019] Figure 10 This is a first flowchart illustrating the phase-locked loop control method provided in the embodiments of this application.

[0020] Figure 11 This is a second flowchart illustrating the phase-locked loop control method provided in the embodiments of this application.

[0021] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] It should be understood that although the terms first, second, third, etc., may be used in this document to describe various information, elements, units, or modules, these information, elements, units, or modules should not be limited to these terms. These terms are only used to distinguish information, elements, units, or modules of the same type from one another.

[0024] It should be noted that step designations such as S11 and S12 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S12 first and then S11, etc., but these should all be within the protection scope of this application.

[0025] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0026] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0027] First Embodiment

[0028] See Figure 1 This embodiment provides an adjustment circuit 100, including a temperature detection module 101 and an adjustment control module 102.

[0029] The temperature detection module 101 is used to output a first control signal corresponding to the current temperature to the adjustment control module 102.

[0030] The adjustment control module 102 is used to output a corresponding first adjustment voltage to the voltage-controlled oscillator 201 of the phase-locked loop 200 according to the first control signal, so that the voltage-controlled oscillator 201 adjusts the frequency adjustment voltage it generates based on the first adjustment voltage, so that the adjusted frequency adjustment voltage is within or tends to the set voltage range.

[0031] In one embodiment, the temperature detection module 101 can represent various devices or circuit structures that are capable of detecting temperature and outputting different signals (such as a first control signal) according to temperature changes.

[0032] In one embodiment, the adjustment control module 102 can characterize various devices or circuit structures that can select or generate a corresponding adjustment voltage (such as a first adjustment voltage) based on the control signal (such as a first control signal) output by the temperature detection module 101 that corresponds to the current temperature.

[0033] In one embodiment, after the voltage-controlled oscillator 201 of the phase-locked loop 200 receives the first adjustment voltage, it can increase or decrease the frequency adjustment voltage generated by controlling specific electrical components or specific circuit structures in the voltage-controlled oscillator 201 using the first adjustment voltage, so that the frequency adjustment voltage generated is within or tends to be within the set voltage range.

[0034] In another embodiment, after the voltage-controlled oscillator 201 of the phase-locked loop 200 receives the first adjustment voltage, it can replace the frequency adjustment voltage it generates with the first adjustment voltage so that the frequency adjustment voltage it ultimately generates is within or tends to the set voltage range.

[0035] In another embodiment, after the voltage-controlled oscillator 201 of the phase-locked loop 200 receives the first adjustment voltage, it can increase or decrease the frequency adjustment voltage by using the first adjustment voltage to perform positive or negative compensation on the frequency adjustment voltage it generates, so that the frequency adjustment voltage it ultimately generates is within or tends to the set voltage range.

[0036] It should be understood that the phase-locked loop 200 may be an environmental feature and not included in the aforementioned adjustment circuit 100; or the phase-locked loop 200 may be included in the aforementioned adjustment circuit 100 and be a part of the adjustment circuit 100.

[0037] In one embodiment, the phase-locked loop 200 (PLL) in the image sensor is a component used to generate a stable clock signal, which can ensure the synchronization and accuracy of image data. The voltage-controlled oscillator 201 in the PLL 200 can output at least one of the following: a frequency-adjustable voltage, a frequency-variable oscillation signal, or a high-frequency differential signal (or tuning frequency). The PLL 200 includes, but is not limited to, a low-jitter clock phase-locked loop 200 (LCPLL), an all-digital phase-locked loop 200 (ADPLL), etc.

[0038] In one embodiment, a frequency adjustment voltage is set within a voltage range to ensure that the phase-locked loop 200 maintains the tuning frequency within the normal tuning range at a specific temperature or within a specific temperature range.

[0039] Through the aforementioned technical solution, the adjustment circuit 100 can determine and output a corresponding adjustment voltage to the voltage-controlled oscillator 201 of the phase-locked loop 200 based on the current temperature. This allows the voltage-controlled oscillator 201 of the phase-locked loop 200 to adjust its generated frequency adjustment voltage to be within or approaching the usable voltage range based on the adjustment voltage. Thus, the technical solution of this embodiment enables the phase-locked loop 200 to maintain the generated frequency adjustment voltage within or approaching the usable voltage range under various temperatures, preventing the tuning frequency of the phase-locked loop 200 from exceeding the normal tuning range and ensuring the normal operation of the phase-locked loop 200.

[0040] Second Embodiment

[0041] See Figure 1 This embodiment provides an adjustment circuit 100, including a temperature detection module 101 and an adjustment control module 102.

[0042] The temperature detection module 101 is used to output a first control signal corresponding to the current temperature to the adjustment control module 102.

[0043] The adjustment control module 102 is used to output a corresponding first adjustment voltage to the voltage-controlled oscillator 201 of the phase-locked loop 200 according to the first control signal, so that the voltage-controlled oscillator 201 adjusts the frequency adjustment voltage it generates based on the first adjustment voltage, so that the adjusted frequency adjustment voltage is within or tends to the set voltage range.

[0044] The voltage within the set voltage range is used to ensure that the phase-locked loop 200 maintains the tuning frequency within the normal tuning range at a specific temperature or within a specific temperature range.

[0045] In one embodiment, see Figure 1 , Figure 4 and Figure 5The temperature detection module 101 includes a temperature sensing voltage generation unit 1011, a preset number of comparators, and a signal output port. Optionally, the preset number of comparators corresponds to the number of divided temperature ranges.

[0046] The temperature sensing voltage generating unit 1011 is used to output temperature sensing voltages of different values ​​according to temperature changes.

[0047] The comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to receive a reference voltage, the second input terminal is connected to a temperature sensing voltage unit to receive a temperature sensing voltage, and the output terminal is used to output a corresponding result signal according to the comparison result of the comparator.

[0048] The signal output port is used to determine the first control signal based on the result signals output by the preset number of comparators, and output it to the adjustment control module 102.

[0049] The temperature detection module 101 in the above technical solution can divide a large temperature range into multiple smaller temperature intervals by using a preset number of comparators. Each comparator corresponds to a preset temperature interval, and the current temperature can be determined to fall within a preset temperature interval based on the comparison result between the temperature sensing voltage and the reference voltage. Configuring the temperature detection module 101 with a preset number of comparators provides a flexible, accurate, and scalable solution for realizing the logic processing from temperature detection to control signal output.

[0050] In one embodiment, see Figure 2 The temperature sensing voltage generating unit 1011 includes a negative temperature coefficient voltage generating unit A2 and at least one mirror circuit A1. The mirror circuit A1 provides a constant current; the negative temperature coefficient voltage generating unit A2 receives the constant current and operates to generate a voltage inversely proportional to temperature as the temperature sensing voltage, and outputs the temperature sensing voltage to the second input terminal of each comparator.

[0051] In another embodiment, see Figure 3 The temperature sensing voltage generating unit 1011 includes a positive temperature coefficient voltage generating unit A2' and at least one mirror circuit A1. The mirror circuit A1 is used to provide a constant current; the positive temperature coefficient voltage generating unit A2' is used to receive the constant current to generate a voltage proportional to temperature as a temperature sensing voltage, and outputs the temperature sensing voltage to the second input terminal of each comparator.

[0052] Among them, the mirror circuit A1 can ensure that the working current received by the negative temperature coefficient voltage generating unit A2 or the positive temperature coefficient voltage generating unit A2' remains constant as the temperature rises, thereby enabling the temperature sensing voltage generating unit 1011 to accurately respond to temperature changes according to the design principle and output a temperature sensing signal that accurately reflects the temperature change.

[0053] In one embodiment, see Figure 4 At least one mirror circuit A1 includes a first mirror circuit A1a and a second mirror circuit A1b.

[0054] The first mirror circuit A1a includes a first transistor Q1 and a second transistor Q2; the source of the first transistor Q1 is grounded to GND, the drain of the first transistor Q1 receives the reference current Iin, and the gate of the first transistor Q1 receives the reference current Iin; the gate of the second transistor Q2 receives the reference current Iin and is connected to the gate of the first transistor Q1, and the source of the second transistor Q2 is grounded to GND.

[0055] The second mirror circuit A1b includes a third transistor Q3, a fourth transistor Q4, and a fifth transistor Q5. The drain of the third transistor Q3 is connected to the drain of the second transistor Q2, the source of the third transistor Q3 receives the power supply voltage VDD, and the gate of the third transistor Q3 is connected to the gate of the fourth transistor Q4 and the gate of the fifth transistor Q5. The source of the fourth transistor Q4 receives the power supply voltage VDD, and the drain of the fourth transistor Q4 outputs a constant current. The source of the fifth transistor Q5 receives the power supply voltage VDD, and the drain of the fifth transistor Q5 outputs a constant current.

[0056] The negative temperature coefficient voltage generating unit A2 includes a first transistor Q6, a second transistor Q7, a first resistor R1, a second resistor R2, a capacitor C1, and a voltage output terminal. The base of the first transistor Q6 is grounded to GND, the emitter of the first transistor Q6 is grounded to GND, the collector of the first transistor Q1 is connected to the drain of the fourth transistor Q4 through the first resistor R1 to receive a constant current, the base of the second transistor Q7 is connected between the collector of the first transistor Q1 and the first resistor R1, the emitter of the second transistor Q7 is grounded to GND and connected to the voltage output terminal through the capacitor C1, the collector of the second transistor Q7 is connected to the drain of the fifth transistor Q5 through the second resistor R2 to receive a constant current, and the collector of the second transistor Q7 is also connected to the voltage output terminal.

[0057] In this configuration, the first transistor Q1 and the second transistor Q2 are both NMOS transistors, while the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are all PMOS transistors.

[0058] In this circuit, the first mirror circuit A1a can copy the reference current Iin received by the drain of the first transistor Q1 to the branch corresponding to the second body transistor as a constant current input to the drain of the third transistor Q3 in the second mirror circuit A1b.

[0059] The second mirror circuit A1b can replicate the current received by the drain of the third transistor Q3 to the branches of the fourth transistor Q4 and the fifth transistor Q5, and use it as a constant current input to the negative temperature coefficient voltage generating unit A2.

[0060] Among them, the first mirror circuit A1a and the second mirror circuit A1b can ensure that the working current received by the negative temperature coefficient voltage generating unit A2 remains constant as the temperature rises, thereby enabling the temperature sensing voltage generating unit 1011 to accurately respond to temperature changes according to the design principle and output a temperature sensing signal that accurately reflects the temperature change.

[0061] Among them, as the temperature increases, the Vbe of the first transistor Q6 and the second transistor Q7 will decrease, thereby enabling the generation of a negative temperature coefficient voltage that is inversely proportional to the temperature coefficient.

[0062] Among them, the first resistor R1 and the second resistor R2 in the negative temperature coefficient voltage generating unit A2 can prevent the fourth transistor Q4 and the fifth transistor Q5 in the second mirror circuit A1b from being affected by the temperature sensing voltage output from the voltage output terminal, thus playing an isolation role. This ensures that the negative temperature coefficient voltage generating unit A2 can accurately respond to temperature changes according to the design principle and output a temperature sensing signal that accurately reflects the temperature change.

[0063] Among them, capacitor C1 in the negative temperature coefficient voltage generating unit A2 enables the voltage output terminal to be grounded to GND through capacitor C1, so as to ensure that the voltage output terminal can stably output the temperature sensing signal and play a role in voltage stabilization.

[0064] For example, see Figure 5 In the embodiment, the temperature adaptation range of the adjustment circuit 100 (the aforementioned larger temperature range) can be designed to be -40°C to 125°C, and the voltage-controlled oscillator 201 of the phase-locked loop 200 is designed with a base temperature of 25°C (i.e., the voltage within the set voltage range is used to ensure that the phase-locked loop 200 maintains the tuning frequency within the normal tuning range at a base temperature of 25°C); the temperature detection module 101 is designed to detect the temperature of 6 temperature ranges based on a base temperature of 25°C, and when the temperature range corresponding to the current temperature changes, the temperature detection module 101 will output different code values ​​as the first control signal; the 6 temperature ranges can be controlled by 6 comparators ( Figure 5 The comparators 0-5 in the system make the determination. The reference voltages received at the first input terminals of the six comparators correspond to the voltage values ​​of the temperature sensing signal vtempt under different temperature ranges, where:

[0065] At -40℃, the reference voltage corresponding to comparator 0 is Vin. <0> At 0℃, the reference voltage corresponding to comparator 1 is Vin. <1> The reference voltage corresponding to comparator 2 at 30℃ is Vin. <2> The reference voltage corresponding to comparator 3 at 60℃ is Vin. <3> At 90℃, the reference voltage corresponding to comparator 4 is Vin. <4> The reference voltage corresponding to comparator 5 at 120℃ is Vin. <5> ;

[0066] When the current temperature is below -40℃, the voltage value of the temperature sensing signal vtempt is greater than Vin. <0> Voltage value, Vin <1> Voltage value, Vin <2> Voltage value, Vin <3> Voltage value, Vin <4> Voltage value and Vin <5> The voltage value and the result signals of comparators 0 to 5 are all 0. At this time, the code value (i.e., temperature sensing signal) output by the temperature detection module 101 is 000000.

[0067] When the current temperature is greater than -40℃ and less than 0℃, the voltage value of the temperature sensing signal vtempt is less than Vin. <0> Voltage value, greater than Vin <1> Voltage value, Vin <2> Voltage value, Vin <3> Voltage value, Vin <4> Voltage value and Vin <5> The voltage value is such that the output signal of comparator 0 is 1, and the output signals of other comparators are 0. At this time, the code value (i.e., temperature sensing signal) output by temperature detection module 101 is 100000.

[0068] When the current temperature is greater than 0℃ and less than 30℃, the voltage value of the temperature sensing signal vtempt is less than Vin. <0> Voltage value and Vin <1> Voltage value, greater than Vin <2> Voltage value, Vin <3> Voltage value, Vin <4> Voltage value and Vin <5> The voltage value is such that the output signals of comparator 0 and comparator 1 are both 1, while the output signals of other comparators are 0. At this time, the code value (i.e., temperature sensing signal) output by temperature detection module 101 is 110000.

[0069] When the temperature is above 30℃ and below 60℃, the voltage value of the temperature sensing signal vtempt is less than Vin. <0> Voltage value, Vin <1> Voltage value and Vin <2> Voltage value, greater than Vin <3> Voltage value, Vin <4> Voltage value and Vin <5> The voltage value is such that the output signals of comparator 0, comparator 1 and comparator 2 are all 1, and the output signals of other comparators are 0. At this time, the code value (i.e. the temperature sensing signal) output by the temperature detection module 101 is 111000.

[0070] When the current temperature is greater than 60℃ and less than 90℃, the voltage value of the temperature sensing signal vtempt is less than Vin. <0> Voltage value, Vin <1> Voltage value, Vin <2> Voltage value and Vin <3> Voltage value, greater than Vin <4> Voltage value and Vin <5> The voltage value is such that the output signals of comparators 0, 1, 2 and 3 are all 1, while the output signals of other comparators are 0. At this time, the code value (i.e., temperature sensing signal) output by the temperature detection module 101 is 111100.

[0071] When the current temperature is greater than 90℃ and less than 120℃, the voltage value of the temperature sensing signal vtempt is less than Vin. <0> Voltage value, Vin <1> Voltage value, Vin <2> Voltage value, Vin <3> Voltage value and Vin <4> Voltage value, greater than Vin <5> The voltage value is such that the output signals of comparators 0, 1, 2, 3 and 4 are all 1, and the output signals of other comparators are 0. At this time, the code value (i.e. the temperature sensing signal) output by the temperature detection module 101 is 111110.

[0072] When the current temperature is greater than 120℃, the voltage value of the temperature sensing signal vtempt is less than Vin. <0> Voltage value, Vin <1> Voltage value, Vin <2> Voltage value, Vin <3> Voltage value, Vin <4> Voltage value and Vin <5> The voltage value, the output signals of comparators 0, 1, 2, 3, 4 and 5 are all 1, and the code value (i.e. the temperature sensing signal) output by the temperature detection module 101 is 111111.

[0073] In one embodiment, see Figure 6 The adjustment control module 102 includes a first selector 1022 and a reference voltage source 1021.

[0074] Among them, the reference voltage source 1021 is used to provide various reference voltages (e.g. Figure 6 (Reference voltages V1 to V7 in the system).

[0075] The first selector 1022 includes an enable terminal, an output terminal, and multiple input terminals, at least some of which are input terminals of the first selector 1022. Figure 6 (Seven input terminals are shown in the example) are used to receive the reference voltage provided by the reference voltage source 1021. The output terminal of the first selector 1022 is connected to the voltage-controlled oscillator 201. The enable terminal of the first selector 1022 is connected to the temperature detection module 101 so that the reference voltage received by the first input terminal is selected as the first adjustment voltage according to the first control signal output by the temperature detection module 101, and output to the voltage-controlled oscillator 201 through the output terminal.

[0076] In this device, at least some of the input terminals of the first selector 1022 receive different reference voltages, and the reference voltages received by at least some of the input terminals of the first selector 1022 are used to adjust the frequency adjustment voltage of the voltage-controlled oscillator 201 to be within or approach the set voltage range under different temperature ranges.

[0077] The aforementioned adjustment control module 102, through the first selector 1022 and the reference voltage source 1021, can construct a low-cost and easily implemented circuit structure. This allows it to determine and output a corresponding adjustment voltage to the voltage-controlled oscillator 201 of the phase-locked loop 200 based on the first control signal determined and output by the temperature detection module 101 in response to the current temperature. This ensures that the voltage-controlled oscillator 201 of the phase-locked loop 200 adjusts its generated frequency adjustment voltage to be within or approaching the usable voltage range. Thus, the technical solution of this embodiment enables the phase-locked loop 200 to maintain the generated frequency adjustment voltage within or approaching the usable voltage range at various temperatures, preventing the phase-locked loop 200's tuning frequency from exceeding the normal tuning range and ensuring the normal operation of the phase-locked loop 200.

[0078] In one embodiment, see Figure 7 The adjustment control module 102 also includes multiple second selectors 1023. Figure 7 Example: The seven inputs of the first selector 1022 are connected to seven second selectors 1023 respectively.

[0079] Among them, at least a portion of the input terminals of the first selector 1022 ( Figure 7 Example 7) The seven input terminals are connected to the reference voltage source 1021 through the second selector 1023 respectively, so as to receive the reference voltage through the second selector.

[0080] The second selector 1023 includes an enable terminal, an output terminal, and multiple input terminals. The input terminals of the second selector 1023 are connected to a reference voltage source 1021 to receive a reference voltage. The output terminal of the second selector 1023 is connected to the input terminal of the first selector 1022. The enable terminal of the second selector 1023 is used to receive a first enable signal to select the reference voltage received by one of the input terminals of the second selector 1023, and output it to the input terminal of the first selector 1022 through the output terminal of the second selector 1023.

[0081] The reference voltages received by the multiple input terminals of the second selector 1023 are different from each other, and at least one of the multiple reference voltages received by the second selector 1023 is used to adjust the frequency adjustment voltage of the voltage-controlled oscillator 201 to be within or approach the set voltage range under a temperature range.

[0082] The aforementioned adjustment control module 102, through a second selector 1023 connected to the input terminal of the first selector 1022, can, after determining the initial adjustment voltage based on the first control signal corresponding to a temperature range output by the temperature detection module 101, manually or automatically trigger the first enable signal of the second selector 1023 when the frequency adjustment voltage of the voltage-controlled oscillator 201 of the phase-locked loop 200 is over-compensated or under-compensated. This increases or decreases the reference voltage input to the first selector by the second selector 1023, thereby increasing or decreasing the frequency adjustment voltage output by the first selector 1022, so that the frequency adjustment voltage of the voltage-controlled oscillator 201 of the phase-locked loop 200 is within or approaches the usable voltage range. Thus, the technical solution of this embodiment can better ensure that the phase-locked loop 200 can maintain the generated frequency adjustment voltage within or approach the usable voltage range under various temperatures, preventing the tuning frequency of the phase-locked loop 200 from exceeding the normal tuning range, ensuring the normal operation of the phase-locked loop 200, and enhancing the flexibility and scalability of the adjustment circuit 100.

[0083] In one embodiment, see Figure 8 The adjustment control module 102 also includes a third selector 1024.

[0084] The third selector 1024 includes an enable terminal, an output terminal, and multiple input terminals. The input terminals of the third selector 1024 are connected to a reference voltage source 1021 to receive a reference voltage. The output terminal of the third selector 1024 is connected to a voltage-controlled oscillator 201. The enable terminal of the third selector 1024 is used to receive a second enable signal to select the reference voltage received by one of the input terminals of the third selector 1024 as a second adjustment voltage. The second adjustment voltage is output to the voltage-controlled oscillator 201 through the output terminal of the third selector 1024, so that the voltage-controlled oscillator 201 adjusts the frequency adjustment voltage it generates based on the first adjustment voltage and the second adjustment voltage, so that the adjusted frequency adjustment voltage is within or tends to be within a set voltage range.

[0085] In particular, the reference voltages received by the multiple input terminals of the third selector 1024 are different from each other.

[0086] When the third selector 1024 is configured in the above-mentioned adjustment control module 102, the first selector 1022 and the second selector 1023 can output the first adjustment voltage and the second adjustment voltage to the voltage-controlled oscillator 201 respectively according to the second enable signal of the third selector 1024 triggered manually or automatically. This allows the frequency adjustment voltage of the voltage-controlled oscillator 201 to be adjusted in combination (e.g., a combination of fine adjustment and coarse adjustment) through the first adjustment voltage and the second adjustment voltage, so that the frequency adjustment voltage of the phase loop voltage-controlled oscillator 201 can be better within or approach the usable voltage range.

[0087] In one embodiment, see Figure 9 The voltage-controlled oscillator 201 of the phase-locked loop 200 includes a resonant circuit 2011, a negative resistance module 2012, and a tail current source 2013.

[0088] The resonant circuit 2011 includes an inductor L1, a first adjustable capacitor C2, and a second adjustable capacitor C3. The first adjustable capacitor C2 and the second adjustable capacitor C3 are connected in series and then connected in parallel with the inductor L1. Both the first adjustable capacitor C2 and the second adjustable capacitor C3 receive a first adjustment voltage output by the adjustment control module 102, which is used to increase or decrease the voltage of the high-impedance node formed by the resonant circuit 2011 to obtain the adjusted frequency adjustment voltage.

[0089] The resonant circuit 2011 is used to generate and output a differential high-frequency signal (i.e., tuning frequency) by adjusting the voltage according to the frequency generated by the high-impedance node it forms.

[0090] The first adjustable capacitor C2 and the second adjustable capacitor C3 change their capacitance values ​​by changing the first adjustment voltage, so that the frequency adjustment voltage generated by the high impedance node formed by the resonant circuit 2011 is within or tends to the set voltage range, thereby making the differential high frequency signal (i.e. the tuning frequency) output by the resonant circuit 2011 tend to or be within the normal tuning range.

[0091] Thus, after receiving the first adjustment voltage, the resonant circuit 2011 in the voltage-controlled oscillator 201 of the phase-locked loop 200 can increase or decrease the frequency adjustment voltage generated by the high-impedance node formed by the resonant circuit 2011 by controlling the adjustable capacitor in the resonant circuit 2011 using the first adjustment voltage. This ensures that the frequency adjustment voltage ultimately generated by the voltage-controlled oscillator 201 of the phase-locked loop 200 is within or approaches the set voltage range. Therefore, the technical solution of this embodiment enables the phase-locked loop 200 to maintain the generated frequency adjustment voltage within or approach the usable voltage range under various temperatures, preventing the tuning frequency of the phase-locked loop 200 from exceeding the normal tuning range and ensuring the normal operation of the phase-locked loop 200.

[0092] In one embodiment, the resonant circuit 2011 may further include a first isolation capacitor C4, a second isolation capacitor C5, a first signal output terminal outn, and a second signal output terminal outp.

[0093] The first adjustable capacitor C2 is connected to the first signal output terminal outn through the first isolation capacitor C4;

[0094] The second adjustable capacitor C3 is connected to the second signal output terminal outp through the second isolation capacitor C5.

[0095] The first isolation capacitor C4 is used to isolate the high-frequency signal output from the first signal output terminal outn from the first adjustable capacitor C2.

[0096] The second isolation capacitor C5 is used to isolate the high-frequency signal output from the second signal output terminal outp from the second adjustable capacitor C3.

[0097] By configuring the first isolation capacitor C4 and the second isolation capacitor C5 in the resonant circuit 2011, isolation from the signal output terminal can be achieved, avoiding the frequency adjustment voltage in the resonant circuit 2011 from being affected, thereby making the tuning accuracy of the voltage-controlled oscillator 201 of the phase-locked loop 200 higher.

[0098] In one embodiment, the resonant circuit 2011 may further include a first isolation resistor R3 and a second isolation resistor R4.

[0099] The first isolation resistor R3 and the second isolation resistor R4 are connected in series with the first isolation capacitor C4 and the second isolation capacitor C5. The first isolation resistor R3 and the second isolation resistor R4 are connected in parallel with the first adjustable capacitor C2 and the second adjustable capacitor C3.

[0100] The first isolation resistor R3 and the second isolation resistor R4 are located at the high-impedance node and are used to isolate the adjusted frequency adjustment voltage from the high-frequency signals output by the first signal output terminal outn and the second signal output terminal outp, respectively.

[0101] By configuring the first isolation resistor R3 and the second isolation resistor R4 in the resonant circuit 2011, the frequency adjustment voltage generated by the high-impedance node of the resonant circuit 2011 can be isolated from the signal output terminal, effectively preventing the frequency adjustment voltage in the resonant circuit 2011 from being affected, thereby making the tuning accuracy of the voltage-controlled oscillator 201 of the phase-locked loop 200 higher.

[0102] In one embodiment, the resonant circuit 2011 may further include a third adjustable capacitor C6 and a fourth adjustable capacitor C7.

[0103] The third adjustable capacitor C6 and the fourth adjustable capacitor C7 are connected in series, and then connected in parallel with the first adjustable capacitor C2 and the second adjustable capacitor C3. Both the third adjustable capacitor C6 and the fourth adjustable capacitor C7 receive the second adjustment voltage output by the adjustment control module 102, which is used to increase or decrease the voltage of the high-impedance node formed by the resonant circuit 2011 to obtain the adjusted frequency adjustment voltage.

[0104] Among them, the third adjustable capacitor C6 and the fourth adjustable capacitor C7 change their own capacitance values ​​by changing the second adjustment voltage, thereby cooperating with the first adjustable capacitor C2 and the second adjustable capacitor C3 to make the frequency adjustment voltage generated by the resonant circuit 2011 be within or approach the set voltage range, and thus make the tuning frequency output by the resonant circuit 2011 approach or be within the normal tuning range.

[0105] Thus, after receiving the first adjustment voltage and the second adjustment voltage, the resonant circuit 2011 in the voltage-controlled oscillator 201 of the phase-locked loop 200 can control the adjustable capacitor in the resonant circuit 2011 by using the combination of the first and second adjustment voltages. This allows the frequency adjustment voltage generated by the high-impedance node formed by the resonant circuit 2011 to increase or decrease, ensuring that the final frequency adjustment voltage generated by the voltage-controlled oscillator 201 of the phase-locked loop 200 is within or approaches a set voltage range. Therefore, the technical solution of this embodiment enables the phase-locked loop 200 to maintain the generated frequency adjustment voltage within or approach a usable voltage range at various temperatures, preventing the tuning frequency of the phase-locked loop 200 from exceeding the normal tuning range and ensuring the normal operation of the phase-locked loop 200.

[0106] The negative resistance module 2012 is used to cancel the impedance in the resonant circuit 2011, so as to avoid the impedance in the resonant circuit 2011 reducing the differential high-frequency signal (i.e., the tuning frequency) generated by it.

[0107] In one embodiment, the negative resistance module 2012 includes a sixth transistor Q8 and a seventh transistor Q9.

[0108] In this configuration, the gate of the sixth transistor Q8 is connected to the second signal output terminal outp, the drain of the sixth transistor Q8 is connected to the first signal output terminal outn, and the source of the sixth transistor Q8 is connected to the tail current source 2013.

[0109] In this configuration, the gate of the seventh transistor Q9 is connected to the first signal output terminal outn, the drain of the seventh transistor Q9 is connected to the second signal output terminal outp, and the source of the seventh transistor Q9 is connected to the tail current source 2013.

[0110] The tail current source 2013 is used to provide current to the resonant circuit 2011 and the negative resistance module 2012.

[0111] Since the resonant circuit 2011 (or LC oscillator) consumes resonant energy during oscillation, causing signal attenuation, the impedance in the resonant circuit 2011 is offset by the negative resistance circuit composed of the sixth transistor Q8 and the seventh transistor Q9 configured in the negative resistance module 2012, so that the signal output by the resonant circuit 2011 will not be attenuated.

[0112] Based on the same inventive concept as the foregoing embodiments, the foregoing embodiments will be illustrated by a specific application scenario below:

[0113] The adjustment circuit 100 provided in this example (such as...) Figure 7 The temperature range of the circuit (shown) can be designed to be from -40℃ to 125℃. The voltage-controlled oscillator 201 of the low-jitter clock phase-locked loop (hereinafter referred to as LCPLL) is designed with a reference temperature of 25℃ (i.e., the voltage within the set voltage range is used to keep the LCPLL tuning frequency within the normal tuning range at a reference temperature of 25℃). The temperature detection module 101 is designed to detect the temperature of 6 temperature ranges based on a reference temperature of 25℃. When the temperature range corresponding to the current temperature changes, the temperature detection module 101 will output different code values ​​as the first control signal.

[0114] Among them, the 6 temperature ranges can be controlled by 6 comparators ( Figure 5 The comparators 0 to 5 in the system make the determination. The reference voltages received at the first input terminals of the six comparators correspond to the voltage values ​​of the temperature sensing signal vtempt under different temperature ranges.

[0115] In some implementations, when the temperature of the LCPLL's operating environment changes, without intervention, the actual tuning range corresponding to the differential high-frequency signal output by the LCPLL's inductor-capacitor voltage-controlled oscillator 201 (LCVCO) will differ from the normal tuning range, causing the LCPLL to malfunction. Therefore, in this example, when the temperature of the LCPLL's operating environment changes, the temperature detection module 101 in the adjustment circuit 100 outputs a different first control signal, which in turn controls the adjustment control module 102 to change the output first adjustment signal. This adjusts the actual tuning range corresponding to the differential high-frequency signal output by the LCPLL's inductor-capacitor voltage-controlled oscillator 201 (LCVCO) to the normal tuning range corresponding to a room temperature of 25°C, ensuring that the LCPLL can operate normally.

[0116] Furthermore, if the first adjustment signal output by the adjustment control module 102 causes the inductor-capacitor voltage-controlled oscillator 201 (LCVCO) to over-compensate or under-compensate, correction can be performed using either of the following two adjustment methods, or a combination of the following two adjustment methods:

[0117] (1) First adjustment method (can achieve fine-tuning):

[0118] The first enable signal of the second selector 1023 connected to the first selector 1022 in the adjustment control module 102 is manually adjusted to reduce the reference voltage (i.e., the first adjustment voltage) transmitted to the output terminal of the first selector 1022. This is to address the overcompensation of the inductor-capacitor voltage-controlled oscillator 201 (LCVCO). Alternatively, the first enable signal of the second selector 1023 connected to the first selector 1022 in the adjustment control module 102 is manually adjusted to increase the reference voltage (i.e., the first adjustment voltage) transmitted to the output terminal of the first selector 1022. This is to address the undercompensation of the inductor-capacitor voltage-controlled oscillator 201 (LCVCO). Ultimately, the actual tuning range corresponding to the differential high-frequency signal output by the LCPLL's inductor-capacitor voltage-controlled oscillator 201 (LCVCO) is adjusted to the normal tuning range corresponding to a room temperature of 25°C, ensuring that the LCPLL can operate normally.

[0119] (2) First adjustment method (can achieve fine-tuning and coarse-tuning):

[0120] The second enable signal of the third selector 1024 in the adjustment control module 102 is manually adjusted to reduce the second adjustment voltage output by the adjustment control module 102. This reduces the second adjustment voltage and the first adjustment voltage output by the adjustment control module 102 to address the overcompensation of the inductor-capacitor voltage-controlled oscillator 201 (LCVCO). Alternatively, the second enable signal of the third selector 1024 in the adjustment control module 102 is manually adjusted to increase the second adjustment voltage output by the adjustment control module 102. This reduces the second adjustment voltage and the first adjustment voltage output by the adjustment control module 102 to address the undercompensation of the inductor-capacitor voltage-controlled oscillator 201 (LCVCO). Ultimately, this adjusts the actual tuning range of the differential high-frequency signal output by the LCPLL's inductor-capacitor voltage-controlled oscillator 201 (LCVCO) to the normal tuning range at room temperature (25°C) to ensure the LCPLL can operate normally.

[0121] The adjustment control module 102, configured with the second selector 1023 and / or the third selector 1024, enables manual adjustment. The combination of the temperature detection module 101 and the first selector 1022 in the adjustment control module 102 enables adaptive adjustment. Furthermore, the adjustment circuit 100 provided in this example can integrate manual adjustment mode into adaptive adjustment mode to better adjust the actual tuning range corresponding to the differential high-frequency signal output by the LCPLL's inductor-capacitor voltage-controlled oscillator 201 (LCVCO) to the normal tuning range at room temperature (25°C), ensuring the LCPLL functions normally.

[0122] Thus, the technical solution of this example provides an adjustment circuit 100, which can adjust the actual tuning range of the differential high-frequency signal output by the LCPLL's inductor-capacitor voltage-controlled oscillator 201 (LCVCO) to the normal tuning range corresponding to the ambient temperature of 25°C when the temperature of the LCPLL's working environment changes. This ensures that the LCPLL can still work normally when the temperature of the working environment changes significantly.

[0123] Based on the same inventive concept as the foregoing embodiments, this application provides an image sensor configured with an adjustment circuit and a phase-locked loop as described in the first or second embodiment above.

[0124] See Figure 10 This application also provides a control method for a phase-locked loop, including the following steps:

[0125] S11: Detect the current temperature;

[0126] S12: Determine and output a first adjustment voltage to the voltage-controlled oscillator of the phase-locked loop based on the current temperature, so that the voltage-controlled oscillator adjusts the frequency adjustment voltage it generates based on the first adjustment voltage, so that the adjusted frequency adjustment voltage is within or tends to the set voltage range.

[0127] In one embodiment, see Figure 11 The phase-locked loop control method further includes the step: S13: in response to a manual setting operation, determining and outputting a second adjustment voltage to the voltage-controlled oscillator of the phase-locked loop, such that the voltage-controlled oscillator adjusts its generated frequency adjustment voltage based on the first adjustment voltage and / or the second adjustment voltage, so that the adjusted frequency adjustment voltage is within or tends to be within the set voltage range.

[0128] This application also provides a control method for a phase-locked loop (PLL), which can determine and output a corresponding adjustment voltage to the voltage-controlled oscillator (VCO) of the PLL based on the current temperature. This allows the VCO to adjust the frequency adjustment voltage generated by the PLL to be within or approach the usable voltage range based on the adjustment voltage. Thus, the technical solution of this embodiment enables the PLL to maintain the generated frequency adjustment voltage within or approach the usable voltage range at various temperatures, preventing the PLL tuning frequency from exceeding the normal tuning range and ensuring the normal operation of the PLL.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An adjustment circuit, characterized in that, include: Temperature detection module and adjustment control module; The temperature detection module is used to output a corresponding first control signal to the adjustment control module according to the current temperature; The adjustment control module is used to output a corresponding first adjustment voltage to the voltage-controlled oscillator of the phase-locked loop according to the first control signal, so that the voltage-controlled oscillator adjusts the frequency adjustment voltage it generates based on the first adjustment voltage, so that the adjusted frequency adjustment voltage is within or tends to a set voltage range.

2. The adjustment circuit according to claim 1, characterized in that, The adjustment control module includes a first selector and a reference voltage source; The reference voltage source is used to provide multiple reference voltages; The first selector includes an enable terminal, an output terminal, and multiple input terminals. At least a portion of the input terminals of the first selector are used to receive a reference voltage provided by the reference voltage source. The output terminal of the first selector is connected to the voltage-controlled oscillator. The enable terminal of the first selector is connected to the temperature detection module to select a reference voltage received by the input terminal as the first adjustment voltage according to the first control signal output by the temperature detection module, and output it to the voltage-controlled oscillator through the output terminal. Wherein, at least some of the input terminals of the first selector receive different reference voltages, and the reference voltages received by at least some of the input terminals of the first selector are used to adjust the frequency adjustment voltage of the voltage-controlled oscillator to be within or tend to be within a set voltage range under different temperature ranges.

3. The adjustment circuit according to claim 2, characterized in that, The adjustment control module also includes multiple second selectors; At least a portion of the input terminals of the first selector are connected to the reference voltage source via the second selector, so as to receive the reference voltage through the second selector; The second selector includes an enable terminal, an output terminal, and multiple input terminals. The input terminals of the second selector are connected to the reference voltage source to receive a reference voltage. The output terminal of the second selector is connected to the input terminal of the first selector. The enable terminal of the second selector is used to receive a first enable signal to select the reference voltage received by one of the input terminals of the second selector, and outputs it to the input terminal of the first selector through the output terminal of the second selector. In this process, the reference voltages received by the multiple input terminals of the second selector are different from each other, and at least one of the multiple reference voltages received by the second selector is used to adjust the frequency adjustment voltage of the voltage-controlled oscillator to be within or tend to be within a set voltage range under a temperature range.

4. The adjustment circuit according to claim 2, characterized in that, The adjustment control module also includes a third selector; The third selector includes an enable terminal, an output terminal, and multiple input terminals. The input terminals of the third selector are connected to the reference voltage source to receive a reference voltage. The output terminal of the third selector is connected to the voltage-controlled oscillator. The enable terminal of the third selector is used to receive a second enable signal to select the reference voltage received by one of the input terminals of the third selector as a second adjustment voltage. The voltage-controlled oscillator is output to the voltage-controlled oscillator through the output terminal of the third selector, so that the voltage-controlled oscillator adjusts the frequency adjustment voltage it generates based on the first adjustment voltage and the second adjustment voltage, so that the adjusted frequency adjustment voltage is within or tends to be within a set voltage range. In this third selector, the reference voltages received by the multiple input terminals are different from each other.

5. The adjustment circuit according to claim 1, characterized in that, The temperature detection module includes a temperature sensing voltage generation unit, a preset number of comparators, and a signal output port. The temperature sensing voltage generating unit is used to output temperature sensing voltages of different values ​​according to temperature changes; The comparator includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to receive a reference voltage, the second input terminal is connected to the temperature sensing voltage unit to receive the temperature sensing voltage, and the output terminal is used to output a corresponding result signal according to the comparison result of the comparator. The signal output port is used to determine the first control signal based on the result signals output by the preset number of comparators, and output it to the adjustment control module.

6. The adjustment circuit according to claim 5, characterized in that, The preset number of the comparators corresponds to the number of temperature ranges to be divided.

7. The adjustment circuit according to claim 5, characterized in that, The temperature sensing voltage generating unit includes a negative temperature coefficient voltage generating unit and at least one mirror circuit. The mirror circuit is used to provide a constant current; The negative temperature coefficient voltage generating unit is used to receive the constant current to generate a voltage that is inversely proportional to the temperature as the temperature sensing voltage, and outputs the temperature sensing voltage to the second input terminal of each of the comparators.

8. The adjustment circuit according to claim 7, characterized in that, At least one of the mirror circuits includes a first mirror circuit and a second mirror circuit; The first mirror circuit includes a first transistor and a second transistor; the source of the first transistor is grounded, the drain of the first transistor receives a reference current, and the gate of the first transistor receives the reference current; the gate of the second transistor receives the reference current and is connected to the gate of the first transistor, and the source of the second transistor is grounded. The second mirror circuit includes a third transistor, a fourth transistor, and a fifth transistor; the drain of the third transistor is connected to the drain of the second transistor, the source of the third transistor receives a power supply voltage, and the gate of the third transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor. The source of the fourth transistor receives the power supply voltage, and the drain of the fourth transistor outputs the constant current; the source of the fifth transistor receives the power supply voltage, and the drain of the fifth transistor outputs the constant current. The negative temperature coefficient voltage generating unit includes a first transistor, a second transistor, a first resistor, a second resistor, a capacitor, and a voltage output terminal. The base of the first transistor is grounded, the emitter of the first transistor is grounded, and the collector of the first transistor is connected to the drain of the fourth transistor through the first resistor to receive the constant current. The base of the second transistor is connected between the collector of the first transistor and the first resistor. The emitter of the second transistor is grounded and connected to the voltage output terminal through the capacitor. The collector of the second transistor is connected to the drain of the fifth transistor through the second resistor to receive the constant current. The collector of the second transistor is also connected to the voltage output terminal. The first and second transistors are both NMOS transistors, while the third, fourth, and fifth transistors are all PMOS transistors.

9. The adjustment circuit according to claim 1, characterized in that, The voltage within the specified voltage range is used to ensure that the phase-locked loop maintains the tuning frequency within the normal tuning range at a specific temperature or within a specific temperature range.

10. The adjustment circuit according to any one of claims 1 to 9, characterized in that, The voltage-controlled oscillator of the phase-locked loop includes a resonant circuit, a negative resistance module, and a tail current source; The resonant circuit includes an inductor, a first adjustable capacitor, and a second adjustable capacitor. The first and second adjustable capacitors are connected in series and then in parallel with the inductor. Both the first and second adjustable capacitors receive the first adjustment voltage output by the adjustment control module to increase or decrease the voltage of the high-impedance node formed by the resonant circuit to obtain the adjusted frequency adjustment voltage. The resonant circuit is used to generate and output a differential high-frequency signal based on the frequency adjustment voltage generated by the high-impedance node it forms. The negative resistance module is used to cancel the impedance within the resonant circuit; The tail current source is used to provide current to the resonant circuit and the negative resistance module.

11. The adjustment circuit according to claim 10, characterized in that, The resonant circuit also includes a first isolation capacitor, a second isolation capacitor, a first signal output terminal, and a second signal output terminal; The first adjustable capacitor is connected to the first signal output terminal through the first isolation capacitor; The second adjustable capacitor is connected to the second signal output terminal through the second isolation capacitor; The first isolation capacitor is used to isolate the high-frequency signal output from the first signal output terminal from the first adjustable capacitor. The second isolation capacitor is used to isolate the high-frequency signal output from the second signal output terminal from the second adjustable capacitor.

12. The adjustment circuit according to claim 11, characterized in that, The resonant circuit also includes a first isolation resistor and a second isolation resistor; The first isolation resistor and the second isolation resistor are connected in series with the first isolation capacitor and the second isolation capacitor, and the first isolation resistor and the second isolation resistor are connected in parallel with the first adjustable capacitor and the second adjustable capacitor. The first isolation resistor and the second isolation resistor are located at the high-impedance node and are used to isolate the adjusted frequency adjustment voltage from the high-frequency signals output by the first signal output terminal and the second signal output terminal, respectively.

13. The adjustment circuit according to claim 10, characterized in that, The resonant circuit also includes a third adjustable capacitor and a fourth adjustable capacitor. The third and fourth adjustable capacitors are connected in series and then connected in parallel with the first and second adjustable capacitors. Both the third and fourth adjustable capacitors receive the second adjustment voltage output by the adjustment control module to increase or decrease the voltage of the high-impedance node formed by the resonant circuit to obtain the adjusted frequency adjustment voltage.

14. An image sensor, characterized in that, It is equipped with an adjustment circuit and a phase-locked loop as described in any one of claims 1 to 13.

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